Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62157G/CY62157GE MoBL
8-Mbit (512K × 16-bits) Static RAM with
Error-Correcting Code (ECC)
CY62157G/CY62157GE MoBL, 8-Mbit (512K × 16-bits) Static RAM with Error-Correcting Code (ECC)
Features
Functional Description
■
Ultra-low standby current
❐ Typical standby current: 1.4 µA
❐ Maximum standby current: 6.5 µA
CY62157G and CY62157GE are high-performance CMOS
low-power (MoBL®) SRAM device with Embedded
Error-Correcting Code. ECC logic can detect and correct single
bit error in accessed location.
■
High speed: 45 ns
■
Voltage range: 1.65 V to 3.6 V
■
Embedded Error-Correcting Code (ECC) for single-bit error
correction
■
1.0 V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Available in Pb-free 48-ball VFBGA, 44-TSOP II and 48-pin
TSOP I packages
This device is offered in dual chip enable option. Dual chip
enable devices are accessed by asserting both chip enable
inputs – CE1 as LOW and CE2 as HIGH.
Data writes are performed by asserting the Write Enable input
(WE LOW), and providing the data and address on device data
(I/O0 through I/O15) and address (A0 through A18) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O0 through I/O15). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high impedance state
when the device is deselected (CE1 HIGH/CE2 LOW for dual
chip enable device), or control signals are de-asserted (OE, BLE,
BHE).
These devices also have a unique “Byte Power down” feature,
where, if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
The CY62157G and CY62157GE devices are available in a
Pb-free 48-ball VFBGA, 44-TSOP II and 48-pin TSOP I
packages. See the Logic Block Diagram – CY62157G on page 2.
The device in the 48-pin TSOP I package can also be configured
to function as a 1M × 8-bit device. See the Pin Configurations on
page 5.
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V)
Operating ICC, (mA)
Speed (ns)
f = fmax
Standby, ISB2 (µA)
Typ[1]
Max
Typ[1]
Max
CY62157G18
Industrial
1.65 V–2.2 V
55
18
22
2.0
8
CY62157G30
Industrial
2.2 V–3.6 V
45
18
25
1.4
6.5
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V) and
VCC = 1.8V (for VCC range of 1.65 V–2.2 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 002-27323 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 28, 2020
CY62157G/CY62157GE MoBL
Logic Block Diagram – CY62157G
ECC DECODER
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DATAIN DRIVERS
SENSE
AMPLIFIERS
ECC ENCODER
512K x 16
RAM ARRAY
I/O0-I/O7
I/O8-I/O15
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN DECODER
CE
POWER DOWN
CIRCUIT
BYTE
BHE
BHE
BLE
WE
CE2
OE
CE1
BLE
Logic Block Diagram – CY62157GE
ECC DECODER
512K x 16
RAM ARRAY
DATA IN
DRIVERS
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
ERR
I/O 0 -I/O 7
I/O 8 -I/O 15
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUM N
DECODER
POW ER
DOW N
CIRCUIT
Document Number: 002-27323 Rev. *C
CE 2
CE 1
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE 2
CE 1
Page 2 of 23
CY62157G/CY62157GE MoBL
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 11
Truth Table – CY62157G/CY62157GE ........................... 16
ERR Output – CY62157GE ............................................. 16
Document Number: 002-27323 Rev. *C
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 3 of 23
CY62157G/CY62157GE MoBL
Pin Configurations
Figure 1. 48-ball VFBGA Pinout (Top View)[2]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
I/O8
BHE
A3
A4
CE1
I/O9
I/O10
A5
A6
A17
Figure 2. 48-ball VFBGA Pinout (with ERR (Top View))[2]
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
CE2
A
I/O0
B
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O1
I/O2
C
I/O9
I/O10
A5
A6
I/O1
I/O2
C
A7
I/O3
VCC
D
VSS
I/O11
A17
A7
I/O3
VCC
D
NC
A16
I/O4
VSS
E
VCC
I/O12 ERR
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O14 I/O13 A14
A15
I/O5
I/O6
F
VSS I/O11
VCC
I/O12
I/O15
NC
A12
A13
WE
I/O7
G
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
A18
A8
A9
A10
A11
NC
H
Figure 3. 44-pin TSOP II Pinout (Top View)[2]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Note
2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 002-27323 Rev. *C
Page 4 of 23
CY62157G/CY62157GE MoBL
Pin Configurations (continued)
Figure 4. 48-pin TSOP I Pinout (Top View)[3, 4]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Figure 5. 48-pin TSOP I Pinout (with ERR (Top View))[3, 4]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
ERR
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. Tie the BYTE pin in the 48-pin TSOP I package to VCC to use the device as a 512K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1M × 8 SRAM
by tying the BYTE signal to VSS. In the 1M × 8 configuration, Pin 45 is the extra address line A19, while BHE, BLE, and I/O8 to I/O14 pins are not used and can be
left floating.
Document Number: 002-27323 Rev. *C
Page 5 of 23
CY62157G/CY62157GE MoBL
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage (HBM)
(MIL-STD-883, Method 3015) ................................. >2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current ..................................................... >140 mA
Storage temperature ............................... –65 °C to + 150 °C
Operating Range
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Grade
Supply voltage
to ground potential .............................. –0.2 V to VCC + 0.3 V
Industrial
Ambient Temperature
VCC
–40 °C to +85 °C
1.65 V to 2.2 V
2.2 V to 3.6 V
DC voltage applied to outputs
in High Z state[5] .................................. –0.2 V to VCC + 0.3 V
DC input voltage[5] .............................. –0.2 V to VCC + 0.3 V
DC Electrical Characteristics
Over the Operating Range of –40 °C to 85 °C
Parameter
VOH
VOL
Description
Output HIGH
voltage
Output LOW
voltage
45/55 ns
Test Conditions
Min
Typ[6]
Max
1.4
–
–
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2
–
–
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
2.4
–
–
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
–
–
0.4
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
VIH
VIL
Input HIGH
voltage
Input LOW
voltage[6]
V
–
–
0.4
1.65 V to 2.2 V –
1.4
–
VCC + 0.2
2.2 V to 2.7 V –
1.8
–
VCC + 0.3
2.7 V to 3.6 V –
2
–
VCC + 0.3
1.65 V to 2.2 V –
–0.2
–
0.4
2.2 V to 2.7 V –
–0.3
–
0.6
2.7 V to 3.6 V –
–0.3
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
f = 22.22 MHz
(45 ns)
–
18
25
f = 18.18 MHz
(55 ns)
–
18
22
f = 1 MHz
–
6
7
–
1.4
6.5
ICC
ISB1[7]
VCC operating supply current
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
Automatic power down
current – CMOS inputs;
VCC = 1.65 to 2.2 V
VCC = Max, IOUT = 0 mA,
CMOS levels
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
Unit
V
V
V
µA
mA
µA
–
2.0
8.0
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V) and
VCC = 1.8V (for VCC range of 1.65 V–2.2 V), TA = 25 °C.
7. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
8. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 002-27323 Rev. *C
Page 6 of 23
CY62157G/CY62157GE MoBL
DC Electrical Characteristics (continued)
Over the Operating Range of –40 °C to 85 °C
Parameter
Description
Automatic power down
current – CMOS inputs
VCC = 2.2 to 3.6 V
ISB2[7]
Automatic power down
current – CMOS inputs
VCC = 1.65 to 2.2 V
Test Conditions
[8]
CE1 > VCC – 0.2 V or CE2 < 0.2 V, 25 °C
40 °C[8]
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, 70 °C[8]
f = 0, VCC = VCC(max)
85 °C
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
45/55 ns
Min
Typ[6]
Max
–
1.4
2.8
–
–
3.5
–
–
5.5
–
–
6.5
–
2.0
8.0
Unit
µA
µA
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V) and
VCC = 1.8V (for VCC range of 1.65 V–2.2 V), TA = 25 °C.
7. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
8. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
pF
10
Thermal Resistance
Parameter[9]
Description
ΘJA
Thermal resistance
(junction to ambient)
ΘJC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
48-pin TSOP I 48-ball VFBGA
44-TSOP II
60.07
36.92
65.91
9.73
13.55
13.96
Unit
°C/W
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 002-27323 Rev. *C
Page 7 of 23
CY62157G/CY62157GE MoBL
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
R1
VCC
OUTPUT
GND
R2
30 pF
ALL INPUT PULSES
90%
90%
10%
VHIGH
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.8 V
2.5 V
3.0 V
Unit
R1
13500
16667
1103
Ω
R2
10800
15385
1554
RTH
6000
8000
645
VTH
0.8
1.20
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
VCC for data retention
Data retention current
ICCDR[11, 12] (For 3.3V Typical Device)
ICCDR[11, 12] Data retention current
(For 1.8V Typical Device)
Min
Typ[15] Max
Unit
1
–
–
CE1 > VCC − 0.2 V or CE2 < 0.2 V,
VCC = 1.2 V
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC − 0.2 V or VIN < 0.2 V
–
4.0
9.0
CE1 > VCC − 0.2 V or CE2 < 0.2 V,
VCC = 1.5 V
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC − 0.2 V or VIN < 0.2 V
–
3.2
8.0
CE1 > VCC − 0.2 V or CE2 < 0.2 V,
2.2 V < VCC < 3.6 V
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC − 0.2 V or VIN < 0.2 V
–
1.4
6.5
1.2 V < VCC < 2.2 V,
CE1 > VCC − 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC − 0.2 V or VIN < 0.2 V
–
5.0
9.0
0
–
–
–
45/55
–
–
ns
tCDR[13]
Chip deselect to data retention –
time
tR[14]
Operation recovery time
–
V
µA
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
11. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1/ISB2/ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after the device is firs powered up to VCC(min) and then brought down to VDR.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 µs.
Document Number: 002-27323 Rev. *C
Page 8 of 23
CY62157G/CY62157GE MoBL
Data Retention Waveform
Figure 7. Data Retention Waveform[15]
V CC
V C C (m in )
tCDR
D A T A R E T E N T IO N M O D E
V D R = 1 .0 V
V C C (m in )
tR
CE1 or
B H E. B LE
CE2
Note
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 002-27323 Rev. *C
Page 9 of 23
CY62157G/CY62157GE MoBL
Switching Characteristics
Parameter[16]
Description
45 ns
55 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
55
–
tAA
Address to data valid/Address LOW to ERR valid
–
45
–
55
tOHA
Data hold from address change
10
–
10
–
tACE
CE1 LOW and CE2 HIGH to data valid/CE LOW to ERR
valid
–
45
–
55
tDOE
OE LOW to data valid/OE LOW to ERR valid
–
22
–
25
tLZOE
OE LOW to Low Z[17]
5
–
5
–
–
18
–
18
10
–
10
–
tHZOE
OE HIGH to High Z
[17, 18]
Low-Z[17]
tLZCE
CE1 LOW and CE2 HIGH to
tHZCE
CE1 HIGH and CE2 LOW to High-Z[17, 18]
–
18
–
18
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
0
–
tPD
CE1 HIGH and CE2 LOW to power-down
–
45
–
55
tDBE
BLE / BHE LOW to data valid
–
45
–
55
Low-Z[17]
tLZBE
BLE / BHE LOW to
5
–
5
–
tHZBE
BLE / BHE HIGH to High-Z[17, 18]
–
18
–
18
tWC
Write cycle time
45
–
55
–
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
40
–
tAW
Address setup to write end
35
–
40
–
tHA
Address hold from write end
0
–
0
–
tSA
Address setup to write start
0
–
0
–
tPWE
WE pulse width
35
–
40
–
tBW
BLE / BHE LOW to write end
35
–
40
–
tSD
Data setup to write end
25
–
25
–
tHD
Data hold from write end
0
–
0
–
–
18
–
20
10
–
10
–
ns
Write Cycle[19, 20]
[17, 18]
tHZWE
WE LOW to High-Z
tLZWE
WE HIGH to Low-Z[17]
ns
Notes
16. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
specified otherwise.
17. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
20. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 002-27323 Rev. *C
Page 10 of 23
CY62157G/CY62157GE MoBL
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY62157G (Address Transition Controlled)[21, 22]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 9. Read Cycle No. 2 (OE Controlled)[22, 23, 24]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tHZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tPU
ISB
Notes
21. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
22. WE is HIGH for read cycle.
23. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
24. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-27323 Rev. *C
Page 11 of 23
CY62157G/CY62157GE MoBL
Switching Waveforms (continued)
Figure 10. Write Cycle No. 1 (WE Controlled, OE LOW)[25, 26, 27, 28]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
tPWE
WE
tHZWE
DATA I/O
NOTE 29
tSD
tLZWE
tHD
DATAIN VALID
Notes
25. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
26. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
27. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
28. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-27323 Rev. *C
Page 12 of 23
CY62157G/CY62157GE MoBL
Switching Waveforms (continued)
Figure 11. Write Cycle No. 2 (CE Controlled)[30, 31, 32]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE/
BLE
OE
t HZOE
DATA I/ O
NOTE 33
tHD
tSD
DATAIN VALID
Notes
30. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
31. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
32. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-27323 Rev. *C
Page 13 of 23
CY62157G/CY62157GE MoBL
Switching Waveforms (continued)
Figure 12. Write Cycle No. 3 (BHE/BLE Controlled, OE LOW)[34, 35, 36, 37]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O NOTE 38
tSD
tHD
tLZWE
DATAIN VALID
Notes
34. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
36. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
37. The minimum write cycle pulse width for Write Cycle No. 3 (BHE/BLE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
38. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-27323 Rev. *C
Page 14 of 23
CY62157G/CY62157GE MoBL
Switching Waveforms (continued)
Figure 13. Write Cycle No. 4 (WE Controlled)[39, 40, 41]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 42
DATA IN VALID
tHZOE
Notes
39. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
40. Data I/O is high impedance if OE = VIH.
41. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
42. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-27323 Rev. *C
Page 15 of 23
CY62157G/CY62157GE MoBL
Truth Table – CY62157G/CY62157GE
BYTE [43] CE1
CE2
WE
OE
BHE
BLE
H
X[44]
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB)
1M × 8/512K×
16
X
X[44]
L
X
X
X
X
High-Z
Deselect/Power-down Standby (ISB)
1M × 8/512K×
16
X
X[44]
X[44]
X
X
H
H
High-Z
Deselect/Power-down Standby (ISB)
512K × 16
H
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
512K × 16
H
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read
Active (ICC)
512K × 16
H
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
512K × 16
H
L
H
H
H
L
H
High-Z
Output disabled
Active (ICC)
512K × 16
H
L
H
H
H
H
L
High-Z
Output disabled
Active (ICC)
512K × 16
H
L
H
H
H
L
L
High-Z
Output disabled
Active (ICC)
512K × 16
H
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
512K × 16
H
L
H
L
X
H
L
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)
Write
Active (ICC)
512K × 16
H
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
512K × 16
L
L
H
H
L
X
X
Data Out (I/O0–I/O7)
Read
Active (ICC)
1M × 8
L
L
H
H
H
X
X
High-Z
Output disabled
Active (ICC)
1M × 8
L
L
H
L
X
X
X
Data In (I/O0–I/O7)
Write
Active (ICC)
1M × 8
X[44]
Inputs/Outputs
Mode
Power
Configuration
ERR Output – CY62157GE
Output[45]
Mode
0
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
High-Z
Device deselected / outputs disabled / Write operation
Notes
43. This pin is available only in the 48-pin TSOP I package. Tie the BYTE to VCC to configure the device in the 512K × 16 option. The 48-pin TSOP I package can also
be used as a 1M × 8 SRAM by tying the BYTE signal to VSS.
44. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
45. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 002-27323 Rev. *C
Page 16 of 23
CY62157G/CY62157GE MoBL
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
CY62157G30-45BVXI
CY62157G30-45BVXIT
45
CY62157GE30-45BVXI
CY62157G30-45ZSXI
CY62157G30-45ZXI
CY62157GE30-45ZXI
55
51-85150
CY62157G18-55BVXI
CY62157G18-55BVXIT
Package Type
Operating
Range
48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
51-85087 44-pin TSOP II (Pb-free)
Industrial
51-85183 48-pin TSOP I (12 × 18.4 × 1.0 mm) (Pb-free)
51-85150
48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
Ordering Code Definitions
CY 621
5
7
G
E
XX - XX XX
X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = BV or ZS or Z
BV = 48-ball VFBGA; ZS = 44-pin TSOP II; Z = 48-pin TSOP I
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage Range: XX = 30 or 18
30 = 3 V typ; 18 = 1.8 V typ
ERR Output: Single-bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 002-27323 Rev. *C
Page 17 of 23
CY62157G/CY62157GE MoBL
Package Diagrams
Figure 14. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 002-27323 Rev. *C
Page 18 of 23
CY62157G/CY62157GE MoBL
Package Diagrams (continued)
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 002-27323 Rev. *C
Page 19 of 23
CY62157G/CY62157GE MoBL
Package Diagrams (continued)
Figure 16. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 002-27323 Rev. *C
Page 20 of 23
CY62157G/CY62157GE MoBL
Acronyms
Document Conventions
Table 1. Acronyms used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
µA
microamperes
ECC
error-correcting code
µs
microseconds
I/O
input/output
mA
milliamperes
OE
output enable
mm
millimeters
SRAM
static random access memory
ns
nanoseconds
TTL
transistor-transistor logic
Ω
ohms
VFBGA
very fine-pitch ball grid array
%
percent
WE
write enable
pF
picofarads
V
volts
W
watts
Document Number: 002-27323 Rev. *C
Symbol
Unit of Measure
Page 21 of 23
CY62157G/CY62157GE MoBL
Document History Page
Document Title: CY62157G/CY62157GE MoBL, 8-Mbit (512K × 16-bits) Static RAM with Error-Correcting Code (ECC)
Document Number: 002-27323
Rev.
ECN No.
Submission
Date
*C
6814364
02/28/2020
Document Number: 002-27323 Rev. *C
Description of Change
Release to web.
Page 22 of 23
CY62157G/CY62157GE MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2019-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
"Security Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk
Device" means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and
other medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-27323 Rev. *C
Revised February 28, 2020
Page 23 of 23
工商网监
湘ICP备2023018690号
