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CY62157H MoBL®
8-Mbit (512K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
Data writes are performed by asserting the Write Enable input
(WE LOW), and providing the data and address on device data
(I/O0 through I/O15) and address (A0 through A18) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
■
Ultra-low standby current
❐ Typical standby current: 5.5A
❐ Maximum standby current: 16 A
■
High speed: 45 ns
■
Voltage range: 2.2 V to 3.6 V
■
Embedded Error-Correcting Code (ECC) for single-bit error
correction
■
1.0 V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62157H is a high-performance CMOS low-power (MoBL)
SRAM device with Embedded Error-Correcting Code. ECC logic
can detect and correct single bit error in accessed location.
This device is offered in dual chip enable option. Dual chip
enable devices are accessed by asserting both chip enable
inputs – CE1 as LOW and CE2 as HIGH.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O0 through I/O15). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high impedance state
when the device is deselected (CE1 HIGH / CE2 LOW for dual
chip enable device), or control signals are de-asserted (OE, BLE,
BHE).
These devices also have a unique “Byte Power down” feature,
where, if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
The CY62157H device is available in a Pb-free 48-ball VFBGA
and 48-pin TSOP I packages. The logic block diagram is on
page 2.
Product Portfolio
Product
CY62157H30
Features and
Options
(see the Pin
Configurations
section)
Dual Chip
Enable
Power Dissipation
Range
Industrial
VCC Range (V)
Speed (ns)
2.2 V–3.6 V
45
Operating ICC, (mA)
f = fmax
Standby, ISB2 (µA)
Typ [1]
Max
Typ [1]
Max
29
36
5.5
16
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-88316 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY62157H MoBL®
Logic Block Diagram
ECC DECODER
512K x 16
RAM ARRAY
DATAIN DRIVERS
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
I/O0-I/O7
I/O8-I/O15
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN DECODER
CE
POWER DOWN
CIRCUIT
BYTE
BHE
BHE
BLE
WE
CE2
OE
CE1
BLE
Document Number: 001-88316 Rev. *E
Page 2 of 20
CY62157H MoBL®
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Truth Table – CY62157H ................................................ 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Document Number: 001-88316 Rev. *E
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
CY62157H MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1mm) pinout [2]
Figure 2. 48-pin TSOP I pinout (Dual Chip Enable) [2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Notes
2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
3. Tie the BYTE pin in the 48-pin TSOP I package to VCC to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8 SRAM by
tying the BYTE signal to VSS. In the 2 M × 8 configuration, Pin 45 is the extra address line A20, while BHE, BLE, and I/O8 to I/O14 pins are not used and can be left
floating.
Document Number: 001-88316 Rev. *E
Page 4 of 20
CY62157H MoBL®
DC input voltage [4] ............................. –0.2 V to VCC + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Supply voltage
to ground potential .............................. –0.2 V to VCC + 0.3 V
DC voltage applied to outputs
in High Z state [4] ................................. –0.2 V to VCC + 0.3 V
Grade
Ambient Temperature
VCC
Industrial
–40 C to +85 C
2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range of –40 C to 85 C
Parameter
Description
45 ns
Test Conditions
Min
Typ [5]
Max
–
VOH
Output HIGH
voltage
2.2 V to 2.7 V
VCC = Min, IOH = –0.1 mA
2
–
2.7 V to 3.6 V
VCC = Min, IOH = –1.0 mA
2.4
–
–
VOL
Output LOW
voltage
2.2 V to 2.7 V
VCC = Min, IOL = 0.1 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 2.1 mA
–
–
0.4
–
1.8
–
VCC + 0.3
VIH
Input HIGH
voltage
2.2 V to 2.7 V
2.7 V to 3.6 V
–
2
–
VCC + 0.3
VIL
Input LOW
voltage [4]
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3
–
0.8
–1
–
+1
IIX
Input leakage current
GND < VIN < VCC
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
ICC
VCC operating supply current
VCC = Max,
IOUT = 0 mA,
CMOS levels
ISB1[6]
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
Unit
V
V
V
V
A
–1
–
+1
A
f = fMAX
–
29.0
36.0
mA
f = 1 MHz
–
7.0
9.0
mA
–
5.5
16.0
A
–
5.5
6.5
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
ISB2
[6]
Automatic power down
current – CMOS inputs
VCC = 2.2 to 3.6 V
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
25 °C [7]
40 °C
(BHE and BLE) > VCC – 0.2 V, 85 °C
[7]
–
6.3
8.0
–
12.0[7]
16.0
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
6. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
7. The ISB2 limits at 25 °C, 70 °C, 40 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-88316 Rev. *E
Page 5 of 20
CY62157H MoBL®
Capacitance
Parameter [8]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter [8]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
48-pin TSOP I 48-ball VFBGA Unit
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
57.99
31.50
°C/W
13.42
15.75
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC
OUTPUT
R1
VHIGH
GND
R2
30 pF
INCLUDING
JIG AND
SCOPE
10%
ALL INPUT PULSES
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH
1.20
1.75
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-88316 Rev. *E
Page 6 of 20
CY62157H MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Min
Typ [9]
Max
Unit
1
–
–
V
–
5.5
16.0
A
Chip deselect to data retention
time
0
–
–
–
Operation recovery time
45
–
–
ns
Description
VDR
VCC for data retention
ICCDR[10, 11]
Data retention current
Conditions
2.2 V < VCC < 3.6 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
tCDR
[12]
tR[13]
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
V CC
V C C (m in )
tCD R
D A T A R E T E N T IO N M O D E
V D R = 1 . 0 V
V C C (m in )
tR
C E 1 o r
B H E . B L E
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
11. ICCDR is guaranteed only after the device is firs powered up to VCC(min) and then brought down to VDR.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-88316 Rev. *E
Page 7 of 20
CY62157H MoBL®
Switching Characteristics
Parameter [15]
Description
45 ns
Unit
Min
Max
45
–
ns
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[16]
tLZOE
OE LOW to Low Z
5
–
ns
tHZOE
OE HIGH to High Z[16, 17]
–
18
ns
CE1 LOW and CE2 HIGH to
Low-Z[16]
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to
High-Z[16, 17]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down
–
45
ns
tDBE
BLE / BHE LOW to data valid
–
45
ns
BLE / BHE LOW to
Low-Z[16]
5
–
ns
BLE / BHE HIGH to
High-Z[16, 17]
–
18
ns
tLZCE
tLZBE
tHZBE
Write Cycle [18, 19]
tWC
Write cycle time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE / BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
tHZWE
tLZWE
WE LOW to High-Z
[16, 17]
WE HIGH to Low-Z
[16]
Notes
15. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
otherwise.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
19. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
Document Number: 001-88316 Rev. *E
Page 8 of 20
CY62157H MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY62157H (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
ADDRESS
tR C
CE
tP D
tH Z C E
tA C E
OE
tH Z O E
tD O E
tL Z O E
BHE/
BLE
tD B E
tL Z B E
D A T A I/O
H IG H IM P E D A N C E
tH Z B E
D A T A O U T V A L ID
H IG H
IM P E D A N C E
tL Z C E
V CC
SU PPLY
CURRENT
tP U
IS B
Notes
20. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
21. WE is HIGH for read cycle.
22. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
23. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-88316 Rev. *E
Page 9 of 20
CY62157H MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled, OE LOW) [24, 25, 26, 27]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
tPWE
WE
tHZWE
DATA I/O
NOTE 28
tSD
tLZWE
tHD
DATAIN VALID
Notes
24. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
26. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
27. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
28. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88316 Rev. *E
Page 10 of 20
CY62157H MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE Controlled) [29, 30, 31]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
t PWE
WE
tBW
BHE/
BLE
OE
t HZOE
DATA I/ O
NOTE 32
tHD
tSD
DATAIN VALID
Notes
29. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
30. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
31. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
32. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88316 Rev. *E
Page 11 of 20
CY62157H MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (BHE/BLE controlled, OE LOW) [33, 34, 35, 36]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
NOTE 37
tSD
tHD
tLZWE
DATAIN VALID
Notes
33. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
34. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
35. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
36. The minimum write cycle pulse width for Write Cycle No. 3 (BHE/BLE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD.
37. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88316 Rev. *E
Page 12 of 20
CY62157H MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 4 (WE Controlled) [38, 39, 40]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 41
DATA IN VALID
tHZOE
Notes
38. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
39. Data I/O is high impedance if OE = VIH.
40. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
41. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88316 Rev. *E
Page 13 of 20
CY62157H MoBL®
Truth Table – CY62157H
CE1
CE2
WE
OE
BHE
BLE
H
X[42]
X
X
X
X
X[42]
L
X
X
X
X[42]
X[42]
X
X
L
H
H
L
H
L
Inputs/Outputs
Mode
Power
High-Z
Deselect/Power-down
Standby (ISB)
X
High-Z
Deselect/Power-down
Standby (ISB)
H
H
High-Z
Deselect/Power-down
Standby (ISB)
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read
Active (ICC)
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)
Write
Active (ICC)
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC)
L
H
H
L
X
X
Data Out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
H
X
X
High-Z
Output disabled
Active (ICC)
L
H
L
X
X
X
Data In (I/O0–I/O7)
Write
Active (ICC)
Note
42. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-88316 Rev. *E
Page 14 of 20
CY62157H MoBL®
Ordering Information
Speed
(ns)
45
Package
Diagram
Ordering Code
CY62157H30-45BVXI
Package Type
51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
CY62157H30-45BVXIT
Operating
Range
Industrial
Ordering Code Definitions
CY 621
5
7
H
30 - 45
BV
X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: 45 = 45 ns
Voltage Range: 30 = 3 V typ
Process Technology: H = 65 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-88316 Rev. *E
Page 15 of 20
CY62157H MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *H
Document Number: 001-88316 Rev. *E
Page 16 of 20
CY62157H MoBL®
Package Diagrams (continued)
Figure 12. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
0.10
2X
N
SEE DETAIL B
A
0.10 C
A2
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-88316 Rev. *E
Page 17 of 20
CY62157H MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
Degrees Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
A
microamperes
I/O
input/output
s
microseconds
OE
output enable
mA
milliamperes
SRAM
static random access memory
mm
millimeters
VFBGA
very fine-pitch ball grid array
ns
nanoseconds
WE
write enable
ohms
%
percent
pF
picofarads
V
volts
W
watts
Document Number: 001-88316 Rev. *E
Symbol
Unit of Measure
Page 18 of 20
CY62157H MoBL®
Document History Page
Document Title: CY62157H MoBL®, 8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-88316
Rev.
ECN No.
Orig. of
Change
Submission
Date
*B
4983842
NILE
10/23/2015
Changed status from Preliminary to Final.
*C
5109716
NILE
01/27/2016
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to VCC Operating Range “2.7 V to 3.6 V” and Test Condition
“VCC = Min, IOH = –1.0 mA”.
*D
5427485
VINI
09/06/2016
Updated Maximum Ratings:
Updated Note 4 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to the Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
*E
6063494
VINI
02/08/2018
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Document Number: 001-88316 Rev. *E
Description of Change
Page 19 of 20
CY62157H MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-88316 Rev. *E
Revised February 8, 2018
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
Page 20 of 20
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