CY62187EV30LL-55BAXI

CY62187EV30, MoBL® 64 Mbit (4M x 16) Static RAM ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A21). If Byte High Enable (BHE) is LOW, then data from I/O pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A21). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of read and write modes. Features ■ Very High Speed ❐ 55 ns Wide Voltage Range ❐ 2.2V to 3.7V Ultra Low Standby Power ❐ Typical Standby Current: 8 μA ❐ Maximum Standby Current: 48 μA Ultra Low Active Power ❐ Typical Active Current: 4.0 mA at f = 1 MHz Easy Memory Expansion with CE1, CE2, and OE Features Automatic Power Down when Deselected CMOS for Optimum Speed and Power Available in Pb-Free 48-Ball FBGA Package ■ ■ ■ ■ ■ ■ ■ Functional Description The CY62187EV30 is a high performance CMOS static RAM organized as 4M words by 16 bits[1]. This device features advanced circuit design to provide ultra low active current. It is Logic Block Diagram DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 4096K × 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE OE BLE A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 CE2 CE1 Power-down Circuit Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-48998 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 10, 2009 [+] Feedback CY62187EV30 Pin Configuration Figure 1. 48-Ball VFBGA 1 BLE IO 8 IO 9 VSS VCC IO 14 IO 15 A18 2 OE BHE IO 10 IO11 IO 12 IO 13 A19 A8 3 A0 A3 A5 A17 A21 A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO 1 IO3 IO 4 IO 5 WE A11 6 CE2 IO 0 IO 2 Vcc Vss IO 6 IO 7 A20 A B C D E F G H Product Portfolio Power Dissipation Product VCC Range (V) Speed (ns) Typ[2] 55 70 4.0 4.0 Operating ICC (mA) f = 1 MHz Min CY62187EV30LL 2.2 Typ[2] 3.0 Max 3.7 Max 6 6 f = fMax Typ[2] 45 35 Max 55 45 Standby ISB2 (μA) Typ[2] 8 8 Max 48 48 Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 001-48998 Rev. *C Page 2 of 12 [+] Feedback CY62187EV30 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage to Ground Potential..........................................–0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High Z State [3, 4] ........................ –0.3V to VCC (max) + 0.3V DC Input Voltage [3, 4] .................... –0.3V to VCC (max) + 0.3V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Device CY62187EV30LL Range Ambient Temperature VCC[5] Industrial –40°C to +85°C 2.2V to 3.7V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB2 [6] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current—CMOS Inputs Test Conditions 2.2V < VCC < 2.7V IOH = –0.1 mA 2.7V < VCC < 3.7V IOH = –1.0 mA 2.2V < VCC < 2.7V IOL = 0.1 mA 2.7V < VCC < 3.7V IOL = 2.1 mA 2.2V < VCC < 2.7V 2.7V < VCC < 3.7V 2.2V< VCC < 2.7V 2.7V < VCC < 3.7V GND < VI < VCC f = fMax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels Output Leakage Current GND < VO < VCC, Output Disabled 1.8 2.2 –0.3 –0.3 –1 –1 45 4.0 8 55 ns Min 2.0 2.4 0.4 0.4 VCC + 0.3V 1.8 VCC + 0.3V 2.2 0.6 0.7 +1 +1 55 6 48 –0.3 –0.3 –1 –1 35 4.0 8 Typ[2] Max 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.7 +1 +1 45 6 48 70 ns Min Typ[2] Max Unit V V V V V V V V μA μA mA mA μA CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.7V Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max 25 35 Unit pF pF Notes 3. VIL(min) = –2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. 6. Only chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-48998 Rev. *C Page 3 of 12 [+] Feedback CY62187EV30 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 2. AC Test Loads and Waveforms VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 VCC GND R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still Air, soldered on a 3 × 4.5 inch, 2-layer printed circuit board FBGA 59.06 14.08 Unit °C/W °C/W Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V Table 1. AC Test Loads Parameter R1 R2 RTH VTH 2.2V to 3.7V 1103 1554 645 VCC/2 1.5 Unit Ω Ω Ω V V 2.2V < VCC < 3V 3V < VCC < 3.7V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [6] tCDR[7] tR[8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Figure 3. Data Retention Waveform [9] VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V VCC(min) tR Conditions VCC= 1.5V, CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 0 tRC Min 1.5 Typ[2] Max 48 Unit V μA ns ns VCC CE1 or BHE.BLE or CE2 Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 9. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 001-48998 Rev. *C Page 4 of 12 [+] Feedback CY62187EV30 Switching Characteristics Over the Operating Range [10] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[11, 12] WE HIGH to Low-Z[11] 10 55 45 45 0 0 40 45 25 0 20 10 70 60 60 0 0 50 60 35 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[11] 5 20 10 20 0 55 55 10 20 10 25 0 70 70 10 25 OE HIGH to High Z[11, 12] CE1 LOW and CE2 HIGH to Low Z[11] CE1 HIGH and CE2 LOW to High Z[11, 12] CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z [11] BLE/BHE HIGH to HIGH Z [11, 12] Description 55 ns Min 55 55 6 55 25 5 6 Max Min 70 70 ns Max Unit ns 70 70 35 25 ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns, timing reference levels of VTH, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads on page 4. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-48998 Rev. *C Page 5 of 12 [+] Feedback CY62187EV30 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled)[14, 15] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Figure 5. Read Cycle 2 (OE Controlled)[15, 16] ADDRESS tRC CE1 tPD tHZCE tACE CE2 BHE/BLE tLZBE OE tDBE tHZBE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU tDOE DATA VALID tHZOE HIGH IMPEDANCE ICC 50% 50% ISB Notes 14. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 001-48998 Rev. *C Page 6 of 12 [+] Feedback CY62187EV30 Switching Waveforms (continued) Figure 6. Write Cycle 1 (WE Controlled) [13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tHA tPWE BHE/BLE tBW OE tSD DATA IO tHD NOTE 19 VALID DATA tHZOE Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA IO NOTE 19 tHD VALID DATA tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period the I/Os are in output state and input signals should not be applied. Document #: 001-48998 Rev. *C Page 7 of 12 [+] Feedback CY62187EV30 Switching Waveforms (continued) Figure 8. Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tHA tPWE WE tSA tSD DATA IO NOTE 19 tHD VALID DATA tHZWE tLZWE Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18,19] tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tHA tBW tSA WE tPWE tSD tHD DATA IO NOTE 19 VALID DATA Document #: 001-48998 Rev. *C Page 8 of 12 [+] Feedback CY62187EV30 Truth Table CE1 H X[20] X [20] CE2 X [20] WE X X X H H H L L L H H H OE X X X L L L X X X H H H BHE X X H L H L L H L L H L BLE X X H L L H L L H H L L Inputs Outputs High Z High Z High Z Data Out (IO0–IO15) High Z (IO8–IO15): Data Out (IO0–IO7) Data Out (IO8–IO15); High Z (IO0–IO7) Data In (IO0–IO15) High Z (IO8–IO15); Data In (IO0–IO7) Data In (IO8–IO15); High Z (IO0–IO7) High Z High Z High Z Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) L X [20] L L L L L L L L L H H H H H H H H H Ordering Information Speed (ns) 55 70 Ordering Code CY62187EV30LL-55BAXI CY62187EV30LL-70BAXI Package Diagram Package Type Operating Range Industrial Industrial 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free Note 20. The ‘X’ (Don’t care) state for the chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-48998 Rev. *C Page 9 of 12 [+] Feedback CY62187EV30 Package Diagrams Figure 10. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 - *A Document #: 001-48998 Rev. *C Page 10 of 12 [+] Feedback CY62187EV30 Document History Page Document Title: CY62187EV30 MoBL® 64 Mbit (4M x 16) Static RAM Document Number: 001-48998 Rev. ** *A *B ECN No. 2595932 2644442 2672650 Orig. of Change VKN/PYRS VKN/PYRS VKN/PYRS Submission Date 10/24/08 01/23/09 03/12/09 Description of Change New Data Sheet Updated the Package diagram on page 10 Extended the VCC range to 3.7V Added 55 ns speed bin and it’s related information Changed ICC (typ) from 2.5 mA to 3.5 mA at f = 1 MHz Changed ICC (max) from 4 mA to 6 mA at f = 1 MHz For 70 ns speed, changed ICC (typ) form 33 mA to 28 mA at f = fMAX For 70 ns speed, changed ICC (max) from 40 mA to 45 mA at f = fMAX For 70 ns speed, changed tPWE from 45 to 50 ns, tSD from 30 to 35 ns Modified footnote #6 Changed 48-Ball FBGA package dimensions from 8 x 9.5 x 1.6 mm to 8 x 9.5 x 1.4 mm and updated package diagram on page 10 Converted from preliminary to final Changed ICC(typ) from 3.5 mA to 4 mA at f = 1 MHz Changed ICC(typ) from 35 mA to 45 mA and from 28 mA to 35 mA for the speeds 50 ns and 70 ns respectively at f = fmax Included VCC range in the test condition of the “Electrical Characteristics” table for the specs VOH, VOL, VIH, VIL Changed VIL(max) from 0.8V to 0.7V for VCC = 2.7V to 3.7V Changed CIN spec from 20 pF to 25 pF and COUT spec from 20 pF to 35 pF Included thermal specs for 48-FBGA Included VCC range for VTH spec in the AC test load table Changed tLZBE spec from 5 ns to 10 ns Added footnote #20 related to chip enable *C 2737164 VKN/AESA 07/13/09 Document #: 001-48998 Rev. *C Page 11 of 12 [+] Feedback CY62187EV30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-48998 Rev. *C Revised July 10, 2009 Page 12 of 12 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback