CY62187G30-55BAXI

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62187G30 MoBL 64-Mbit (4M words × 16-bit) Static RAM with Error-Correcting Code (ECC) CY62187G30 MoBL, 64-Mbit (4M words × 16-bit) Static RAM with Error-Correcting Code (ECC) Features ■ Ultra-low standby current ❐ Typical standby current: 6 µA ❐ Maximum standby current: 38 µA ■ High speed: 55 ns ■ Embedded error-correcting code (ECC) for single-bit error correction[1] ■ Operating voltage range: 2.2 V to 3.6 V ■ 1.0-V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Available in Pb-free 48-ball VFBGA package Functional Description CY62187G30 is a high-performance CMOS, low-power (MoBL®) SRAM device with embedded ECC[2]. This device is offered in Dual Chip Enable option. To access a Dual Chip Enable device, assert both Chip Enable inputs – CE1 as LOW and CE2 as HIGH. To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A21) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can access the read data on the I/O lines (I/O0 through I/O15). To perform byte accesses, assert the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of the data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a High-Z state when the device is deselected (CE1 HIGH / CE2 LOW for a Dual Chip Enable device), or the control signals are deasserted (OE, BLE, BHE). These devices have a unique byte power-down feature where, when both Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to the standby mode irrespective of the state of the Chip Enables, thereby saving power. CY62187G30 is available in a Pb-free 48-ball VFBGA package. See Logic Block Diagram – CY62187G30 on page 2. For a complete list of related documentation, click here. Product Portfolio Current Consumption Product Features and Options (see Pin Configuration – CY62187G30) CY62187G30 Dual Chip Enable Range Industrial VCC Range (V) Speed (ns) 2.2 V–3.6 V 55 Operating ICC, (mA) Standby, ISB2 (µA) f = fmax Typ[3] Max Typ[3] Max 40 55 6 38 Notes 1. SER FIT rate 2001 V Latch-up current ..................................................... >140 mA Ambient temperature with power applied .................................. –55 °C to + 125 °C Operating Range Supply voltage to ground potential .............................. –0.5 V to VCC + 0.5 V DC voltage applied to outputs in High Z state[6] .................................. –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC[7] Industrial –40 °C to +85 °C 2.2 V to 3.6 V DC Electrical Characteristics Over the operating range of –40°C to 85°C Parameter VOH Description Output HIGH 2.2 V to 2.7 V voltage 2.7 V to 3.6 V 55 ns Test Conditions Min Typ [8] Max VCC = Min, IOH = –0.1 mA 2.0 – – VCC = Min, IOH = –1.0 mA 2.4 – – – – 0.4 – – 0.4 1.8 – VCC + 0.3 2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA 2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA Input HIGH voltage[6] 2.2 V to 2.7 V – 2.7 V to 3.6 V – 2.0 – VCC + 0.3 VIL Input LOW voltage[6] 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 – 0.8 IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 ICC VCC operating supply current VCC = Max, IOUT = 0 mA, CMOS levels f = 22.22 MHz (45 ns) – 40 55.0 f = 1 MHz – 15 38.0 – 12.0 38.0 – – – – – – – – – – – – VOL VIH Output LOW voltage Unit V µA mA CE1 > VCC – 0.2 V or CE2 < 0.2 V ISB1[11] Automatic Power-down Current – CMOS Inputs; VCC = 2.2 V to 3.6 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, µA f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC(max) CE1 > VCC – 0.2V or CE2 < 0.2 V or ISB2[11] Automatic Power-down Current – CMOS Inputs VCC = 2.2 V to 3.6 V (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, µA – – 6.0 38.0 f = 0, VCC = VCC(max) Notes 6. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 7. Full device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 400-µs wait time after VCC stabilizes to its operational value. 8. Indicates the value for the center of distribution at 3.0 V, 25°C and not 100% tested. 9. Chip enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 10. The ISB2 maximum limits at 25 °C, 40 °C, and 70 °C are guaranteed by design and not 100% tested. Document Number: 002-24731 Rev. *B Page 5 of 18 CY62187G30 MoBL Capacitance Parameter [11] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 15.0 pF 15.0 pF Thermal Resistance Parameter [11] Description ΘJA Thermal resistance (junction to ambient) ΘJC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA Unit 82.6 °C/W 10.8 °C/W Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms VCC OUTPUT R1 VHIGH GND 30 pF R2 INCLUDING JIG AND SCOPE 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5 V 3.0 V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V VHIGH 2.5 3.0 V Note 11. Tested initially and after any design or process changes that may affect these parameters. Document Number: 002-24731 Rev. *B Page 6 of 18 CY62187G30 MoBL Data Retention Characteristics Over the Operating Range Parameter VDR Description VCC for data retention Conditions Min Typ [12] Max Unit – 1.5 – – V – 6.0 38.0 µA – – 48.0 0.0 – – – 55.0 – – ns 2.2 V < VCC < 3.6 V CE1 > VCC − 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC − 0.2 V or VIN < 0.2 V ICCDR[13, 14] Data retention current 1.5 V < VCC < 2.2 V, CE1 > VCC − 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC − 0.2 V or VIN < 0.2 V tCDR[15] Chip deselect to data retention time – tR[15, 16] Operation recovery time – Data Retention Waveform Figure 3. Data Retention Waveform [17] VCC VCC (min) tCDR DATA RETENTION MODE VDR = 1.0 V VCC (min) tR CE1 or BHE. BLE CE2 Notes 12. Indicates the value for the center of distribution at 3.0 V, 25°C and not 100% tested. 13. Chip Enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 14. ICCDR is guaranteed only after the device is first powered up to VCC(min) and then brought down to VDR. 15. These parameters are guaranteed by design and are not tested. 16. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 400 µs or stable at VCC(min) > 400 µs. 17. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document Number: 002-24731 Rev. *B Page 7 of 18 CY62187G30 MoBL Switching Characteristics Parameter [18] Description 55 ns Unit Min Max 55.0 – ns – 55.0 ns Read Cycle tRC Read cycle time tAA Address to data valid / Address to ERR valid tOHA Data hold from address change / ERR hold from address change 10.0 – ns tACE CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid – 55.0 ns tDOE OE LOW to data valid / OE LOW to ERR valid – 25.0 ns 5.0 – ns tLZOE OE LOW to low Z[19, 20] High-Z[19, 20, 21] tHZOE OE HIGH to tLZCE CE1 LOW and CE2 HIGH to low Z[19, 20] – 18.0 ns 10.0 – ns – 18.0 ns 0.0 – ns – 55.0 ns – 55.0 ns Z[19] 5.0 – ns High-Z[19, 21] – 18.0 ns CE1 HIGH and CE2 LOW to High-Z[19, 20, 21] CE1 LOW and CE2 HIGH to power-up[22] tPD CE1 HIGH and CE2 LOW to power-down[22] tDBE BLE / BHE LOW to data valid tHZCE tPU tLZBE BLE / BHE LOW to low tHZBE Write Cycle BLE / BHE HIGH to [23, 24] tWC Write cycle time 55.0 – ns tSCE CE1 LOW and CE2 HIGH to write end 40.0 – ns tAW Address setup to write end 40.0 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 40.0 – ns tBW BLE / BHE LOW to write end 40.0 – ns tSD Data setup to write end 25.0 – ns tHD Data hold from write end 0.0 – ns High-Z[19, 20, 21] – 18.0 ns Z[19, 20] 10.0 – ns tHZWE tLZWE WE LOW to WE HIGH to low Notes 18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in Figure 2 on page 6, unless specified otherwise. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. Tested initially and after any design or process changes that may affect these parameters. 21. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 22. These parameters are guaranteed by design and are not tested. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 24. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of tHZWE and tSD. Document Number: 002-24731 Rev. *B Page 8 of 18 CY62187G30 MoBL Switching Waveforms Figure 4. Read Cycle No. 1 of CY62187G30 (Address Transition Controlled) [25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 5. Read Cycle No. 1 of CY62177GE30 (Address Transition Controlled) [25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 25. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE, or both = VIL. 26. WE is HIGH for read cycle. Document Number: 002-24731 Rev. *B Page 9 of 18 CY62187G30 MoBL Switching Waveforms (continued) Figure 6. Read Cycle No. 2 (OE Controlled) [27, 28, 29, 31] ADDRESS tR C CE tP D tH Z C E tA C E OE tH Z O E tD O E tL Z O E BHE/ BLE tD B E tL Z B E D A T A I/O tH Z B E H IG H IM P E D A N C E H IG H IM P E D A N C E D A T A O U T V A L ID tLZC E tP U V CC SUPPLY CURRENT IS B Figure 7. Write Cycle No. 1 (WE Controlled, OE LOW) [28, 30, 31, 32] tW C ADDRESS tS C E CE tB W BHE/ BLE tS A tA W tH A tP W E WE tH Z W E D A T A I/O Note 32 tS D tLZW E tH D D A T A IN V A L ID Notes 27. WE is HIGH for read cycle. 28. For all Dual Chip Enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 29. Address valid prior to or coincident with CE LOW transition. 30. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 31. Data I/O is in the High-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 32. During this period, the I/Os are in the output state. Do not apply input signals. 33. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD. Document Number: 002-24731 Rev. *B Page 10 of 18 CY62187G30 MoBL Switching Waveforms (continued) Figure 8. Write Cycle No. 2 (CE Controlled) [34, 35, 36] tWC ADDRESS tSA t SCE CE tAW tHA t PWE WE tBW BHE/ BLE OE t HZOE DATA I/ O Note 37 tHD tSD DATAIN VALID Notes 34. For all Dual Chip Enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write.Any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 36. Data I/O is in the High-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 37. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 002-24731 Rev. *B Page 11 of 18 CY62187G30 MoBL Switching Waveforms (continued) Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [38, 39, 40] tW C ADDRESS tS C E CE tA W tS A tH A tB W BHE/ B LE tP W E WE t H ZW E D A TA I/O tH D t SD Note 41 t LZW E D A TA IN V A LID Figure 10. Write Cycle No. 5 (WE Controlled) [38, 39, 40] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE tB W B H E /B L E OE tH Z O E D A T A I/O Note 41 tH D tS D D A T A IN V A L I D Notes 38. For all Dual Chip Enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 39. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write. Any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 40. Data I/O is in the High-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 41. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 002-24731 Rev. *B Page 12 of 18 CY62187G30 MoBL Truth Table – CY62187G30 CE1 WE OE BHE BLE [42] Mode Power X X X X High-Z Deselect/Power-down Standby (ISB) X L X X X X[42] [42] X High-Z Deselect/Power-down Standby (ISB) X X H H High-Z Deselect/Power-down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O0–I/O7); High-Z (I/O8–I/O15) Read Active (ICC) L H H L L H High-Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High-Z Output disabled Active (ICC) L H H H H L High-Z Output disabled Active (ICC) L H H H L L High-Z Output disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High-Z (I/O8–I/O15) Write Active (ICC) L H L X L H High-Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) H CE2 X [42] X Inputs/Outputs Note 42. The ‘X’ (Don’t care) state for the Chip Enables refers to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins are not permitted. Document Number: 002-24731 Rev. *B Page 13 of 18 CY62187G30 MoBL Ordering Information Speed (ns) 55 Voltage Range 2.2 V–3.6 V Ordering Code CY62187G30-55BAXI Package Diagram Package Type (all Pb-free) 001-50044 48-ball VFBGA Key Features / Differentiators Dual Chip Enable Operating Range Industrial Ordering Code Definitions CY 621 8 7 G XX - XX XX X X Temperature Grade: X = I; I = Industrial Pb-free Package Type: XX = BV; BA = 48-ball VFBGA Speed Grade: XX: 55 = 55 ns Voltage range: 30 = 3-V typ; Process Technology: Ultra Low-power Bus width: 7 = ×16 Density: 8 = 64-Mbit Family Code: MoBL® SRAM family Company ID: CY = Cypress Document Number: 002-24731 Rev. *B Page 14 of 18 CY62187G30 MoBL Package Diagram Figure 11. 48L FBGA 8 × 9.5 × 1.4 MM BK48L Package Outline, 001-50044 001-50044 *D Document Number: 002-24731 Rev. *B Page 15 of 18 CY62187G30 MoBL Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary metal oxide semiconductor μA microampere I/O Input/output μs microsecond OE Output Enable mA milliampere SRAM Static random access memory mm millimeter TSOP Thin small outline package ns nanosecond VFBGA Very fine-pitch ball grid array Ω ohm WE Write Enable % percent pF picofarad V volt W watt Document Number: 002-24731 Rev. *B Symbol Unit of Measure Page 16 of 18 CY62187G30 MoBL Document History Page Document Title: CY62187G30 MoBL, 64-Mbit (4M words × 16-bit) Static RAM with Error-Correcting Code (ECC) Document Number: 002-24731 Rev. ECN Submission Date *A 6714290 10/30/2019 Updated maximum standby current value in Features, Product Portfolio, and DC Electrical Characteristics. Updated Icc maximum value in Product Portfolio and DC Electrical Characteristics. Updated Icc @ 1MHz maximum value in DC Electrical Characteristics. Updated Data Retention Characteristics. Added Thermal Resistance values. Added Package Diagram spec 001-50044. *B 6883183 05/28/2020 Moved datasheet status from Preliminary to Final. Removed CY62187G30-55BAXIT from Ordering Information. Updated Ordering Code Definitions. Document Number: 002-24731 Rev. *B Description of Change Page 17 of 18 CY62187G30 MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-24731 Rev. *B Revised May 28, 2020 Page 18 of 18