CY7B9911

lock+ CY7B9911 RoboClock+ Programmable Skew Clock Buffer (PSCB) Features • All output pair skew 2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 10% Note: 4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID). Document #: 38-07209 Rev. ** t 0 +6t t0 U Page 3 of 12 CY7B9911 RoboClock+ Electrical Characteristics Over the Operating Range CY7B9911 Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL IOS ICCQ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage (REF and FB inputs only) Input LOW Voltage (REF and FB inputs only) Three-Level Input HIGH Voltage (Test, FS, xFn)[5] Three-Level Input MID Voltage (Test, FS, xFn)[5] Three-Level Input LOW Voltage (Test, FS, xFn)[5] Input HIGH Leakage Current (REF and FB inputs only) Input LOW Leakage Current (REF and FB inputs only) Input HIGH Current (Test, FS, xFn) Input MID Current (Test, FS, xFn) Input LOW Current (Test, FS, xFn) Output Short Circuit Current[6] Operating Current Used by Internal Circuitry Output Buffer Current per Output Pair[7] Power Dissipation per Output Pair[8] Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND VCC = Max., VOUT = GND (25°C only) VCCN = VCCQ = Max., All Input Selects Open Com’l – 50 – 500 200 50 – 200 – 250 85 Test Conditions VCC = Min., IOH = – 16 mA VCC = Min., IOH =– 40 mA VCC = Min., IOL = 46 mA VCC = Min., IOL = 46 mA 2.0 – 0.5 VCC – 0.85 VCC/2 – 500 mV 0.0 VCC 0.8 VCC VCC/2 + 500 mV 0.85 10 V V V V V µA µA µA µA µA mA mA 0.45 V Min. 2.4 Max. Unit V ICCN VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX 14 mA PD 78 mW Notes: 5. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 6. CY7B9911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 7. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7B9911: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1 Where F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F ∗ C 8. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: CY7B9911: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1 See note 7 for variable definition. Document #: 38-07209 Rev. ** Page 4 of 12 CY7B9911 RoboClock+ Capacitance[9] Parameter CIN Description Test Conditions Max. Unit pF Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 10 Note: 9. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V R1 CL R1=130 R2=91 CL = 30 pF (Includes fixture and probe capacitance) 7B9911–4 3.0V 2.0V Vth =1.5V 0.8V 0.0V 2.0V Vth =1.5V 0.8V R2 ≤1ns ≤1ns 7B9911–5 TTL AC Test Load (CY7B9911) TTL Input Test Waveform (CY7B9911) Document #: 38-07209 Rev. ** Page 5 of 12 CY7B9911 RoboClock+ Switching Characteristics Over the Operating Range[2, 10, 11] CY7B9911–5 Parameter fNOM Description Operating Clock Frequency in MHz FS = LOW FS = MID [1, 2] [1, 2] [1, 2 , 3] CY7B9911–7 Max. 30 50 100 Min. 15 25 40 4.0 4.0 See Table 1 Typ. Max. 30 50 100 ns ns Unit MHz Min. 15 25 40 4.0 4.0 See Table 1 Typ. FS = HIGH tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR REF Pulse Width HIGH REF Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1)[12, 13] Zero Output Skew (All Outputs)[12, 14] 0.1 0.25 0.6 0.5 0.5 0.5 0.25 0.5 0.7 1.2 0.9 1.2 1.25 0.1 0.3 0.6 1.0 0.7 1.2 0.25 0.75 1.0 1.7 1.4 1.9 1.65 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps ps Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[12, 15] Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[12, 15] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[12, 15] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[12, 15] Device-to-Device Skew[11, 16] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation [17] [18, 19] – 0.5 – 1.0 0.0 0.0 +0.5 +1.0 2.0 2.5 – 0.7 – 1.2 0.0 0.0 +0.7 +1.2 2.5 3 Output HIGH Time Deviation from 50% Output LOW Time Deviation from 50% Output Rise Time Output Fall Time PLL Lock Time [18, 20] [18, 20] [18, 19] 0.15 0.15 [11] [11] 1.0 1.0 1.5 1.5 0.5 0.15 0.15 1.5 1.5 2.5 2.5 0.5 25 200 [21] Cycle-to-Cycle Output Jitter RMS 25 200 Peak-to-Peak Notes: 10. Test measurement levels for the CY7B9911 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 12. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30 pF and terminated with 50Ω to 2.06V. 13. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 14. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 15. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 16. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 17. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 18. Specified with outputs loaded with 30 pF. Devices are terminated through 50Ω to 2.06V. 19. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 20. tORISE and tOFALL measured between 0.8V and 2.0V. 21. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Document #: 38-07209 Rev. ** Page 6 of 12 CY7B9911 RoboClock+ AC Timing Diagrams tREF tRPWH REF tPD tODCV tRPWL tODCV FB tJR Q tSKEWPR, tSKEW0, 1 OTHER Q tSKEWPR, tSKEW0, 1 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1,3, 4 REF DIVIDED BY 4 tSKEW2 tSKEW3, 4 tSKEW2, 4 7B9911–8 Document #: 38-07209 Rev. ** Page 7 of 12 CY7B9911 RoboClock+ Operational Mode Descriptions REF L1 SYSTEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LENGTH L1 = L2 = L3 = L4 Z0 7B9911–9 LOAD Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 L3 Z0 L4 LOAD L2 Z0 LOAD Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the PSCB configured as a zero-skew clock buffer. In this mode the 7B9911 can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an indepenREF Z0 dent load. The FB input can be tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design. LOAD L1 SYS– TEM CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LENGTH L1 = L2 L3 < L2 by 6 inches L4 > L2 by 6 inches L3 Z0 L4 Z0 7B9911–10 L2 Z0 LOAD LOAD Figure 3. Programmable-Skew Clock Driver Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the PSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. Document #: 38-07209 Rev. ** In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. Clock skews can be advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU, and –tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by proper selection of the xFn inputs. For example a +10 tU between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx Page 8 of 12 CY7B9911 RoboClock+ skews to +6 tU, a total of +10 tU skew is realized.) Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs. REF simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80-MHz operation because that is the frequency of the fastest output. REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 7B9911–11 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 20 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 10 MHz 5 MHz 20 MHz Figure 4. Inverted Output Connections Figure 4 shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting which output is connect to FB, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q. REF 7B9911–13 Figure 6. Frequency Divider Connections Figure 6 demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the 1 ⁄2 frequency and 1⁄4 frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15- to 30-MHz range since the highest frequency output is running at 20 MHz. Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. The PSCB can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. 20 MHz FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 40 MHz 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 20 MHz 80 MHz 7B9911–12 Figure 5. Frequency Multiplier with Skew Connections Figure 5 illustrates the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which results in a 40-MHz waveform at these outputs. Note that the 20- and 40-MHz clocks fall Document #: 38-07209 Rev. ** Page 9 of 12 CY7B9911 RoboClock+ REF Z0 20–MHz DISTRIBUTION CLOCK FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 80–MHz INVERTED LOAD LOAD 20–MHz Z0 LOAD 80–MHz ZEROSKEW 80–MHz SKEWED4ns Z0 LOAD Z0 7B9911–14 Figure 7. Multi-Function Clock Driver REF Z0 L1 FB SYSTEM CLOCK REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST Z0 L2 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 L4 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LOAD LOAD Z0 L3 Z0 LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD LOAD 7B9911–15 Figure 8. Board-to-Board Clock Distribution Figure 8 shows the CY7B9911 connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series. Ordering Information Accuracy (ps) 500 750 Ordering Code CY7B9911–5JC CY7B9911–7JC Package Name J65 J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Document #: 38-07209 Rev. ** Page 10 of 12 CY7B9911 RoboClock+ Package Diagrams 32-Lead Plastic Leaded Chip Carrier J65 Document #: 38-07209 Rev. ** Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7B9911 RoboClock+ Document Title: CY7B9911 RoboClock+ Programmable Skew Clock Buffer (PSCB) Document Number: 38-07209 REV. ** ECN NO. 110342 Issue Date 12/21/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00623 to 38-07209 Document #: 38-07209 Rev. ** Page 12 of 12