CY7B9945V-5AC

RoboClock CY7B9945V High-speed Multi-phase PLL Clock Buffer Features • • • • • • • • • • • • • • • 500 ps max. Total Timing Budget™ (TTB™) window 24–200 MHz input/output operation Low output-output skew < 200 ps 10 + 1 LVTTL outputs driving 50Ω terminated lines Dedicated feedback output Phase adjustments in 625/1300 ps steps up to +10.4 ns 3.3V LVTTL/LVPECL, fault-tolerant, and hot-insertable reference inputs Multiply/divide ratios of 1–6, 8, 10, and 12 Individual output bank disable Output high-impedance option for testing purposes Integrated phase-locked loop (PLL) with lock indicator Low cycle-cycle jitter ( 1100V (per MIL-STD-883, Method 3015) Latch-up Current.................................................. > ± 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ±10% 3.3V ±10% Electrical Characteristics Over the Operating Range Parameter Description LVTTL-compatible Output Pins (1Q[0:3],2Q[0:5]) VOH VOL LVTTL HIGH Voltage LVTTL LOW Voltage (QF, 1Q[0:3], 2Q[0:5]) LOCK (QF, 1Q[0:3], 2Q[0:5]) LOCK Test Conditions VCC = Min., IOH = –30 mA IOH = –2 mA, VCC = Min. VCC = Min., IOL= 30 mA IOL= 2 mA, VCC = Min. Min. 2.4 2.4 – – –100 Min. < VCC < Max. Min. < VCC < Max. VCC = GND, VIN = 3.63V VCC = Max., VIN = VCC 2.0 –0.3 – – –500 0.87 * VCC Max. – – 0.5 0.5 100 VCC + 0.3 0.8 100 500 – – Unit V V V V µA V V µA µA µA V V V µA µA µA µA µA µA mV V V V mA mA High-impedance State Leakage Current IOZ LVTTL-compatible Input Pins (FBK, REF±, DIS[1:2],REFSEL) VIH VIL II IlH LVTTL Input HIGH LVTTL Input LOW LVTTL VIN >VCC LVTTL Input HIGH Current LVTTL Input LOW Current VCC = Max., VIN = GND IlL Three-level Input Pins (FS[0:2], 1F[0:3], 2F[0:1], [1:2]DS[0:1], FBFO, FBDS[0:1],MODE) VIHH VIMM VILL IIHH IIMM IILL Three-level Input HIGH[4] Three-level Input Three-level Input LOW[4] Three-level Input HIGH FS[0:2],IF[0:3],FBDS[0:1] Current 2F[0:1],[1:2]DS[0:1],FBFO Three-level Input MID Current FS[0:2],IF[0:3],FBDS[0:1] 2F[0:1],[1:2]DS[0:1],FBFO MID[4] Min. < VCC < Max. Min. < VCC < Max. Min. < VCC < Max. VIN = VCC VIN = VCC/2 VIN = GND 0.47 * VCC 0.53 * VCC – 0.13 * VCC – 200 – 400 –50 –100 –200 –400 400 1.0 GND 0.8 50 100 – – VCC VCC VCC – 0.4 VCC – 0.2 250 40 Three-level Input LOW FS[0:2],IF[0:3],FBDS[0:1] Current 2F[0:1],[1:2]DS[0:1],FBFO LVDIFF Input Pins (REF[A:B]±) VDIFF Input Differential Voltage VIHHP VILLP Highest Input HIGH Voltage Lowest Input LOW Voltage Common Mode Range (Crossing Voltage) VCOM Operating Current ICCI ICCN Internal Operating Current Output Current Dissipation/Pair[6] CY7B9945V CY7B9945V VCC = Max., fMAX[5] VCC = Max., CLOAD = 25 pF, RLOAD = 50Ω at VCC/2, fMAX – – Note: 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 200 MHz) and the other output bank to run at half the maximum frequency. FS is asserted to the HIGH state. 6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50Ω at VCC/2. Document #: 38-07336 Rev. *D Page 6 of 10 RoboClock CY7B9945V Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V [7, 8, 9, 10, 11] Min. – Max. 5 Unit pF Switching Characteristics Over the Operating Range Parameter fin fout tSKEWPR tSKEWBNK tSKEW0 tSKEW1 tSKEW2 tCCJ1-3 Clock Input Frequency Clock Output Frequency Description CY7B9945V-2 CY7B9945V-5 Min. 24 24 – – – – – – Max. 200 200 200 250 250 250 500 150 Min. 24 24 – – – – – – Max. 200 200 200 250 550 650 800 150 Unit MHz MHz ps ps ps ps ps ps PeakPeak ps PeakPeak ps ps ps ns ns ns ms µs µs ns ns ns UI ns ns Matched-Pair Skew[12, 13],1Q[0:1],1Q[2:3],2Q[0:1],2Q[2:3],2Q[4:5] Intrabank Skew[12, 13] Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[12, 13] Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[12, 13] Output-Output Skew (all output configurations outside of tSKEW0 and tSKEW1)[12, 13] Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) tCCJ4-12 Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6, 8, 10, 12) Propagation Delay, REF to FB Rise Total Timing Budget window (same frequency and phase)[14, 15] Propagation Delay difference between two devices[16] REF input (Pulse Width HIGH)[5] REF input (Pulse Width LOW)[5] Output Rise/Fall Time[17] PLL Lock TIme From Power-Up PLL Relock Time (from same frequency, different phase) with Stable Power Supply PLL Re-Lock Time (from different frequency, different phase) with Stable Power Supply[18] Output duty cycle deviation from 50%[11] Output HIGH time deviation from 50% [19] – 100 – 100 tPD TTB tPDDELTA tREFpwh tREFpwl tr/tf tLOCK tRELOCK1 tRELOCK2 tODCV tPWH tPWL tPDEV tOAZ tOZA –250 – – 2.0 2.0 0.15 – – – –1.0 – – reference[20] – 1.0 0.5 250 500 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 –500 – – 2.0 2.0 0.15 – – – –1.0 – – – 1.0 0.5 500 700 200 – – 2.0 10 500 1000 1.0 1.5 2.0 0.025 10 14 Output LOW time deviation from 50%[19] Period deviation when changing from reference to DIS[1:2] HIGH to output high-impedance from ACTIVE[12, 21] DIS[1:2] LOW to output ACTIVE from output is high-impedance[21, 22] Notes: 7. This is for non-three-level inputs. 8. Assumes 25 pF Max. Load Capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF. 9. Both outputs of pair must be terminated, even if only one is being used. 10. Each package must be properly decoupled. 11. AC parameters are measured at 1.5V, unless otherwise indicated. 12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω up to185 MHz and 10-pF load to 200 MHz. 13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF. 14. Tested initially and after any design or process changes that may affect these parameters. 15. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given output frequency. 16. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 17. Rise and fall times are measured between 2.0V and 0.8V. 18. fNOM must be within the frequency range defined by the same FS state. 19. tPWH is measured at 2.0V. tPWL is measured at 0.8V. Document #: 38-07336 Rev. *D Page 7 of 10 RoboClock CY7B9945V AC Test Loads and Waveforms[23] 3.3V R1 For LOCK output only R1 = 910 Ω R2 = 910 Ω CL < 30 pF For all other outputs OUTPUT R1 = 100 Ω CL R2 = 100 Ω CL < 25 pF to 185 MHz or 10 pF at 200 MHz (Includes fixture and probe capacitance) R2 (a) LVTTL AC Test Load 3.3V 2.0V GND < 1 ns 0.8V 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform AC Timing Diagram tREFpwl tREFpwh REF t SKEWPR tPD t PWH 2.0V FB 0.8V tCCJ1-3,4-12 Q [1:2]Q[0:3] t SKEWBNK [1:2]Q[0:3] REF TO DEVICE 1 and 2 tODCV tPD FB DEVICE1 tPDELTA Q t SKEW0,1 Other Q FB DEVICE2 t SKEW0,1 tODCV t SKEWBNK t PWL [1:2]Q[1,3] t SKEWPR [1:2]Q[0,2] tPDELTA Notes: 20. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period. 21. Measured at 0.5V deviation from starting voltage. 22. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz. 23. These figures are for illustration purposes only. The actual ATE loads may vary. Document #: 38-07336 Rev. *D Page 8 of 10 RoboClock CY7B9945V Ordering Information Propagation Delay (ps) 250 500 250 500 Max. Speed (MHz) 200 200 200 200 Ordering Code CY7B9945V-2AC CY7B9945V-5AC CY7B9945V-2AI CY7B9945V-5AI Package Name A52 A52 A52 A52 Package Type 52-lead Thin Quad Flat Pack 52-lead Thin Quad Flat Pack 52-lead Thin Quad Flat Pack 52-lead Thin Quad Flat Pack Operating Range Commercial Commercial Industrial Industrial Package Diagram 52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** RoboClock is a registered trademark, and Total Timing Budget and TTB are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07336 Rev. *D Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. RoboClock CY7B9945V Document History Page Document Title: CY7B9945V RoboClock High-speed Multi-phase PLL Clock Buffer Document Number: 38-07336 REV. ** *A *B ECN NO. 111747 116572 119078 Issue Date 03/04/02 09/05/02 10/16/02 Orig. of Change CTK HWT HWT New Data Sheet Added TTB Features Corrected the following items in the Electrical Characteristics table: IIIL,IIIH,IIIM specifications from: three-level input pins excluding FBFO to FS[0:2],IF[0:3],FBDS[0:1] and FBFO to 2F[0:1],[1:2]DS[0:1],FBFO Common Mode Range (VCOM) from VCC to VCC–0.2 Corrected typo TQFP to LQFP in Features Corrected typo LQFP to TQFP in Features Added clock input frequency (fin) specifications in the switching characteristics table. Description of Change *C *D 124645 128464 03/20/03 07/25/03 RGL RGL Document #: 38-07336 Rev. *D Page 10 of 10