CY7C1011CV33-12ZI

CY7C1011CV33 2-Mbit (128K x 16) Static RAM Features • Pin equivalent to CY7C1011BV33 • High speed — tAA = 10 ns • Low active power — 360 mW (max.) • Data Retention at 2.0 • Automatic power-down when deselected • Independent control of upper and lower bits • Easy memory expansion with CE and OE features • Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin TQFP and non Pb-free 48-ball VFBGA packages Functional Description The CY7C1011CV33 is a high-performance CMOS Static RAM organized as 131,072 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011CV33 is available in a standard 44-pin TSOP II package with center power and ground pinout, a 44-pin Thin Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch ball grid array (VFBGA) package. Logic Block Diagram INPUT BUFFER Pin Configuration TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 128K x 16 ARRAY I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC ROW DECODER A9 A10 A 11 A 12 A 13 A 14 A 15 A 16 SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05232 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 6, 2006 [+] [+] Feedback CY7C1011CV33 Selection Guide –10 Maximum Access Time Maximum Operating Current Com’l Ind’l Maximum CMOS Standby Current Com’l/Ind’l 10 90 100 10 –12 12 85 95 10 –15 15 80 90 10 mA Unit ns mA Pin Configurations 44-pin TQFP (Top View) BHE 35 A16 BLE 34 33 32 31 30 29 28 27 26 25 24 23 21 12 13 14 16 17 18 15 19 20 22 A13 A15 A14 A11 A10 38 A9 37 OE 36 A12 40 1 44 43 42 41 39 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 11 I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC WE A0 A1 NC A5 A6 A2 A3 48-ball VFBGA (Top View) 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 3 A0 A3 A5 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H I/O11 NC I/O12 I/O13 NC A8 NC A14 A12 A9 Document #: 38-05232 Rev. *E A4 A7 A8 Page 2 of 11 [+] [+] Feedback CY7C1011CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND [1] Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] .................................–0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range –10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Leakage Current GND < VI < VCC Output Leakage Current GND < VOUT < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l/ Ind’l Com’l Ind’l Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 –1 –1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 90 100 40 2.0 –0.3 –1 –1 Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 85 95 40 2.0 –0.3 –1 –1 –12 Min. Max. 2.4 0.4 VCC + 0.3 0.8 +1 +1 80 90 40 –15 Min. Max. Unit V V V V µA µA mA mA mA ISB2 10 10 10 mA Capacitance[2] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Thermal Resistance[2] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board TSOP II 44.56 10.75 TQFP 42.66 14.64 VFBGA 46.98 9.63 Unit °C/W °C/W Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05232 Rev. *E Page 3 of 11 [+] Feedback CY7C1011CV33 AC Test Loads and Waveforms[3] 10-ns devices: OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Z = 50Ω 12-, 15-ns devices: 3.3V R 317 Ω 30 pF* OUTPUT 30 pF R2 351Ω (a) (b) High-Z characteristics: R 317 Ω 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF R2 351Ω Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) AC Switching Characteristics Over the Operating Range[4] –10 Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE LOW to CE HIGH to High-Z[6, 7] Low-Z[7] High-Z[6, 7] 0 10 5 0 6 0 6 3 5 0 12 6 0 7 0 5 3 6 0 15 7 3 10 5 0 6 3 7 1 10 10 3 12 6 0 7 1 12 12 3 15 7 1 15 15 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. –12 Max. Min. –15 Max. Unit CE LOW to Power-up CE HIGH to Power-down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Notes: 3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load shown in (b). High-Z characteristics are tested for all speeds using the test load shown in (d). 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. Document #: 38-05232 Rev. *E Page 4 of 11 [+] [+] Feedback CY7C1011CV33 AC Switching Characteristics Over the Operating Range[4] (continued) –10 Parameter Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW [8, 9] –12 Min. 12 8 8 0 0 8 6 0 3 5 6 8 10 Max. Min. 15 10 10 0 0 10 7 0 3 –15 Max. Unit ns ns ns ns ns ns ns ns ns 7 ns ns Description Min. 10 7 7 0 0 7 5 0 3 7 Max. Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[7] WE LOW to High-Z[6, 7] Byte Enable to End of Write Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 11. WE is HIGH for read cycle. Document #: 38-05232 Rev. *E Page 5 of 11 [+] [+] Feedback CY7C1011CV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05232 Rev. *E Page 6 of 11 [+] [+] Feedback CY7C1011CV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Document #: 38-05232 Rev. *E Page 7 of 11 [+] [+] Feedback CY7C1011CV33 Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1011CV33-10ZC CY7C1011CV33-10ZXC CY7C1011CV33-10ZXI CY7C1011CV33-10BVI CY7C1011CV33-12ZC CY7C1011CV33-12ZXC CY7C1011CV33-12ZI CY7C1011CV33-12ZXI CY7C1011CV33-12AXI CY7C1011CV33-12BVI CY7C1011CV33-15ZXC CY7C1011CV33-15AI Package Name 51-85087 Package Type 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TSOP II (Pb-Free) 48-ball (6 x 8 x 1 mm) VFBGA 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TSOP II 44-pin TSOP II (Pb-Free) 44-pin TQFP (Pb-Free) 48-ball (6 x 8 x 1 mm) VFBGA 44-pin TSOP II (Pb-Free) 44-pin TQFP Operating Range Commercial Industrial Commercial Industrial 12 51-85150 51-85087 15 51-85064 51-85150 51-85087 51-85064 Commercial Industrial Document #: 38-05232 Rev. *E Page 8 of 11 [+] [+] Feedback CY7C1011CV33 Package Diagrams 44-Pin TSOP II (51-85087) 51-85087-*A 44-pin Thin Plastic Quad Flat Pack (51-85064) 12.00±0.25 SQ 10.00±0.10 SQ 44 34 0° MIN. 1 33 0.37±0.05 STAND-OFF 0.05 MIN. 0.15 MAX. R. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE R. 0.08 MIN. 0.20 MIN. 0.20 MIN. 0-7° 0.60±0.15 1.00 REF. 11 23 0.80 B.S.C. DETAIL A 12 22 NOTE: 1. JEDEC STD REF MS-026 SEATING PLANE 1.60 MAX. 12°±1° (8X) 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 1.40±0.05 0.10 0.20 MAX. 51-85064-*C SEE DETAIL A Document #: 38-05232 Rev. *E Page 9 of 11 [+] [+] Feedback CY7C1011CV33 Package Diagrams (continued) 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 TOP VIEW A B C 8.00±0.10 8.00±0.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.00±0.10 A 1.875 0.75 3.75 B 6.00±0.10 0.55 MAX. 0.25 C 0.15(4X) 0.21±0.05 0.10 C 51-85150-*D SEATING PLANE 0.26 MAX. C 1.00 MAX All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05232 Rev. *E Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1011CV33 Document History Page Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM Document Number: 38-05232 REV. ** *A *B ECN NO. 117132 118057 119702 Issue Date 07/31/02 08/19/02 10/11/02 Orig. of Change HGK HGK DFP New Data Sheet Pin configuration for 48-ball FBGA correction Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1 from 8 to 10 mA Added lead-free parts in Ordering Information Table Corrected typo in the Logic Block Diagram on page# 1 Incuded the Maximum Ratings for Static Discharge Voltage and Latch up Current on page# 3 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Added Thermal Resistance Table Description of Change *C *D 386106 498501 See ECN See ECN PCI NXR *E 522620 See ECN VKN Document #: 38-05232 Rev. *E Page 11 of 11 [+] [+] Feedback