CY7C1041BNL-15ZXCT

CY7C1041BN 256K × 16 Static RAM 256K × 16 Static RAM Features Functional Description ■ Temperature range: ❐ Commercial: 0 °C to 70 °C ❐ Automotive-A: –40 °C to 85 °C The CY7C1041BN is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. ■ High speed ❐ tAA = 15 ns ■ Low active power ■ Low CMOS standby power ❐ 2.75 mW (max.) ■ 2.0 V data retention (400 W at 2.0 V retention) ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free and non Pb-free 44-pin TSOP II and molded 44-pin (400-Mil) SOJ packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BN is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram Buffer 256K x 16 Array I/O0–I/O7 Sense Amps A0 A1 A2 A3 A4 A5 A6 A7 A8 Row Decoder Input I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 Column Decoder Cypress Semiconductor Corporation Document Number: 001-06496 Rev. *L • 198 Champion Court BHE WE CE OE BLE • San Jose, CA 95134-1709 • 408-943-2600 Revised April 15, 2019 CY7C1041BN Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Document Number: 001-06496 Rev. *L Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1041BN Selection Guide Description -15 Maximum access time Maximum operating current Commercial Automotive-A Maximum CMOS standby current Commercial Automotive-A -20 Unit 15 20 ns 190 170 mA – 190 – 0.5 0.5 mA – 6 Pin Configurations Figure 1. 44-pin TSOP II / SOJ pinout (Top View) SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 Document Number: 001-06496 Rev. *L 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Page 3 of 16 CY7C1041BN Maximum Ratings DC voltage applied to outputs in High Z State [1] ................................ –0.5 V to VCC + 0.5 V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Storage temperature ................................ –65 °C to +150 °C Current into outputs (LOW) ........................................ 20 mA Ambient temperature with power applied ................................... –55 °C to +125 °C Operating Range Supply voltage on VCC to relative GND[1] ............................–0.5 V to +7.0 V Range Ambient Temperature [2] VCC 0 °C to +70 °C 5 V ± 0.5 Commercial Automotive-A –40 °C to +85 °C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage Min VCC, IOH = –4.0 mA -15 -20 Unit Min Max Min Max 2.4 – 2.4 – V VOL Output LOW voltage Min VCC, IOL = 8.0 mA – 0.4 – 0.4 V VIH[1] Input HIGH voltage – 2.2 VCC + 0.5 2.2 VCC + 0.5 V VIL[1] Input LOW voltage – –0.5 0.8 –0.5 0.8 V IIX Input load current GND < VIN < VCC –1 +1 –1 +1 µA IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC operating supply current Max VCC, f = fMAX = 1/tRC – 190 – 170 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE power-down current – CMOS inputs Max VCC, Commercial CE > VCC – 0.3 V, Automotive-A VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Commercial Automotive-A – – – 190 mA – 40 – 40 mA – 0.5 – 0.5 mA – – – 6 mA Notes 1. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the case temperature. Document Number: 001-06496 Rev. *L Page 4 of 16 CY7C1041BN Capacitance Parameter [3] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 481  5V Output R1 481 5V 3.0 V Output R2 255  30 pF Including JIG and Scope Equivalent to: Output Including JIG and Scope (a) R2 255  5 pF GND All Input Pulses 90% 90% 10% 10% 3 ns  3 ns (b) Thé venin Equivalent 167  1.73 V Data Retention Characteristics Over the Operating Range (Commercial only) Parameter VDR ICCDR tCDR [5] Conditions[4] Description VCC for data retention – Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Chip deselect to data retention time tR[6] Operation recovery time Min Max Unit 2.0 – V – 200 A 0 – ns tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform Data Retention Mode VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. No input may exceed VCC + 0.5 V. 5. Tested initially and after any design or process changes that may affect these parameters. 6. tr < 3 ns for the –15 speed. tr < 5 ns for the -20 and slower speeds. Document Number: 001-06496 Rev. *L Page 5 of 16 CY7C1041BN Switching Characteristics Over the Operating Range Parameter [7] Description -15 -20 Min Max Min Max Unit Read Cycle tpower VCC(typical) to the first access [8] 1 – 1 – s tRC Read cycle time 15 – 20 – ns tAA Address to data valid – 15 – 20 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 15 – 20 ns tDOE OE LOW to data valid – 7 – 8 ns tLZOE OE LOW to low Z 0 – 0 – ns – 7 – 8 ns 3 – 3 – ns – 7 – 8 ns 0 – 0 – ns [9, 10] tHZOE OE HIGH to high Z tLZCE CE LOW to low Z [10] [9, 10] tHZCE CE HIGH to high Z tPU CE LOW to power-up tPD CE HIGH to power-down – 15 – 20 ns tDBE Byte enable to data valid – 7 – 8 ns tLZBE Byte enable to low Z 0 – 0 – ns Byte disable to high Z – 7 – 8 ns tHZBE Write Cycle [11, 12] tWC Write cycle time 15 – 20 – ns tSCE CE LOW to write end 12 – 13 – ns tAW Address setup to write end 12 – 13 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 12 – 13 – ns tSD Data setup to write end 8 – 9 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low Z [13] 3 – 3 – ns – 7 – 8 ns 12 – 13 – ns [13, 14] tHZWE WE LOW to high Z tBW Byte enable to end of write Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. This part has a voltage regulator which steps down the voltage from 5 V to 3.3 V internally. tpower time has to be provided initially before a read/write operation is started. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady-state voltage. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady-state voltage. Document Number: 001-06496 Rev. *L Page 6 of 16 CY7C1041BN Switching Waveforms Figure 4. Read Cycle No. 1 [15, 16] tRC Address tOHA Data I/O tAA Previous Data Valid Data Out Valid Figure 5. Read Cycle No. 2 (OE Controlled) [16, 17] Address tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE Data I/O High Impedance Data Out Valid tLZCE VCC Supply Current tHZBE High Impedance tPD tPU 50% ICC 50% ISB Notes 15. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE transition LOW. Document Number: 001-06496 Rev. *L Page 7 of 16 CY7C1041BN Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [18, 19] tWC Address CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD Data In Valid Data I/O Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC Address BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD Data I/O tHD Data In Valid Notes 18. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 001-06496 Rev. *L Page 8 of 16 CY7C1041BN Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC Address tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE Data I/O tSD tHD Data In Valid tLZWE Note 20. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 001-06496 Rev. *L Page 9 of 16 CY7C1041BN Truth Table CE OE WE BLE BHE I/O0–I/O7 H X X X X High Z High Z Power-down Standby (ISB) L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out High Z Read lower bits only Active (ICC) L L H H L High Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in High Z Write lower bits only Active (ICC) L X L H L High Z Data in Write upper bits only Active (ICC) L H H X X High Z High Z Selected, Outputs disabled Active (ICC) L X X H H High Z High Z Selected, Outputs disabled Active (ICC) Document Number: 001-06496 Rev. *L I/O8–I/O15 Mode Power Page 10 of 16 CY7C1041BN Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 20 Ordering Code CY7C1041BN-20ZSXA Package Name 51-85087 Package Type 44-pin TSOP Type II Operating Range Automotive-A Ordering Code Definitions CY 7 C 1 04 1 BN X - XX XX X X Temperature Range: A = Automotive-A Pb-free Package Type: ZS = 44-pin TSOP Type II Speed: XX = 20 ns Power: X = blank blank = High Power Process Technology: BN = 180 nm Technology Bus Width: 1 = × 16 bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06496 Rev. *L Page 11 of 16 CY7C1041BN Package Diagram Figure 9. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-06496 Rev. *L Page 12 of 16 CY7C1041BN Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor µA microampere I/O Input/Output mA milliampere OE Output Enable mV millivolt SRAM Static Random Access Memory mW milliwatt TSOP Thin Small Outline Package ns nanosecond WE Write Enable pF picofarad V volt W watt Document Number: 001-06496 Rev. *L Symbol Unit of Measure Page 13 of 16 CY7C1041BN Document History Page Document Title: CY7C1041BN, 256K × 16 Static RAM Document Number: 001-06496 Revision ECN Orig. of Change Submission Date ** 424111 NXR 02/02/2006 New data sheet. *A 498575 NXR 08/31/2006 Added Automotive-A Temperature Range related information in all instances across the document. Updated Ordering Information: Updated part numbers. *B 2897061 AJU 03/22/2010 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85082 – Changed revision from *B to *C. spec 51-85087 – Changed revision from *A to *C. *C 2906679 NXR 04/07/2010 Updated Ordering Information: Updated part numbers. *D 3086674 PRAS 11/15/2010 Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. Updated Package Diagram: Removed spec 51-85082 *C. Added Acronyms. Updated to new template. *E 3232637 PRAS 04/20/2011 Updated Electrical Characteristics: Changed unit for IIX and IOZ parameters from mA to µA. Added Units of Measure. Updated to new template. *F 3383869 TAVA 09/26/2011 Removed Industrial Temperature Range related information in all instances across the document. Replaced “Commercial-L” with “Commercial” in all instances across the document. Rearranged sections for better clarity. Updated Switching Waveforms: Modified the notes in figures under Read cycle and Write cycle sections. Updated Package Diagram: spec 51-85087 – Changed revision from *C to *D. Completing Sunset Review. *G 4113666 VINI 09/04/2013 Updated Package Diagram: spec 51-85087 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. *H 4545523 VINI 10/20/2014 Updated Features: Removed “1540 mW (max.)” under “Low active power”. Updated Truth Table: Added a row in the last (to show what happens when both BLE and BHE are high). Completing Sunset Review. *I 4576406 VINI 01/16/2015 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Switching Waveforms: Added Note 20 and referred the same note in Figure 8. Document Number: 001-06496 Rev. *L Description of Change Page 14 of 16 CY7C1041BN Document History Page (continued) Document Title: CY7C1041BN, 256K × 16 Static RAM Document Number: 001-06496 Revision ECN Orig. of Change Submission Date *J 5508709 VINI 11/03/2016 *K 5977242 AESATMP8 11/27/2017 Updated Cypress Logo and Copyright. *L 6544621 VINI 04/15/2019 Updated to new template. Document Number: 001-06496 Rev. *L Description of Change Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. Page 15 of 16 CY7C1041BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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