CY7C1371BV25-100AC

CY7C1373BV25 CY7C1371BV25 512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Registered inputs for Flow-Thru operation • Byte Write capability • Common I/O architecture • Single 2.5V +5% power supply • Fast clock-to-output times — 7.5 ns (for 117-MHz device) The CY7C1371BV25 and CY7C1373BV25 are 2.5V, 512K×36 and 1M×18 Synchronous Flow-Thru Burst SRAMs, respectively, designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371BV25/CY7C1373BV25 is equipped with the advanced No Bus Latency™ (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions.The CY7C1371BV25/CY7C1373BV25 is pincompatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). — 8.5 ns (for 100-MHz device) • • • • • • — 10 ns (for 83-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Available in 100-pin TQFP and 119-ball BGA packages Burst Capability–linear or interleaved burst order JTAG boundary scan for BGA packaging version Automatic power-down available using ZZ mode or CE deselect Write operations are controlled by the Byte Write Selects for CY7C1371BV25 and BWSa,b for (BWSa,b,c,d CY7C1373BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. ZZ may be tied to LOW if it is not used. Synchronous Chip Enable (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CLK CE D Data-In REG. Q ADV/LD Ax CY7C1373 AX CY7C1371 X = 18:0 DQX X= a, b, c, d X = a, b X = 19:0 DPX X = a, b, c, d X = a, b BWSX X = a, b, c, d X = a, b CEN CE1 CE2 CE3 WE BWSx CONTROL and WRITE LOGIC 256KX36/ 512KX18 MEMORY ARRAY DQx DPx Mode OE Selection Guide 117 MHz 100 MHz 83 MHz Unit Maximum Access Time 7.5 8.5 10.0 ns Maximum Operating Current 210 190 160 mA Maximum CMOS Standby Current 30 30 30 mA Cypress Semiconductor Corporation Document #: 38-05250 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 18, 2003 CY7C1373BV25 CY7C1371BV25 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1373BV25 (1M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A DNU A A A A A A DNU DNU DNU A A A A A A A MODE A A A A A1 A0 DNU DNU VSS VDD Document #: 38-05250 Rev. *A DPb NC DQb NC DQb NC VDDQ VDDQ VSS VSS DQb NC DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb VSS NC NC VDD NC VDD ZZ VSS DQa DQb DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DPb DQa NC VSS VSS VDDQ VDDQ DQa NC DQa NC DPa NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C1371BV25 (512K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DNU DNU VSS VDD DPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ A A A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Packages Page 2 of 25 CY7C1373BV25 CY7C1371BV25 Pin Configurations (continued) 119-ball BGA CY7C1371BV25 (512K × 36) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC CE2 A ADV/LD A CE3 NC NC A A VDD A A NC DQc DPc VSS NC VSS DPb DQb DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS OE VSS DQb VDDQ DQc DQc VDDQ DQc DQc VDD BWSc VSS NC A WE VDD BWSb VSS NC DQb DQb VDD DQb DQb VDDQ DQd DQd VSS CLK VSS DQa DQa DQd DQd BWSd NC BWSa DQa DQa VDDQ DQd DQd DQd VSS VSS CEN A1 VSS VSS DQa DQa VDDQ DQa DQd DPd VSS A0 VSS DPa DQa NC A MODE VDD VSS A NC NC 64M A A A 32M ZZ VDDQ TMS TDI TCK TDO NC VDDQ CY7C1373BV25 (1M × 18) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M NC CE2 A ADV/LD A CE3 NC NC A A VDD A A DQb NC NC DQb CE1 VSS VSS DPa NC VSS VSS NC NC NC DQa VDDQ NC VSS VSS DQa VDDQ NC DQb DQb NC VDDQ VDD BWSb VSS NC WE VDD VSS VSS NC NC DQa VDD DQa NC VDDQ NC VSS CLK VSS NC DQa DQb DQb NC VSS NC VDDQ DQb VSS CEN BWSa VSS DQa NC NC VDDQ OE A N P DQb NC VSS A1 VSS DQa NC NC DPb VSS A0 VSS NC DQa R T U NC A MODE VDD Vss A NC 64M A A A A VDDQ TMS TDI 32M TCK TDO NC ZZ VDDQ Document #: 38-05250 Rev. *A Page 3 of 25 CY7C1373BV25 CY7C1371BV25 Pin Configurations (continued) 165-ball Bump FBGA CY7C1371BV25 (512K × 36)–11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWSc BWSb CE3 CEN ADV/LD A A NC B C D E F G H J K L M N P NC DPc A NC CE2 VDDQ BWSd VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC 128M DPb DQb R DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb NC DQd VDD DQd NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ DQa DQd DQd DQd DQd VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DPd NC VDDQ VSS NC NC NC VSS VDDQ NC DPa NC 64M A A TDI A1 TDO A A A NC MODE 32M A A TMS A0 TCK A A A A 11 CY7C1373BV25 (1M × 18)–11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 A NC A CE1 BWSb NC CE3 CEN ADV/LD A A A B C D E F G H J K L M N P NC NC A NC CE2 VDDQ NC VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC 128M DPa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDD NC NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ NC DQb DQb NC NC VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa NC NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC NC 64M A A TDI A1 TDO A A A NC MODE 32M A A TMS A0 TCK A A A A R Document #: 38-05250 Rev. *A Page 4 of 25 CY7C1373BV25 CY7C1371BV25 Pin Definitions (100-Pin TQFP) Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK. BWSa BWSb BWSc BWSd InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[x] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQ a,b,c and d are 8 bits wide. DPa DPb DPc DPd I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. DP a,b,c and d are 1 bit wide ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. MODE Input-pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. VDD Power Supply Power supply inputs to the core of the device. Document #: 38-05250 Rev. *A Page 5 of 25 CY7C1373BV25 CY7C1371BV25 Pin Definitions (100-Pin TQFP) (continued) Pin Name I/O Type Pin Description VDDQ I/O Power Supply Power supply for the I/O circuitry. VSS Ground Ground for the device. Should be connected to ground of the system. TDO JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). TDI JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). TMS Test Mode Select Synchronous This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only). TCK JTAG serial clock Serial clock to the JTAG circuit (BGA only) 32M 64M 128M – No connects. Reserved for address expansion. NC – No connects. Pins are not internally connected. DNU – Do not use pins. Functional Overview The CY7C1371BV25/CY7C1373BV25 is a Synchronous Flow-Through Burst NoBL SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting Chip Enable(s) (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). Byte Write Selects can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP, CE1 on the BGA) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core Document #: 38-05250 Rev. *A and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The CY7C1371BV25/CY7C1373BV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip Enable(s) asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DP. Page 6 of 25 CY7C1373BV25 CY7C1371BV25 On the next clock rise the data presented to DQ and DP (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by Byte Write Select signals. The CY7C1371BV25/ CY7C1373BV25 provide byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1371BV25/CY7C1373BV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DP are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1371BV25/CY7C1373BV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWSa,b,c,d/BWSa,b inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address used Operation CE CEN ADV/ LD WE BWSx CLK Comments Deselected External 1 0 0 X X L-H I/Os three-state following next recognized clock. Suspend – X 1 X X X L-H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L-H Address latched. Begin Write External 0 0 0 0 Valid L-H Address latched, data presented two valid clocks later. Burst READ Operation Internal X 0 1 X X L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst WRITE Operation Internal X 0 1 X Valid L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWSa,b,c,d/BWSa,b. Interleaved Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Document #: 38-05250 Rev. *A Page 7 of 25 CY7C1373BV25 CY7C1371BV25 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 20 mA tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns Write Cycle Description Function (CY7C1371BV25) WE BWSd BWSc BWSb BWSa 1 X X X X Read Write – No Bytes Written 0 1 1 1 1 Write Byte 0 − (DQa and DPa) 0 1 1 1 0 Write Byte 1 − (DQb and DPb) 0 1 1 0 1 Write Bytes 1, 0 0 1 1 0 0 Write Byte 2 − (DQc and DPc) 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Byte 3 − (DQb and DPd) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0 Function (CY7C1373BV25) Read WE BWSb BWSa 1 x x Write – No Bytes Written 0 1 1 Write Byte 0 – (DQa and DPa) 0 1 0 Write Byte 1 – (DQb and DPc) 0 0 1 Write Both Bytes 0 0 0 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature The CY7C1371BV25/CY7C1373BV25 incorporates a serial boundary scan TAP in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) – Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Notes: 1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables. CE = 0 stands for ALL Chip Enables are active. 2. Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN = 1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05250 Rev. *A Page 8 of 25 CY7C1373BV25 CY7C1371BV25 Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (See TAP Controller State diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset TAP Instruction Set A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Test Data Out (TDO) Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. Bypass Register EXTEST To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP Document #: 38-05250 Rev. *A Page 9 of 25 CY7C1373BV25 CY7C1371BV25 controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (TCS and TCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05250 Rev. *A Page 10 of 25 CY7C1373BV25 CY7C1371BV25 TAP Controller State Diagram 1[7] TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 7. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05250 Rev. *A Page 11 of 25 CY7C1373BV25 CY7C1371BV25 TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register x . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[8, 9] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −4.0 mA 2.0 V VOH2 Output HIGH Voltage IOH = −100 µA VDD−0.2 V VOL1 Output LOW Voltage IOL = 8.0 mA 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage 1.7 VDD+0.3 V VIL Input LOW Voltage −0.3 0.7 V IX Input Load Current −5 5 µA GND ≤ VI ≤ VDDQ Notes: 8. All Voltage referenced to Ground. 9. Overshoot: VIH(AC)