Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
THIS SPEC IS OBSOLETE
Spec No: 38-05356
Spec Title: CY7C1461AV33/CY7C1463AV33, 36-MBIT (1M X 36/2M X 18)
FLOW-THROUGH SRAM WITH NOBL(TM) ARCHITECTURE
Replaced by:
None
CY7C1461AV33
CY7C1463AV33
36-Mbit (1M × 36/2M × 18)
Flow-Through SRAM with NoBL™ Architecture
336-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
The
CY7C1461AV33/CY7C1463AV33
are
3.3 V,
1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs
designed specifically to support unlimited true back-to-back read
and write operations without the insertion of wait states. The
CY7C1461AV33/CY7C1463AV33 is equipped with the advanced
NoBL logic required to enable consecutive read and write
operations with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
■
Byte write capability
■
3.3 V and 2.5 V I/O power supply
■
Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
■
Clock Enable (CEN) pin to enable clock and suspend operation
■
Synchronous self timed writes
■
Asynchronous Output Enable
■
CY7C1461AV33,
CY7C1463AV33
available
JEDEC-standard Pb-free 100-pin TQFP package.
■
Three chip enables for simple depth expansion
■
Automatic power down feature available using ZZ mode or CE
deselect
■
Burst capability – linear or interleaved burst order
■
Low standby power
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
in
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
310
mA
Maximum CMOS Standby Current
120
mA
Cypress Semiconductor Corporation
Document Number: 38-05356 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 26, 2016
CY7C1461AV33
CY7C1463AV33
Logic Block Diagram – CY7C1461AV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
BW C
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05356 Rev. *O
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Page 2 of 24
CY7C1461AV33
CY7C1463AV33
Logic Block Diagram – CY7C1463AV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
BW B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05356 Rev. *O
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
E
E
READ LOGIC
SLEEP
CONTROL
Page 3 of 24
CY7C1461AV33
CY7C1463AV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Truth Table for Read/Write ............................................ 11
Truth Table for Read/Write ............................................ 11
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
Electrical Characteristics ............................................... 12
Capacitance .................................................................... 13
Document Number: 38-05356 Rev. *O
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 4 of 24
CY7C1461AV33
CY7C1463AV33
Pin Configurations
A
40
41
42
43
44
45
46
47
48
49
50
VDD
NC/72M
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
Document Number: 38-05356 Rev. *O
81
A
82
83
A
A
84
ADV/LD
VSS
90
85
VDD
91
OE
CE3
92
86
BWA
93
CEN
BWB
94
87
BWC
95
WE
BWD
96
CLK
CE2
97
89
CE1
A
98
88
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1461AV33
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 5 of 24
CY7C1461AV33
CY7C1463AV33
Pin Configurations (continued)
A
42
43
44
45
46
47
48
49
50
A
A
A
A
A
A
A
A
41
NC/72M
40
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document Number: 38-05356 Rev. *O
81
A
82
A
83
A
84
85
ADV/LD
OE
86
CEN
90
87
VSS
91
WE
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
97
96
CE1
CE2
A
98
88
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1463AV33
A
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 6 of 24
CY7C1461AV33
CY7C1463AV33
Pin Definitions
Pin Name
A0, A1, A
I/O
Description
InputAddress Inputs. Used to select one of the address locations. Sampled at the rising edge of the CLK.
Synchronous A[1:0] are fed to the two-bit burst counter.
BWA, BWB,
InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
BWC, BWD Synchronous rising edge of CLK.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance or Load Input. Used to advance the on-chip address counter or load a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After deselecting, drive ADV/LD LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside
Asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ
InputZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition with
Asynchronous data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull down.
DQs
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
VDD
VDDQ
Input Strap
Pin
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for I/O Circuitry.
VSS
Ground
NC
N/A
No Connects. Not internally connected to the die.
Ground for the Device.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
Document Number: 38-05356 Rev. *O
Page 7 of 24
CY7C1461AV33
CY7C1463AV33
Pin Definitions (continued)
Pin Name
I/O
Description
NC/576M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/1G
N/A
Not Connected to the Die. Can be tied to any voltage level.
Functional Overview
The CY7C1461AV33/CY7C1463AV33 is a synchronous flow
through burst SRAM designed specifically to eliminate wait
states during Write-Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the clock enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized
and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). BWX can be used to conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
The write enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW for the device to
drive out the requested data. On the subsequent clock, another
operation (Read/Write/Deselect) can be initiated. When the
SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1461AV33/CY7C1463AV33 has an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four reads without reasserting the address inputs.
ADV/LD must be driven LOW to load a new address into the
Document Number: 38-05356 Rev. *O
SRAM, as described in the Single Read Accesses section. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps
around when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table on page 10
for details) inputs is latched into the device and the write is
complete. Additional accesses (read/write/deselect) can be
initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1461AV33/CY7C1463AV33 provides byte write
capability that is described in the truth table. Asserting the (WE)
with the selected byte write select input selectively writes to only
the desired bytes. Bytes not selected during a byte write
operation remains unaltered. A synchronous self timed write
mechanism is provided to simplify the write operations. Byte
write capability is included to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1461AV33/CY7C1463AV33 is a common I/O
device, data must not be driven into the device when the outputs
are active. The OE can be deasserted HIGH before presenting
data to the DQs and DQPX inputs. This tri-states the output
drivers. As a safety precaution, DQs and DQPX are automatically
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
Burst Write Accesses
The CY7C1461AV33/CY7C1463AV33 has an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in the Single Write Accesses on page 8.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BWX inputs
must be driven in each cycle of the burst write, to write the correct
bytes of data.
Page 8 of 24
CY7C1461AV33
CY7C1463AV33
Sleep Mode
Interleaved Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, and CE3,
must remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > VDD– 0.2 V
IDDZZ
Sleep mode standby current
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 38-05356 Rev. *O
Min
Max
Unit
–
100
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 9 of 24
CY7C1461AV33
CY7C1463AV33
Truth Table
The truth table for CY7C1461AV33/CY7C1463AV33 follows.
Operation [1, 2, 3, 4, 5, 6, 7]
Address Used CE1 CE2 CE3
ZZ
ADV/LD WE BWX OE
CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tristate
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tristate
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tristate
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tristate
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tristate
Next
X
X
X
L
H
X
X
H
L
L->H
Tristate
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tristate
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tristate
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read Cycle (Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Notes
1. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BWX, and WE. See truth table for read or write.
3. When a write cycle is detected, all IOs are tristated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 38-05356 Rev. *O
Page 10 of 24
CY7C1461AV33
CY7C1463AV33
Truth Table for Read/Write
Function (CY7C1461AV33) [8, 9]
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write – No Bytes Written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Truth Table for Read/Write
Function (CY7C1463AV33) [8, 9]
WE
BWb
BWa
Read
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Notes
8. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects are
asserted, see truth table for details.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 38-05356 Rev. *O
Page 11 of 24
CY7C1461AV33
CY7C1463AV33
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch Up Current .................................................. > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature
Commercial 0 °C to +70 °C
Industrial
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% /
+ 10%
2.5 V – 5% to
VDD
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
Test Conditions
for 3.3 V I/O
for 2.5 V I/O
Min
3.135
3.135
2.375
Max
3.6
VDD
2.625
Unit
V
V
V
V
V
V
V
V
V
V
V
VOH
Output HIGH voltage
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
VOL
Output LOW voltage
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
VIH
Input HIGH voltage[10]
for 3.3 V I/O
for 2.5 V I/O
2.4
2.0
–
–
2.0
1.7
VIL
Input LOW voltage[10]
for 3.3 V I/O
for 2.5 V I/O
–0.3
–0.3
–
–
0.4
0.4
VDD + 0.3 V
VDD + 0.3 V
0.8
0.7
IX
Input leakage current except ZZ GND VI VDDQ
and MODE
Input current of MODE
Input = VSS
Input = VDD
Input current of ZZ
Input = VSS
Input = VDD
–5
5
A
–30
–
–5
–
–5
–
5
–
30
5
A
A
A
A
A
IOZ
IDD
Output leakage current
GND VI VDDQ, Output Disabled
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
310
mA
ISB1
Automatic CE power down
current – TTL Inputs
–
180
mA
ISB2
Automatic CE power down
current – CMOS Inputs
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN VIH or VIN VIL; f = fMAX, 133 MHz
Inputs Switching
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN 0.3 V or VIN > VDD – 0.3 V, 133 MHz
f = 0, Inputs Static
–
120
mA
ISB3
Automatic CE power down
current – CMOS Inputs
7.5 ns cycle,
133 MHz
–
180
mA
ISB4
Automatic CE Power down
current – TTL Inputs
7.5 ns cycle,
133 MHz
–
135
mA
VDD = Max, Device Deselected,
VIN 0.3 V or VIN > VDDQ – 0.3 V
f = fMAX, Inputs Switching
VDD = Max, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, Inputs Static
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05356 Rev. *O
Page 12 of 24
CY7C1461AV33
CY7C1463AV33
Capacitance
Parameter [12]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
100-pin TQFP Unit
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
6.5
pF
3
pF
5.5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51.
25.21
°C/W
2.28
°C/W
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
10%
GND
R = 351
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
1ns
1ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
90%
10%
90%
10%
90%
10%
90%
GND
R = 1538
(b)
1ns
1ns
(c)
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05356 Rev. *O
Page 13 of 24
CY7C1461AV33
CY7C1463AV33
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
tPOWER[15]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid after CLK Rise
–
6.5
ns
tDOH
Data Output Hold after CLK Rise
2.5
–
ns
2.5
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[16, 17, 18]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [16, 17, 18]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[16, 17, 18]
OE HIGH to Output High Z
[16, 17, 18]
Setup Times
tAS
Address Setup before CLK Rise
1.5
–
ns
tALS
ADV/LD Setup before CLK Rise
1.5
–
ns
tWES
WE, BWX Setup before CLK Rise
1.5
–
ns
tCENS
CEN Setup before CLK Rise
1.5
–
ns
tDS
Data Input Setup before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup before CLK Rise
1.5
–
ns
tAH
Address Hold after CLK Rise
0.5
–
ns
tALH
ADV/LD Hold after CLK Rise
0.5
–
ns
tWEH
WE, BWX Hold after CLK Rise
0.5
–
ns
tCENH
CEN Hold after CLK Rise
0.5
–
ns
tDH
Data Input Hold after CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 3 on page 13 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 13. Transition is measured ±200 mV from steady-state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z
prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 38-05356 Rev. *O
Page 14 of 24
CY7C1461AV33
CY7C1463AV33
Switching Waveforms
Figure 4. Read/Write Waveforms [19, 20, 21]
1
2
3
t CYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05356 Rev. *O
Page 15 of 24
CY7C1461AV33
CY7C1463AV33
Switching Waveforms (continued)
Figure 5. NOP, STALL, and DESELECT Cycles [22, 23, 24]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05356 Rev. *O
Page 16 of 24
CY7C1461AV33
CY7C1463AV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 38-05356 Rev. *O
Page 17 of 24
CY7C1461AV33
CY7C1463AV33
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
CY7C1461AV33-133AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
lndustrial
CY7C1463AV33-133AXC
CY7C1461AV33-133AXI
Ordering Code Definitions
CY 7
C 146X
A V33 - 133 A X X
Temperature range: X = C or I
C = Commercial; I = Industrial
X = Pb-free; X Absent = Leaded
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
V33 = 3.3 V
Process Technology: A 90 nm Technology
Part Identifier: 146X = 1461 or 1463
1461 = FT, 1 Mb × 36 (36 Mb)
1463 = FT, 2 Mb × 18 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05356 Rev. *O
Page 18 of 24
CY7C1461AV33
CY7C1463AV33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05356 Rev. *O
Page 19 of 24
CY7C1461AV33
CY7C1463AV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CEN
Clock Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
I/O
Input/Output
µA
microampere
LSB
Least Significant Bit
mA
milliampere
MSB
Most Significant Bit
mV
millivolt
mm
millimeter
ms
millisecond
ns
nanosecond
NoBL
No Bus Latency
OE
Output Enable
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05356 Rev. *O
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 20 of 24
CY7C1461AV33
CY7C1463AV33
Document History Page
Document Title: CY7C1461AV33/CY7C1463AV33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05356
Revision
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
254911
See ECN
SYT
New data sheet.
Part number changed from previous revision (New and old part number differ
by the letter “A”).
*A
300131
See ECN
SYT
Updated Features (Removed 150 MHz and 117 MHz frequencies related
information).
Updated Selection Guide (Removed 150 MHz and 117 MHz frequencies
related information).
Updated Electrical Characteristics (Removed 150 MHz and 117 MHz
frequencies related information).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to 25.21 °C/W and 2.58 °C/W respectively for 100-pin TQFP
package).
Updated Switching Characteristics (Removed 150 MHz and 117 MHz
frequencies related information).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
165-ball FBGA and 209-ball FBGA packages, added “Pb-free BG and BZ
packages availability” comment below the Ordering Information).
*B
320813
See ECN
SYT
Updated Pin Configurations (Changed H9 pin from VSSQ to VSS for 209-ball
FBGA).
Updated Electrical Characteristics (Changed the test condition for VOL
parameter from VDD = Min. to VDD = Max., replaced the TBD’s with their
respective values for IDD, ISB1, ISB2, ISB3 and ISB4 parameters).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for 165-ball FBGA and 209-ball FBGA
Packages).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
6.5 pF, 3 pF and 5.5 pF from 5 pF, 5 pF and 7 pF for 100-pin TQFP Package).
Updated Ordering Information (Removed “Pb-free BG packages availability”
comment below the Ordering Information).
*C
331551
See ECN
SYT
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 165-ball FBGA and 209-ball FBGA Packages according to JEDEC
standards).
Updated Pin Definitions.
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Changed maximum value of IDDZZ parameter from TBD to 100 mA)).
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, changed maximum value of ISB2 parameter from 100 mA to
120 mA, changed maximum value of ISB4 parameter from 110 mA to 135 mA
respectively).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
7 pF, 7 pF and 6 pF from 5 pF, 5 pF and 7 pF for 165-ball FBGA Package).
Updated Ordering Information (By shading and unshading MPNs according to
availability).
Document Number: 38-05356 Rev. *O
Page 21 of 24
CY7C1461AV33
CY7C1463AV33
Document History Page (continued)
Document Title: CY7C1461AV33/CY7C1463AV33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05356
Revision
ECN No.
Issue Date
Orig. of
Change
Description of Change
*D
417547
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 11 (Changed test condition
from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum
value of IX parameter (corresponding to Input current of MODE (Input = VSS))
from –5 A to –30 A, changed maximum value of IX parameter (corresponding
to Input current of MODE (Input = VDD)) from 30 A to 5 A respectively,
changed minimum value of IX parameter (corresponding to Input current of ZZ
(Input = VSS)) from –30 A to –5 A, changed maximum value of IX parameter
(corresponding to Input current of ZZ (Input = VDD)) from 5 A to 30 A
respectively).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams.
*E
473650
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
and tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Ordering Information (Updated part numbers).
*F
1274733
See ECN
VKN /
AESA
Updated Switching Waveforms (Updated Figure 5 (Corrected typo)).
*G
2499107
See ECN
VKN /
PYRS
Updated Logic Block Diagram – CY7C1465AV33 (Corrected typo).
*H
2897278
03/22/2010
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagrams.
*I
3208774
03/29/2011
NJY
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagrams.
Updated to new template.
*J
3309506
07/12/2011
OSN
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Document Number: 38-05356 Rev. *O
Page 22 of 24
CY7C1461AV33
CY7C1463AV33
Document History Page (continued)
Document Title: CY7C1461AV33/CY7C1463AV33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05356
Orig. of
Change
Revision
ECN No.
Issue Date
*K
3591743
05/10/2012
*L
3690005
07/24/2012
PRIT
No technical updates.
Completing Sunset Review.
*M
4572829
11/18/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*N
4865506
07/30/2015
PRIT
Updated to new template.
Completing Sunset Review.
*O
5373812
07/26/2016
PRIT
Obsolete document.
Completing Sunset Review.
Document Number: 38-05356 Rev. *O
Description of Change
NJY / PRIT Updated Features (Removed CY7C1465AV33 related information, removed
165-ball FBGA package, 209-ball FBGA package related information).
Updated Functional Description (Removed CY7C1465AV33 related
information, removed the Note “For best practices recommendations, refer to
the Cypress application note System Design Guidelines on
www.cypress.com.” and its reference).
Updated Selection Guide (Removed 100 MHz frequency related information).
Removed Logic Block Diagram – CY7C1465AV33.
Updated Pin Configurations (Removed 165-ball FBGA package
(corresponding to CY7C1461AV33 and CY7C1463AV33), 209-ball FBGA
package (corresponding to CY7C1465AV33) related information).
Updated Pin Definitions (Removed JTAG related information).
Updated Functional Overview (Removed CY7C1465AV33 related
information).
Updated Truth Table (Removed CY7C1465AV33 related information).
Removed Truth Table for Read/Write (Corresponding to CY7C1465AV33).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Order (Corresponding to 165-ball FBGA package).
Removed Boundary Scan Order (Corresponding to 209-ball FBGA package).
Updated Electrical Characteristics (Removed 100 MHz frequency related
information).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Switching Characteristics (Removed 100 MHz frequency related
information).
Updated Package Diagrams (Removed 165-ball FBGA package, 209-ball
FBGA package related information).
Replaced all instances of IO with I/O across the document.
Page 23 of 24
CY7C1461AV33
CY7C1463AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
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© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05356 Rev. *O
Revised July 26, 2016
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NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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