CY7C185_11

CY7C185 64-Kbit (8 K × 8) Static RAM Features ■ Functional Description The CY7C185[1] is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input or output pins. The input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. High speed ❐ 15 ns Fast tDOE Low active power ❐ 715 mW Low standby power ❐ 85 mW CMOS for optimum speed/power Easy memory expansion with CE1, CE2 and OE features TTL-compatible inputs and outputs Automatic power-down when deselected Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin (300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded DIP ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram I/O0 INPUT BUFFER I/O1 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 I/O6 8K x 8 ARRAY CE1 CE2 WE OE COLUMN DECODER POWER DOWN I/O7 A10 A11 Selection Guide Description Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -15 15 130 15 -20 20 110 15 -35 35 100 15 Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A12 A0 A9 Cypress Semiconductor Corporation Document #: 38-05043 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 20, 2011 [+] Feedback CY7C185 Contents Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 3 Operating Range ............................................................... 3 Electrical Characteristics ................................................. 3 Capacitance ...................................................................... 4 Switching Characteristics ,Over the Operating Range ................................................. 5 Switching Waveforms ...................................................... 6 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Address Designators ..................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Document #: 38-05043 Rev. *E Page 2 of 15 [+] Feedback CY7C185 Pin Configuration DIP/SOJ Top View NC A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A3 A2 A1 OE A0 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature .................................. –65°C to +150°C Ambient temperature with power applied ............................................. –55°C to +125°C Supply voltage to ground potential ...............–0.5 V to +7.0 V DC voltage applied to outputs in High Z State[2] ...........................................–0.5 V to +7.0 V DC input voltage[2] ........................................–0.5 V to +7.0 V Output current into outputs (LOW) .............................. 20 mA Range Commercial Industrial Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... >200 mA Operating Range Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5 V ± 10% 5 V ± 10% Electrical Characteristics Over the Operating Range –15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic Power-down Current Automatic Power-down Current Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Max Min 2.4 –20 Max Min 2.4 –35 Max Unit V V V V μA μA mA mA 0.4 2.2 –0.5 VCC + 0.3 V 0.8 +5 +5 130 40 2.2 –0.5 –5 –5 0.4 VCC + 0.3 V 0.8 +5 +5 110 20 2.2 –0.5 –5 –5 0.4 VCC + 0.3 V 0.8 +5 +5 100 20 GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., IOUT = 0 mA Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL Min. Duty Cycle =100% Max. VCC, CE1 ≥ VCC – 0.3 V, or CE2 ≤ 0.3 V VIN ≥ VCC – 0.3 V or VIN ≤ 0.3 V –5 –5 ISB2 15 15 15 mA Document #: 38-05043 Rev. *E Page 3 of 15 [+] Feedback CY7C185 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0 V Max 7 7 Unit pF pF Figure 1. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 481 Ω 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R1 481 Ω 3.0 V R2 255Ω GND 10% ALL INPUT PULSES 90% 90% 10% ≤ 5 ns R2 255Ω ≤ 5 ns Equivalent to: OUTPUT (a) (b) THÉVENIN EQUIVALENT 167Ω 1.73 V Notes 2. Minimum voltage is equal to –3.0 V for pulse durations less than 30 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05043 Rev. *E Page 4 of 15 [+] Feedback CY7C185 Switching Characteristics Over the Operating Range[4] -15 Parameter Read Cycle tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE tLZCE1 tLZCE2 tHZCE tPU tPD Write Cycle[7] tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW to Write End CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z[5] WE HIGH to Low Z 3 15 12 12 12 0 0 12 8 0 7 5 20 15 15 15 0 0 15 10 0 7 5 35 20 20 25 0 0 20 12 0 8 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[5] 3 3 7 0 15 0 20 CE1 LOW to Low Z[6] CE2 HIGH to Low Z CE1 HIGH to High Z[5, 6] CE2 LOW to High Z CE1 LOW to Power-up CE2 to HIGH to Power-up CE1 HIGH to Power-down CE2 LOW to Power-down 3 7 5 3 8 0 20 3 15 15 8 3 8 5 3 10 15 15 5 20 20 9 3 10 20 20 5 35 35 15 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max Min -20 Max Min -35 Max Unit Notes 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 6. At any temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device. 7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05043 Rev. *E Page 5 of 15 [+] Feedback CY7C185 Switching Waveforms Figure 2. Read Cycle No.1[8,9] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 3. Read Cycle No.2[10,11] CE1 tRC CE2 OE OE tACE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE tHZOE tHZCE DATA VALID tPD ICC HIGH IMPEDANCE VCC SUPPLY CURRENT tPU 50% 50% ISB Notes 8. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 9. WE is HIGH for read cycle. 10. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL. 11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. Document #: 38-05043 Rev. *E Page 6 of 15 [+] Feedback CY7C185 Switching Waveforms (continued) Figure 4. Write Cycle No. 1 (WE Controlled)[9,11] tWC ADDRESS CE1 tAW CE2 CE WE tSA tSCE2 tPWE tSCEI tHA OE tSD DATA I/O NOTE 12 tHZOE DATA IN VALID tHD Figure 5. Write Cycle No. 2 (CE Controlled)[11,12,13] tWC ADDRESS CE1 tSA CE2 tAW WE tSD DATA I/O DATA IN VALID tHD tSCE2 tHA tSCE1 Notes 12. During this period, the I/Os are in the output state and input signals must not be applied. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05043 Rev. *E Page 7 of 15 [+] Feedback CY7C185 Switching Waveforms (continued) Figure 6. Write Cycle No. 3 (WE Controlled, OE LOW)[11,12,13,14] tWC ADDRESS CE1 CE2 tSCE1 tSCE2 tAW tSA WE tSD DATA I/O NOTE 12 tHZWE DATA IN VALID tLZWE tHD tHA Note 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05043 Rev. *E Page 8 of 15 [+] Feedback CY7C185 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 SB OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0 V TA =25°C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 I SB 5.5 6.0 I CC 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 NORMALIZED I,CC I NORMALIZED I, I CC I CC V CC=5.0 V V IN=5.0 V 125 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED t AA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 6.0 TA =25°C 1.6 1.4 1.2 1.0 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 VCC =5.0 V TA =25°C VCC =5.0 V 0.8 0.6 –55 25 125 AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC OUTPUT SINK CURRENT (mA) NORMALIZED I CC vs. CYCLE TIME VCC =5.0 V TA =25°C VCC =0.5 V 1.00 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC =4.5 V TA =25°C 0.75 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-05043 Rev. *E Page 9 of 15 [+] Feedback CY7C185 Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Input/Output High Z High Z Data Out Data In High Z Mode Deselect/ Power-down Deselect/ Power-down Read Write Deselect Address Designators Address Name A4 A5 A6 A7 A8 A9 A10 A11 A12 A0 A1 A2 A3 Address Function X3 X4 X5 X6 X7 Y1 Y4 Y3 Y0 Y2 X0 X1 X2 Pin Number 2 3 4 5 6 7 8 9 10 21 23 24 25 Ordering Information Speed (ns) 15 20 35 Ordering Code CY7C185-15VI CY7C185-20PXC CY7C185-35SC Package Name 51-85031 51-85014 51-85026 Package Type 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) Molded DIP (Pb-free) 28-pin (300-Mil) Molded SOIC Operating Range Industrial Commercial Commercial Ordering Code Definitions CY 7 C 1 85 - XX XX X Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: XX = V or PX or S V = 28-pin Molded SOJ PX = 28-pin Molded DIP (Pb-free) S = 28-pin Molded SOIC Speed: 15 ns or 20 ns or 35 ns 85 = 64 Kbit density with datawidth × 8 bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 38-05043 Rev. *E Page 10 of 15 [+] Feedback CY7C185 Package Diagrams Figure 7. 28-pin (300-Mil) PDIP (51-85014) 51-85014 *E Figure 8. 28-pin (300-Mil) Molded SOIC (51-85026) 51-85026 *F Document #: 38-05043 Rev. *E Page 11 of 15 [+] Feedback CY7C185 Package Diagrams (continued) Figure 9. 28-pin (300-Mil) Molded SOJ (51-85031) 51-85031 *D Document #: 38-05043 Rev. *E Page 12 of 15 [+] Feedback CY7C185 Acronyms Acronym CE CMOS I/O OE SRAM SOJ TSOP VFBGA chip enable Complementary metal oxide semiconductor Input/output output enable Static random access memory Small Outline J-Lead Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure Document #: 38-05043 Rev. *E Page 13 of 15 [+] Feedback CY7C185 Document History Page Document Title: CY7C185, 64-Kbit (8 K × 8) Static RAM Document Number: 38-05043 Revision ** *A *B ECN 107145 116470 486744 Submission Date 09/10/01 09/16/02 See ECN Orig. of Change SZV CEA NXR Description of Change Change from Spec number: 38-00037 to 38-05043 Add applications foot note to data sheet Changed Low standby power from 220mW to 85mW Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information table *C *D *E 2263686 3105329 3235800 See ECN 12/09/2010 04/20/2011 VKN/AESA Removed 25 ns speed bin Updated the Ordering Information table as per the current product offerings AJU PRAS Added Ordering Code Definitions. Updated Package Diagrams. Template changes. Added Acronyms and Units of Measure. Updated package diagram spec 51-85026 to *F. Document #: 38-05043 Rev. *E Page 14 of 15 [+] Feedback CY7C185 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. 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Document #: 38-05043 Rev. *E Revised April 20, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback