CY7C199C_06

CY7C199C 256K (32K x 8) Static RAM Features • Fast access time: 12 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL–compatible Inputs and Outputs • 2.0V Data Retention • Low CMOS standby power • Automated Power-down when deselected • Available in Pb-free and non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I packages General Description The CY7C199C is a high-performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. See the Truth Table in this data sheet for a complete description of read and write modes Logic Block Diagram Input Buffer Row Decoder RAM Array ARRAY 32K x 8 Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE A X X Product Portfolio 12 ns Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current (L) 12 85 15 ns 15 80 500 20 ns 20 75 Unit ns mA µA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05408 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C199C Pin Layout and Specifications 28 DIP (6.9 x 35.6 x 3.5 mm) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 TSOP I (8 x 13.4 mm) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A14 A13 A12 28 SOJ A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Document #: 38-05408 Rev. *C Page 2 of 13 [+] Feedback CY7C199C Pin Description Pin AX CE I/OX OE VCC VSS WE Type Input Control Input or Output Control Supply Supply Control Description Address Inputs Chip Enable Data Input/Outputs Output Enable Power (5.0V) Ground Write Enable DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 20 11, 12, 13, 15, 16, 17, 18, 19 22 28 14 27 TSOP I 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 27 18, 19, 20, 22, 23, 24, 25, 26 1 7 21 6 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (i.e., case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-up Current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Industrial Ambient Temperature (TA) 0°C to 70°C –40°C to 85°C Voltage Range (VCC) 5.0V ± 10% 5.0V ± 10% DC Electrical Characteristics Over the Operating Range [2] 12 ns Parameter VIH VIL VOH VOL IIX IOZ ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input Leakage Current Output Leakage Current VCC Operating Supply Current GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC L 10 L –5 –5 Condition Min. 2.2 –0.5 2.4 0.4 +5 +5 85 30 –5 –5 Max. VCC + 0.3 0.8 Min. 2.2 –0.5 2.4 0.4 +5 +5 80 30 10 10 500 10 –5 –5 15 ns Max. VCC + 0.3 0.8 Min. 2.2 –0.5 2.4 0.4 +5 +5 75 30 20 ns Max. VCC + 0.3 0.8 Unit V V V V µA µA mA mA mA mA µA Automatic CE Max. VCC, CE ≥ VIH, VIN ≥ Power-down Current VIH or VIN ≤ VIL, f = FMAX TTL Inputs Automatic CE Max. VCC, CE ≥ VCC – 0.3V, Power-down Current VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 CMOS Inputs ISB2 Note: 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. Document #: 38-05408 Rev. *C Page 3 of 13 [+] [+] Feedback CY7C199C Capacitance[3] Max. Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V ALL – PACKAGES 8 8 Unit pF Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board TSOP I 88.6 21.94 SOJ 79 41.42 DIP 69.33 31.62 Unit °C/W AC Test Loads and Waveforms VCC C1 INCLUDING JIG AND SCOPE R1 VCC R2 C2 INCLUDING JIGAND SCOPE R1 3.0V R2 GND 10% ALL INPUT PULSES 90% 90% 10% ≤ 1V/ns ≤ 1V/ns (a) (b) Equivalent to: OUTPUT THÉVENIN EQUIVALENT Rth VT output load output load for tHZOE, tHZCE, tHZWE Notes: 3. Tested initially and after any design or process change that may affect these parameters. 4. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Document #: 38-05408 Rev. *C Page 4 of 13 [+] [+] Feedback CY7C199C AC Test Conditions Parameter C1 C2 R1 R2 RTH VTH Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor Thevenin Voltage Thevenin Description Nom. 30 5 480 255 167 1.73 Unit pF Ω V AC Electrical Characteristics[5, 6, 7] 12 ns Parameter tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Addres Change CE to Data Valid OE to Data Valid OE to Low Z OE to High Z CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 3 12 9 9 0 0 8 8 0 7 3 0 12 15 10 10 0 0 9 9 0 7 3 3 5 0 15 20 15 15 0 0 15 10 0 10 0 5 3 7 0 20 3 12 5 0 7 3 9 Min 12 12 3 15 7 0 9 Max Min 15 15 3 20 9 15 ns Max Min 20 20 20 ns Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage. Document #: 38-05408 Rev. *C Page 5 of 13 [+] [+] Feedback CY7C199C Data Retention Characteristics[8] ALL Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR=2.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Condition Min. 2.0 – 0 200 Max. – 150 – – Unit V µA ns µs Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR CE tR Read Cycle No. 1[11, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes: 8. L-version only. 9. Device is continuously selected. OE = VIL = CE. 10. WE is HIGH for Read Cycle. Document #: 38-05408 Rev. *C Page 6 of 13 [+] [+] Feedback CY7C199C Timing Waveforms (continued) Read Cycle No. 2[11, 12] tRC Address CE tACE OE tDOE tLZOE High Z Data Out ICC ISB tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE VCC Current Write Cycle No. 1 (WE Controlled)[13, 14, 15] tWC Address tSCE CE tAW tSA WE tPWE tHA OE tHZOE tSD tHD Data In/Out Undefined see footnotes Data-In Valid Notes: 11. This cycle is OE Controlled and WE is HIGH read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. This cycle is WE controlled, OE is HIGH during write. 14. Data In/Out is high impedance if OE = VIH. 15. During this period the I/Os are in output state and input signals should not be applied. Document #: 38-05408 Rev. *C Page 7 of 13 [+] [+] Feedback CY7C199C Timing Waveforms (continued) Write Cycle No. 2 (CE Controlled)[14, 16, 17] tWC Address tSCE CE tSA tAW tHA WE tSD Data In/Out High Z Data-In Valid tHD High Z Write Cycle No. 3 (WE Controlled, OE Low)[18] t WC Address tSCE CE tAW tSA WE tSD Data In/Out Undefined see footnotes tHA tPWE tHD Undefined See Footnotes Data-In Valid tHZWE tLZWE Notes: 16. This cycle is CE controlled. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 38-05408 Rev. *C Page 8 of 13 [+] [+] Feedback CY7C199C Truth Table CE H L L L WE X H L H OE X L X H High Z Data Out Data In High Z Input/Output Read Write Deselect Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed 12 Ordering Code CY7C199C–12VC CY7C199C–12VXC CY7C199C–12ZXC CY7C199C–12VI 15 CY7C199C–15PC CY7C199C–15PXC CY7C199C–15ZC CY7C199C–15ZXC CY7C199C–15VC CY7C199C–15VXC CY7C199CL–15VC CY7C199CL–15VXC CY7C199C–15VI 20 CY7C199C–20ZXI 51-85031 51-85071 51-85031 51-85071 51-85071 51-85031 51-85014 Package Name 51-85031 Package Type 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) Molded SOJ (Pb-Free) 28-pin TSOP I (Pb-Free) 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) DIP 28-pin (300-Mil) DIP (Pb-Free) 28-pin TSOP I 28-pin TSOP I (Pb-Free) 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) Molded SOJ (Pb-Free) 28-pin (300-Mil) Molded SOJ 28-pin (300-Mil) Molded SOJ (Pb-Free) 28-pin (300-Mil) Molded SOJ 28-pin TSOP I (Pb-Free) Industrial Industrial Industrial Commercial Operating Range Commercial Document #: 38-05408 Rev. *C Page 9 of 13 [+] [+] Feedback CY7C199C Package Diagrams 28-pin TSOP 1 (8 x 13.4 mm) (51-85071) 51-85071-*G Document #: 38-05408 Rev. *C Page 10 of 13 [+] [+] Feedback CY7C199C Package Diagrams (continued) 28-pin (300-Mil) Molded SOJ (51-85031) NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 38-05408 Rev. *C Page 11 of 13 [+] [+] Feedback CY7C199C Package Diagrams (continued) 28-pin (300-Mil) PDIP (51-85014) SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. 0.260[6.60] 0.295[7.49] REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 3° MIN. 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05408 Rev. *C Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C199C Document History Page Document Title: CY7C199C 256K (32K x 8) Static RAM Document Number: 38-05408 REV. ** *A ECN No. 129233 129697 Issue Date 09/11/03 09/15/03 Orig. of Change HGK KKV New Data Sheet Minor change: Move Product Portfolio from page 4 to page 1 Move Truth table from page 9 to page 3 Added Lead-Free part to Ordering info on Page #10 Removed 25 ns speed bin Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table Description of Change *B *C 341574 492500 See ECN See ECN PCI NXR Document #: 38-05408 Rev. *C Page 13 of 13 [+] [+] Feedback