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CY8C24223A-12PVXET

CY8C24223A-12PVXET

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    SSOP20

  • 描述:

    IC MCU 8BIT 4KB FLASH 20SSOP

  • 数据手册
  • 价格&库存
CY8C24223A-12PVXET 数据手册
CY8C24223A, CY8C24423A Automotive - Extended Temperature PSoC® Programmable System-on-Chip Features ■ AEC qualified ■ Powerful Harvard architecture processor ❐ M8C processor speeds up to 12 MHz ❐ 8x8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ 4.75V to 5.25V operating voltage ❐ Automotive temperature range: -40°C to +125°C ■ ■ ■ ■ ■ Additional system resources 2 ❐ I C™ slave, master, or multi-master operation up to 400 kHz ❐ Watchdog and Sleep timers ❐ User-configurable Low Voltage Detection (LVD) ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ■ Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full Featured, In-Circuit Emulator (ICE) and Programmer ❐ Full speed emulation ❐ Complex breakpoint structure ❐ 128K bytes trace memory Advanced peripherals (PSoC® blocks) ❐ Six rail-to-rail analog PSoC blocks provide: • Up to 14-Bit Analog-to-Digital Converters (ADCs) • Up to 9-Bit Digital-to-Analog Converters (DACs) • Programmable Gain Amplifiers (PGAs) • Programmable filters and comparators ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers and counters, 8- and 16-bit pulse-width modulators (PWMs) • CRC and PRS modules • Full- or Half-Duplex UART • SPI master or slave • Connectable to all General Purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks Logic Block Diagram Port 2 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Precision, programmable clocking ❐ Internal ±4% 24 MHz oscillator ❐ High accuracy 24 MHz with optional 32 kHz crystal and Phase Locked Loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low power oscillator for Watchdog and Sleep functionality SROM Global Analog Interconnect Flash 4K CPU Core (M8C) Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Flexible on-chip memory ❐ 4K bytes Flash program storage, 100 erase/write cycles ❐ 256 bytes SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash updates ❐ Flexible protection modes ❐ EEPROM emulation in Flash Programmable pin configurations ❐ 25 mA Sink, 10 mA Drive on all GPIO ❐ Pull up, pull down, High Z, strong, or open drain drive modes on all GPIO [1] ❐ Up to 12 analog inputs on GPIO ❐ Two 30 mA analog outputs on GPIO ❐ Configurable interrupt on all GPIO Port 1 Digital Clocks ANALOG SYSTEM Digital Block Array Analog Block Array (1 Row, 4 Blocks) (2 Columns, 6 Blocks) Multiply Accum. Decimator I2C Analog Ref Analog Input Muxing POR and LVD System Resets Internal Voltage Ref. SYSTEM RESOURCES Note 1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the PSoC Technical Reference Manual for more details Cypress Semiconductor Corporation Document Number: 38-12029 Rev. *L • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 11, 2014 CY8C24223A, CY8C24423A Contents PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ............................................................. 3 Analog System ............................................................ 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Document Conventions ................................................... 8 Acronyms Used ........................................................... 8 Units of Measure ......................................................... 8 Numeric Naming .......................................................... 8 Pinouts .............................................................................. 9 20-Pin Part Pinout ...................................................... 9 28-Pin Part Pinout .................................................... 10 Document Number: 38-12029 Rev. *L Registers ......................................................................... 11 Register Conventions ................................................ 11 Register Mapping Tables .......................................... 11 Electrical Specifications ................................................ 14 Absolute Maximum Ratings ....................................... 15 Operating Temperature ............................................ 15 DC Electrical Characteristics ..................................... 16 AC Electrical Characteristics ..................................... 21 Packaging Information ................................................... 28 Thermal Impedances ................................................ 29 Capacitance on Crystal Pins .................................... 29 Solder Reflow Specifications ..................................... 29 Development Tool Selection ......................................... 30 Software .................................................................... 30 Development Kits ...................................................... 30 Evaluation Tools ........................................................ 30 Device Programmers ................................................. 31 Accessories (Emulation and Programming) .............. 31 Ordering Information ...................................................... 32 Ordering Code Definitions ........................................ 32 Document History Page ................................................. 33 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC® Solutions ...................................................... 34 Cypress Developer Community ................................. 34 Technical Support ..................................................... 34 Page 2 of 34 CY8C24223A, CY8C24423A The PSoC family consists of many programmable system-on-chips with on-chip Controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user modules. Figure 1. Digital System Block Diagram Port 1 Port 2 Port 0 To System Bus Digital Clocks From Core The PSoC architecture, as shown in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allow all the device resources to be combined into a complete custom system. Each CY8C24x23A PSoC device includes four digital blocks and six analog blocks. Depending on the PSoC package, up to 24 GPIO are also included. The GPIO provide access to the global digital and analog interconnects. To Analog System DIGITAL SYSTEM Digital PSoC Block Array 8 Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 Row Output Configuration 8 Row Input Configuration PSoC Functional Overview 8 PSoC Core GIE[7:0] The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 12 MHz, providing a two MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with multiple vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep Timer and Watchdog Timer (WDT). Memory includes 4 KB of Flash for program storage and 256 bytes of SRAM for data storage. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to ±4% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the Sleep Timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt. Document Number: 38-12029 Rev. *L GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include: ■ PWMs (8- and 16-bit) ■ PWMs with Dead Band (8- and 16-bit) ■ Counters (8 to 32 bit) ■ Timers (8 to 32 bit) ■ Full or Half-Duplex 8-bit UART with selectable parity ■ SPI master and slave ■ I2C master, slave, or multi-master ■ Cyclical Redundancy Checker/Generator (16 bit) ■ IrDA ■ Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Page 3 of 34 CY8C24223A, CY8C24423A Analog System The Analog System is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: Figure 2. Analog System Block Diagram P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] ADCs (up to two, with 6 to 14-bit resolution, selectable as Incremental, Delta-Sigma, and SAR) ■ Filters (two and four pole band-pass, low-pass, and notch) ■ Amplifiers (up to two, with selectable gain up to 48x) ■ Instrumentation amplifiers (one with selectable gain up to 93x) P2[3] P2[2] ■ Comparators (up to two, with 16 selectable thresholds) P2[1] P2[0] ■ DACs (up to two, with 6 to 9-bit resolution) ■ Multiplying DACs (up to two, with 6 to 9-bit resolution) ■ High current output drivers (two with 30 mA drive) ■ 1.3V reference (as a System Resource) ■ DTMF Dialer ■ Modulators ■ Correlators ■ Peak Detectors ■ Many other topologies possible AGNDIn RefIn ■ P2[6] P2[4] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array Analog blocks are arranged in a column of three, which includes one Continuous Time (CT) and two Switched Capacitor (SC) blocks, as shown in Figure 2. ACB00 ACB01 ASC10 ASD11 ASD20 ASC22 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn BandGap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-12029 Rev. *L Page 4 of 34 CY8C24223A, CY8C24423A Additional System Resources PSoC Device Characteristics System Resources, some of which have been previously listed, provide additional capability useful for complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow: Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in Table 1. ■ ■ ■ The I2C module provides 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. LVD interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V voltage reference provides an absolute reference for the analog system, including ADCs and DACs. Analog Columns Analog Blocks up to 64 4 16 12 4 4 12 2K 32K CY8C27x43 up to 44 2 8 12 4 4 12 256 Bytes 16K CY8C24x94 64 Flash Size Analog Outputs CY8C29x66[2] PSoC Part Number SRAM Size Analog Inputs The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. Digital Blocks ■ A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. Table 1. PSoC Device Characteristics Digital Rows ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Digital I/O ■ 1 4 48 2 2 6 1K 16K CY8C24x23A[2] up to 24 1 4 12 2 2 6 256 Bytes 4K CY8C23x33 up to 1 4 12 2 2 4 256 Bytes 8K CY8C21x34[2] up to 28 1 4 28 0 2 4[3] 512 Bytes 8K CY8C21x23 16 1 4 8 0 2 4[3] 256 Bytes 4K CY8C20x34 up to 28 0 0 28 0 0 3[3, 4] 512 Bytes 8K Getting Started For in-depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. CYPros Consultants For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Application Notes Solutions Library Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Notes 2. Automotive qualified devices available in this group. 3. Limited analog functionality. 4. Two analog blocks and one CapSense™ block. Document Number: 38-12029 Rev. *L Page 5 of 34 CY8C24223A, CY8C24423A Development Tools Code Generation Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. ■ Integrated source-code editor (C and assembly) Debugger ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Document Number: 38-12029 Rev. *L Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 6 of 34 CY8C24223A, CY8C24423A Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure User Modules. 3. Organize and Connect. 4. Generate, Verify, and Debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user Document Number: 38-12029 Rev. *L module parameter, and other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. These include monitoring address and data bus values, memory locations, and external signals. Page 7 of 34 CY8C24223A, CY8C24423A Document Conventions Units of Measure Acronyms Used A units of measure table is located in the Electrical Specifications section. Table 8 on page 14 lists all the abbreviations used to measure the PSoC devices. The following table lists the acronyms that are used in this document. Table 2. Acronyms Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal. EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose I/O GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator I/O input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip PWM pulse width modulator SC switched capacitor SRAM static random access memory Document Number: 38-12029 Rev. *L Page 8 of 34 CY8C24223A, CY8C24423A Pinouts The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O. 20-Pin Part Pinout Table 3. 20-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type Pin Description Digital Analog Name I/O I P0[7] Analog column mux input I/O I/O P0[5] Analog column mux input and column output I/O I/O P0[3] Analog column mux input and column output I/O I P0[1] Analog column mux input Power Vss Ground connection I/O P1[7] I2C Serial Clock (SCL) I/O P1[5] I2C Serial Data (SDA) I/O P1[3] I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[5] Power Vss Ground connection I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[5] I/O P1[2] I/O P1[4] Optional External Clock Input (EXTCLK) I/O P1[6] Input XRES Active high external reset with internal pull down I/O I P0[0] Analog column mux input I/O I P0[2] Analog column mux input I/O I P0[4] Analog column mux input I/O I P0[6] Analog column mux input Power Vdd Supply voltage Figure 3. CY8C24223A 20-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] Vss I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Note 5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details. Document Number: 38-12029 Rev. *L Page 9 of 34 CY8C24223A, CY8C24423A 28-Pin Part Pinout Table 4. 28-Pin Part Pinout (SSOP) Type Pin Pin Description No. Digital Analog Name 1 I/O I P0[7] Analog column mux input 2 I/O I/O P0[5] Analog column mux input and column output 3 I/O I/O P0[3] Analog column mux input and column output 4 I/O I P0[1] Analog column mux input 5 I/O P2[7] 6 I/O P2[5] 7 I/O I P2[3] Direct switched capacitor block input 8 I/O I P2[1] Direct switched capacitor block input 9 Power Vss Ground connection 10 I/O P1[7] I2C Serial Clock (SCL) 11 I/O P1[5] I2C Serial Data (SDA) 12 I/O P1[3] 13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[5] 14 Power Vss Ground connection 15 I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[5] 16 I/O P1[2] 17 I/O P1[4] Optional External Clock Input (EXTCLK) 18 I/O P1[6] 19 Input XRES Active high external reset with internal pull down 20 I/O I P2[0] Direct switched capacitor block input 21 I/O I P2[2] Direct switched capacitor block input 22 I/O P2[4] External Analog Ground (AGND) 23 I/O P2[6] External Voltage Reference (VRef) 24 I/O I P0[0] Analog column mux input 25 I/O I P0[2] Analog column mux input 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power Vdd Supply voltage Figure 4. CY8C24423A 28-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] Vss I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12029 Rev. *L Page 10 of 34 CY8C24223A, CY8C24423A Registers Register Conventions Register Mapping Tables This section lists the registers of the automotive CY8C24x23A PSoC device. For detailed register information, refer to the PSoC Technical Reference Manual. The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set the user is in Bank 1. The register conventions specific to this section are listed in the following table. Table 5. Abbreviations Convention R Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Description Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 38-12029 Rev. *L Page 11 of 34 CY8C24223A, CY8C24423A Table 6. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 Addr (0,Hex) Access Name Addr (0,Hex) 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W ASY_CR 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # 6C DCB03DR1 2D W 6D DCB03DR2 2E RW 6E DCB03CR0 2F # 6F 30 ACB00CR3 70 31 ACB00CR0 71 32 ACB00CR1 72 33 ACB00CR2 73 34 ACB01CR3 74 35 ACB01CR0 75 36 ACB01CR1 76 37 ACB01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and must not be accessed. Document Number: 38-12029 Rev. *L Access RW RW # # RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW # RW # RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # Page 12 of 34 CY8C24223A, CY8C24423A Table 7. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 Addr (1,Hex) Access Name Addr (1,Hex) 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 DBB00IN 21 RW CLK_CR1 61 DBB00OU 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW 6C DCB03IN 2D RW 6D DCB03OU 2E RW 6E 2F 6F 30 ACB00CR3 70 31 ACB00CR0 71 32 ACB00CR1 72 33 ACB00CR2 73 34 ACB01CR3 74 35 ACB01CR0 75 36 ACB01CR1 76 37 ACB01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and must not be accessed. Document Number: 38-12029 Rev. *L Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW R W W RW W RL # # Page 13 of 34 CY8C24223A, CY8C24423A Electrical Specifications This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC device. For the latest electrical specifications, visit http://www.cypress.com. Specifications are valid for -40C  TA  125C and TJ  135C, except where noted. Figure 5. Voltage versus CPU Frequency 5.25 l i d i ng Va rat n pe i o O eg R 4.75 Vdd Voltage (V) 0 12 MHz 93 kHz 24 MHz CPU Frequency (nominal setting) The following table lists the units of measure that are used in this section. Table 8. Units of Measure Symbol C dB fF Hz KB Kbit kHz k Mbaud Mbps MHz M A F H s V Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megabaud megabits per second megahertz megaohm microampere microfarad microhenry microsecond microvolts Document Number: 38-12029 Rev. *L Symbol Vrms W mA ms mV nA ns nV  pA pF pp ppm ps sps  V Unit of Measure microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Page 14 of 34 CY8C24223A, CY8C24423A Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature TBAKETEMP Bake Temperature TBAKETIME Bake Time TA Vdd VIO VIOZ IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch up Current Min -55 Typ +25 Max +125 Units Notes C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Storage temperatures above 65C degrades reliability. Maximum combined storage and operational time at +125°C is 7000 hours. C – 125 See package label -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 – – See package label 72 Hours – – – – – – – +125 +6.0 Vdd + 0.5 Vdd + 0.5 +25 – 200 C V V V mA V mA Min -40 -40 Typ – – Max +125 +135 Human Body Model ESD. Operating Temperature Table 10. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Document Number: 38-12029 Rev. *L Units Notes C C The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 29. The user must limit the power consumption to comply with this requirement. Page 15 of 34 CY8C24223A, CY8C24423A DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 11. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 4.75 – 5.25 V See table titled DC POR and LVD Specifications on page 20 IDD Supply Current – 5 8 mA Conditions are Vdd = 5.25V, -40C  TA  125C, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, Analog power = off. ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[6] – 4 13 A Conditions are with internal low speed oscillator active, Vdd = 5.25V, -40C  TA  55C. Analog power = off. ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[6] – 4 100 A Conditions are with internal slow speed oscillator active, Vdd = 5.25V, 55C < TA  125C. Analog power = off. ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[6] – 6 15 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 5.25V, -40C  TA  55C. Analog power = off. ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[6] – 6 100 A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 5.25V, 55C < TA  125C. Analog power = off. VREF Reference Voltage (Bandgap) 1.25 1.3 1.35 V Trimmed for appropriate Vdd. DC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance. Table 12. DC GPIO Specifications Symbol Description Min Typ Max Units 4 5.6 8 k Pull down Resistor 4 5.6 8 k High Output Level 3.5 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. IOH High Level Source Current 10 – – mA VOH  Vdd-1.0V, see the limitations of the total current in the note for VOH. IOL Low Level Sink Current 25 – – mA VOL  0.75V, see the limitations of the total current in the note for VOL. VIL Input Low Level – – 0.8 V RPU Pull up Resistor RPD VOH Notes Note 6. Standby current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 38-12029 Rev. *L Page 16 of 34 CY8C24223A, CY8C24423A Table 12. DC GPIO Specifications (continued) Symbol Description Min Typ Max Units – mV Notes VIH Input High Level 2.1 – VH Input Hysterisis – 60 IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 A CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25C COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp = 25C V DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor (SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time (CT) PSoC blocks. Table 13. DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power Input Offset Voltage (absolute value) High Power TCVOSOA Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) GOLOA Open Loop Gain Power = Low Power = Medium Power = High Min – – – – – – Typ 1.6 1.3 1.2 7.0 200 4.5 0.0 0.5 – – – – – 80 80 80 VOHIGHOA High Output Voltage Swing (worst case internal load) Vdd - 0.2 Power = Low Vdd - 0.2 Power = Medium Vdd - 0.5 Power = High VOLOWOA Low Output Voltage Swing (worst case internal load) Power = Low – Power = Medium – Power = High – ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low – Power = Low, Opamp Bias = High – Power = Medium, Opamp Bias = Low – Power = Medium, Opamp Bias = High – Power = High, Opamp Bias = Low – Power = High, Opamp Bias = High – PSRROA Supply Voltage Rejection Ratio – Document Number: 38-12029 Rev. *L Max 11 9 9 35.0 – 9.5 Units Notes mV mV mV V/C pA Gross tested to 1 A pF Package and pin dependent. Temp = 25C. Vdd V The common-mode input Vdd - 0.5 – voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable – dB at high power. For all other – dB bias modes (except high – dB power, high opamp bias), minimum is 60 dB. – – – – – – V V V – – – 0.2 0.2 0.5 V V V 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN  Vdd Page 17 of 34 CY8C24223A, CY8C24423A DC Low Power Comparator Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 14. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max Vdd - 1 40 30 Units V A mV Notes DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 15. DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance High Output Voltage Swing (Load = 32 to Vdd/2) VOLOWOB Low Output Voltage Swing (Load = 32 to Vdd/2) ISOB PSRROB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Document Number: 38-12029 Rev. *L Min – – 0.5 – 0.5 x Vdd + 1.1 – Typ 3 +6 – 1 – Max Units 18 mV – V/°C Vdd - 1.0 V –  – V – 0.5 x Vdd - 1.3 V – – – 1.1 2.6 64 5.1 8.8 – mA mA dB Notes Page 18 of 34 CY8C24223A, CY8C24423A DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 16. DC Analog Reference Specifications Symbol BG – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference AGND = Vdd/2[7] AGND = 2 x BandGap[7] AGND = P2[4] (P2[4] = Vdd/2)[7] AGND = BandGap[7] AGND = 1.6 x BandGap[7] AGND Column to Column Variation (AGND = Vdd/2)[7] RefHi = Vdd/2 + BandGap[8] RefHi = 3 x BandGap[8] RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)[8] RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[8] RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)[8] RefHi = 3.2 x BandGap[8] RefLo = Vdd/2 – BandGap[8] RefLo = BandGap[8] RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)[8] RefLo = P2[4] – BandGap (P2[4] = Vdd/2)[8] RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)[8] Min 1.25 Vdd/2 - 0.02 2.4 P2[4] - 0.02 1.23 1.98 -0.035 Typ 1.30 Vdd/2 2.6 P2[4] 1.30 2.08 0.000 Max 1.35 Vdd/2 + 0.02 2.8 P2[4] + 0.02 1.37 2.14 0.035 Units V V V V V V V Vdd/2 + 1.15 Vdd/2 +1.30 Vdd/2 +1.45 3.65 P2[6] + 2.4 P2[4] + 1.24 P2[4] + P2[6] - 0.1 3.9 P2[6] + 2.6 P2[4] +1.30 P2[4] + P2[6] 4.15 P2[6] + 2.8 P2[4] + 1.36 P2[4] + P2[6] + 0.1 V V V V V 4.42 1.15 1.45 2.8 - P2[6] P2[4] - 1.15 P2[4] - P2[6] + 0.1 V V V V V V 3.9 4.16 Vdd/2 - 1.45 Vdd/2 - 1.3 1.15 2.4 - P2[6] P2[4] - 1.45 P2[4] - P2[6] - 0.1 1.3 2.6 - P2[6] 1.3 P2[4] - P2[6] Notes 7. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V. 8. This specification is only valid when Ref Control Power = High. Document Number: 38-12029 Rev. *L Page 19 of 34 CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 17. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units RCT Resistor Unit Value (Continuous Time) – 12.24 – k CSC Capacitor Unit Value (Switch Cap) – 80 – fF Notes DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual for more information on the VLT_CR register. Table 18. DC POR and LVD Specifications Symbol Description VPPOR2 Vdd Value for PPOR Trip PORLEV[1:0] = 10b VLVD6 VLVD7 Vdd Value for LVD Trip VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units – 4.55 4.70 V 4.62 4.710 4.73 4.814 4.83 4.950 V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from watchdog. DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 19. DC Programming Specifications Symbol Description VddIWRITE Supply Voltage for Flash Write Operations Min Typ Max Units 4.75 – – V Notes IDDP Supply Current During Programming or Verify – 10 25 mA VILP Input Low Voltage During Programming or Verify – – 0.8 V VIHP Input High Voltage During Programming or Verify 2.1 – – V IILP Input Current when Applying VILP to P1[0] or P1[1] During Programming or Verify – – 0.2 mA Driving internal pull down resistor. IIHP Input Current when Applying VIHP to P1[0] or P1[1] During Programming or Verify – – 1.5 mA Driving internal pull down resistor. VOLV Output Low Voltage During Programming or Verify – – 0.75 V VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block)[9] FlashENT FlashDR Flash Endurance (total)[9, 10] Flash Data Retention[11] 3.5 – Vdd V 100 – – – Erase/write cycles per block. 6,400 – – – Erase/write cycles. 15 – – Years Notes 9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. 10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. 11. Flash data retention based on the use condition of  7000 hours at TA  125°C and the remaining time at TA  65°C. Document Number: 38-12029 Rev. *L Page 20 of 34 CY8C24223A, CY8C24423A AC Electrical Characteristics AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 20. AC Chip-Level Specifications Symbol FIMO24 FCPU1 F24M F32K1 F32KU Description Internal Main Oscillator Frequency for 24 MHz CPU Frequency (5V Vdd Nominal) Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency Internal Low Speed Oscillator (ILO) Untrimmed Frequency Min 23.04[12] Typ 24 Max 24.96[12] Units MHz 0.09[12] 0 15 12 24 32 12.48[12] 24.96[12, 13] 64 MHz MHz kHz 5 – – kHz F32K2 External Crystal Oscillator – 32.768 – kHz FPLL PLL Frequency – 23.986 – MHz Jitter24M2 TPLLSLEW TPLLSLEWSLOW TOS 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle Internal Low Speed Oscillator (ILO) Duty Cycle 24 MHz Trim Step Size 24 MHz Period Jitter (IMO) Peak-to-Peak 24 MHz Period Jitter (IMO) Root Mean Squared Maximum frequency of signal on row input or row output. Power Supply Slew Rate Time between end of POR state and CPU code execution – 0.5 0.5 – – – – 1700 800 10 50 2620 ps ms ms ms – 2800 3800 ms – 10 40 20 100 – 50 50 – – 60 80 ns s % % – – 50 600 – – kHz ps – – 600 ps – – 12.48[12] MHz – – – 16 250 100 V/ms ms TOSACC Jitter32k TXRST DC24M DCILO Step24M Jitter24M1P Jitter24M1R FMAX SRPOWERUP TPOWERUP Notes Trimmed using factory trim values. This specification applies when the ILO has been trimmed. After a reset and before the M8C processor starts to execute, the ILO is not trimmed. Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. Refer to Figure 9 on page 22. Refer to Figure 6 on page 22. Refer to Figure 7 on page 22. Refer to Figure 8 on page 22. Refer to Figure 10 on page 22. Refer to Figure 9 on page 22. Vdd slew rate during power up. Power up from 0V. Notes 12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 13. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 38-12029 Rev. *L Page 21 of 34 CY8C24223A, CY8C24423A Figure 6. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 7. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 8. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz TOS F32K2 Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1P Jitter24M2 F 24M Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 Document Number: 38-12029 Rev. *L Page 22 of 34 CY8C24223A, CY8C24423A AC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 21. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 2 2 9 9 Typ – – – 27 22 Max 12.48[12] 22 22 – – Units MHz ns ns ns ns Notes Normal Strong Mode 10% - 90% 10% - 90% 10% - 90% 10% - 90% Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 22. AC Operational Amplifier Specifications Symbol SRROA SRFOA BWOA Description Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Document Number: 38-12029 Rev. *L Min Typ Max Units 0.15 0.15 0.15 1.7 1.7 6.5 – – – – – – – – – – – – V/s V/s V/s V/s V/s V/s 0.01 0.01 0.01 0.5 0.5 4.0 – – – – – – – – – – – – V/s V/s V/s V/s V/s V/s 0.75 0.75 0.75 3.1 3.1 5.4 – – – – – – – – – – – – MHz MHz MHz MHz MHz MHz Page 23 of 34 CY8C24223A, CY8C24423A AC Low Power Comparator Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 23. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – Typ – Max 50 Units s Notes  50 mV overdrive comparator reference set within VREFLPC. When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 12. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 13. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 Document Number: 38-12029 Rev. *L 0.01 0.1 Freq (kHz) 1 10 100 Page 24 of 34 CY8C24223A, CY8C24423A AC Digital Block Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 24. AC Digital Block Specifications Function Description Min Typ Max Units – – 24.96[12] MHz 50[14] – – ns Maximum Frequency, No Capture – – 24.96[12] MHz Maximum Frequency, With Capture – – 24.96[12] MHz Enable Pulse Width [14] – – ns All Functions Maximum Block Clocking Frequency Timer Capture Pulse Width Counter Dead Band 50 [12] MHz Maximum Frequency, No Enable Input – – 24.96 Maximum Frequency, Enable Input – – 24.96[12] MHz Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 50[14] – – ns Disable Mode 50[14] – – ns MHz Notes Kill Pulse Width: Maximum Frequency – – 24.96[12] CRCPRS (PRS Mode) Maximum Input Clock Frequency – – 24.96[12] MHz CRCPRS (CRC Mode) Maximum Input Clock Frequency – – 24.96[12] MHz SPIM Maximum Input Clock Frequency – – 4.16[12] MHz SPIS Maximum Input Clock Frequency – – 2.08[12] MHz Width of SS_ Negated Between Transmissions 50[14] – – ns Transmitter Maximum Input Clock Frequency – – 8.32[12] MHz Maximum baud rate is 1.04 Mbaud due to 8 x over clocking. Receiver Maximum Input Clock Frequency – – 24.96[12] MHz Maximum baud rate is 3.12 Mbaud due to 8 x over clocking. Maximum data rate is 2.08 Mbps due to 2 x over clocking. Note 14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12029 Rev. *L Page 25 of 34 CY8C24223A, CY8C24423A AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 25. AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units – – – – 3 3 s s – – – – 3 3 s s 0.6 0.6 – – – – V/s V/s 0.6 0.6 – – – – V/s V/s 0.8 0.8 – – – – MHz MHz 300 300 – – – – kHz kHz AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 26. AC External Clock Specifications Min Typ Max Units FOSCEXT Frequency Symbol Description 0.093 – 24.24 MHz – High Period 20.6 – – ns – Low Period 20.6 – – ns – Power Up IMO to Switch 150 – – s Notes AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 27. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TPRGH TPRGC Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Total Flash Block Program Time (TERASEB + TWRITE), Hot Total Flash Block Program Time (TERASEB + TWRITE), Cold Document Number: 38-12029 Rev. *L Min 1 1 40 40 0 – – – – Typ – – – – – 20 80 – – Max 20 20 – – 8 80[9] 320[9] 50 200[9] Units ns ns ns ns MHz ms ms ns ms Notes TJ  0°C – – 400[9] ms TJ  0°C Page 26 of 34 CY8C24223A, CY8C24423A AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  125°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 28. AC Characteristics of the I2C SDA and SCL Pins Symbol Description FSCLI2C THDSTAI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard Mode Min Max 0 100[15] 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – Fast Mode Min Max 0 400[15] 0.6 – – – – – – – – – 1.3 0.6 0.6 0 100[16] 0.6 1.3 0 – – – – – – – 50 Units kHz s s s s s ns s s ns Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Notes 15. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 38-12029 Rev. *L Page 27 of 34 CY8C24223A, CY8C24423A Packaging Information This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 15. 20-Pin (210-Mil) SSOP 51-85077 *E Document Number: 38-12029 Rev. *L Page 28 of 34 CY8C24223A, CY8C24423A Figure 16. 28-Pin (210-Mil) SSOP 51-85079 *E Thermal Impedances Capacitance on Crystal Pins Typical JA [17] Package Package Package Capacitance 20 SSOP 117 C/W 20 SSOP 2.6 pF 28 SSOP 101 C/W 28 SSOP 2.8 pF Solder Reflow Specifications The following table shows the solder reflow temperature limits that must not be exceeded. Package Maximum Time above TC – 5 °C Maximum Peak Temperature 20 SSOP 30 seconds 260C 28 SSOP 30 seconds 260C Note 17. TJ = TA + POWER x JA Document Number: 38-12029 Rev. *L Page 29 of 34 CY8C24223A, CY8C24423A Development Tool Selection This section presents the development tools available for the CY8C24x23A family. Software Evaluation Tools PSoC Designer All evaluation tools can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for years. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Designer comes with a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. Development Kits All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes: ■ ICE-Cube Unit ■ 28-Pin PDIP Emulation Pod for CY8C29466-24PXI ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two) ■ PSoC Designer Software CD ■ ISSP Cable ■ MiniEval Socket Programming and Evaluation board ■ Backward Compatibility Cable (for connecting to legacy Pods) ■ Universal 110/220 Power Supply (12V) ■ European Plug Adapter ■ USB 2.0 Cable ■ Getting Started Guide ■ Development Kit Registration form Document Number: 38-12029 Rev. *L CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ Evaluation Board with LCD Module ■ MiniProg Programming Unit ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable CY3210-24X23 Evaluation Pod (EvalPod) PSoC EvalPods are pods that connect to the ICE In-Circuit Emulator (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-24X23 provides evaluation of the CY8C24x23A PSoC device family. Page 30 of 34 CY8C24223A, CY8C24423A Device Programmers CY3207ISSP In-System Serial Programmer (ISSP) All device programmers can be purchased from the Cypress Online Store. The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ MiniEval Socket Programming and Evaluation Board ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes: ■ CY3207 Programmer Unit ■ PSoC ISSP Software CD ■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ USB 2.0 Cable Accessories (Emulation and Programming) Table 29. Emulation and Programming Accessories Part Number Pin Package Pod Kit[18] Foot Kit[19] CY8C24223A-12PVXE 20 SSOP CY3250-24X23A CY3250-20SSOP-FK CY8C24423A-12PVXE 28 SSOP CY3250-24X23A CY3250-28SSOP-FK Adapter[20] Adapters can be found at http://www.emulation.com. Notes 18. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 19. Foot kit includes surface mount feet that can be soldered to the target PCB. 20. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 38-12029 Rev. *L Page 31 of 34 CY8C24223A, CY8C24423A Ordering Information Flash (Bytes) RAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin CY8C24223A-12PVXE CY8C24223A-12PVXET 4K 4K 256 256 No No -40°C to +125°C -40°C to +125°C 4 4 6 6 16 16 8 8 2 2 Yes Yes CY8C24423A-12PVXE CY8C24423A-12PVXET 4K 4K 256 256 No No -40°C to +125°C -40°C to +125°C 4 4 6 6 24 24 12[1] 12[1] 2 2 Yes Yes Package Ordering Code The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes. 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) Ordering Code Definitions CY 8 C 24 xxx-12xx Package Type: Thermal Rating: PX = PDIP Pb-free A = Automotive -40°C to +85°C SX = SOIC Pb-free C = Commercial PVX = SSOP Pb-free I = Industrial LFX/LKX = QFN Pb-free E = Automotive Extended -40°C to +125°C AX = TQFP Pb-free CPU Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 38-12029 Rev. *L Page 32 of 34 CY8C24223A, CY8C24423A Document History Page Document Title: CY8C24223A, CY8C24423A Automotive - Extended Temperature PSoC® Programmable System-on-Chip Document Number: 38-12029 Orig. of Submission Rev. ECN Description of Change Change Date 238268 SFV See ECN First release of CY8C24x23A Automotive Preliminary Data Sheet. ** 271471 HMT See ECN Update per SFV memo. Input MWR changes, including removing SMP. Change *A to Final. *B 286089 HMT See ECN Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table. 512475 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note *C to pinout tables. Update typical and recommended Storage Temperature per extended temp. specs. Update CY branding and QFN convention. Update copyright and trademarks. *D 2101387 AESA See ECN Post to www.cypress.com *E 2619935 OGNE/AESA 12/11/2008 Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™” Added note on digital signaling in DC Analog Reference Specifications on page 19. Added Die Sales information note to Ordering Information on page 32. Updated data sheet template. *F 2659314 PRKA/PYRS 02/13/09 Changed title to “Automotive - Extended Temperature CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™” Updated Development Tools and Designing with PSoC Designer sections on pages 5 and 6. *G 2719510 BTK 06/16/09 Changed title. Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of the Register Reference section to “Registers”. Improved formatting of the register tables. Added clarifying comments to some electrical specifications. Changed TRAMP specification per MASJ input. Changed number of analog inputs for 28-pin package to 12 from 10. Fixed all AC specifications to conform to a ±4% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block connections. Added Development Tool Selection section. *H 2822792 BTK/AESA 12/07/2009 Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the text of footnote 10. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Added “Contents” on page 2. This revision fixes CDT 63984. *I 2888007 NJF 03/30/2010 Updated Cypress website links. Updated PSoC Designer Software Subsystems. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings. Updated links in Sales, Solutions, and Legal Information. Removed Third Party Tools and Build a PSoC Emulator into your Board. *J 3184892 PRKA/VIVG 03/01/2011 No change. Sunset review spec. *K 3726340 08/28/2012 tess_ukr/ Updated the following sections: Getting Started, Development Tools, and LURE Designing with PSoC Designer as all the System level designs have been de-emphasized. Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”. Updated package diagrams. Updated solder reflow specifications. *L 4304787 03/11/2014 JICG Updated in new template. Completing Sunset Review. Document Number: 38-12029 Rev. *L Page 33 of 34 CY8C24223A, CY8C24423A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-12029 Rev. *L Revised March 11, 2014 Page 34 of 34 PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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