CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CapSense® Express™ Controllers
With SmartSense™ Auto-tuning
16 Buttons, 2 Sliders, Proximity Sensors
CapSense Express 16 Button Controller
General Description
The CY8CMBR3xxx CapSense® Express™ controllers enable advanced, yet easy-to-implement, capacitive touch sensing user
interface solutions. This register-configurable family, which supports up to 16 capacitive sensing inputs, eliminates time-consuming
firmware development. These controllers are ideal for implementing capacitive buttons, sliders, and proximity sensing solutions with
minimal development-cycle times.
The CY8CMBR3xxx family features an advanced analog sensing channel and the Capacitive Sigma Delta PLUS (CSD PLUS) sensing
algorithm, which delivers a signal-to-noise ratio (SNR) of greater than 100:1 to ensure touch accuracy even in extremely noisy
environments. These controllers are enabled with Cypress's SmartSense™ Auto-tuning algorithm, which compensates for manufacturing variations and dynamically monitors and maintains optimal sensor performance in all environmental conditions. In addition,
SmartSense Auto-tuning enables a faster time-to-market by eliminating the time-consuming manual tuning efforts during development
and production ramp-up.
Advanced features, such as LED brightness control, proximity sensing, and system diagnostics, save development time. These
controllers enable robust water-tolerant designs by eliminating false touches due to mist, water droplets, or streaming water. The
CY8CMBR3xxx controllers are offered in a variety of small form factor industry-standard packages.
The ecosystem for the CY8CMBR3xxx family includes development tools—software and hardware—to enable rapid user interface
designs. For example, the EZ-Click Customizer tool is a simple graphical user interface software for configuring the device features
through the I2C interface. This tool also supports CapSense data viewing to monitor system performance and support validation and
debugging. Another tool, the Design Toolbox, simplifies circuit board layout by providing design guidelines and layout recommendations to optimize sensor size, trace lengths, and parasitic capacitance. To quickly evaluate the CY8CMBR3xxx family features, use
the CY3280-MBR3 Evaluation Kit.
Features
■
■
■
Flanking Sensor Suppression (FSS) to eliminate false touches in closely spaced buttons
❐ Analog voltage output
❐ Attention line interrupt to the host to indicate any change in
sensor status
❐
Register-configurable CapSense Express controller
❐ No firmware development required
❐ Patented CSD sensing algorithm
❐ High sensitivity (0.1 pF)
• Overlay thickness of up to 15 mm for glass and 5 mm for
plastic
• Proximity solutions
• Sensitivity up to 2 fF per count
❐ Best-in-class >100:1 SNR performance
• Superior noise-immunity performance against conducted
and radiated noise
• Ultra-low radiated emissions
❐ SmartSense Auto-tuning
• Sets and maintains optimal sensor performance during
run time
• Eliminates manual tuning during development and production
■
System diagnostics to detect
❐ Improper value of the modulating capacitor (CMOD)
❐ Out of range sensor parasitic capacitance (CP)
❐ Sensor shorts
■
EZ-Click™ Customizer tool
❐ Simple GUI for device configuration
❐ Data viewing and monitoring for CapSense buttons, sliders,
and proximity sensors
❐ System diagnostics for rapid debug
■
I2C slave
❐ Supports up to 400 kHz
❐ Wake-on-hardware address match
❐ No bus-stalling or clock-stretching during transactions
Low-power CapSense
❐ Average current consumption of 22 µA per sensor at 120-ms
refresh interval
❐ Wide parasitic capacitance (CP) range: 5–45 pF
■
Low-power 1.71-V to 5.5-V operation
2
❐ Deep Sleep mode with wake-up on interrupt and I C address
detect
■
Industrial temperature range: –40 °C to +85 °C
Advanced user interface features
❐ Water tolerance
❐ User-configurable LED brightness for visual touch feedback
• Up to eight high-sink current GPOs to drive LEDs
❐ Buzzer signal output for audible touch feedback
■
Package options
❐ 8-pin SOIC (150 mil)
❐ 16-pin SOIC (150 mil)
❐ 16-pin QFN (3 × 3 × 0.6 mm)
❐ 24-pin QFN (4 × 4 × 0.6 mm)
Cypress Semiconductor Corporation
Document Number: 001-85330 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Revised May 6, 2014
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Contents
System Overview.............................................................. 3
Features Overview............................................................ 4
CapSense Sensors ..................................................... 4
Sliders ......................................................................... 4
Proximity Sensors ....................................................... 4
SmartSense Auto-tuning ............................................. 4
Water Tolerance.......................................................... 4
Noise Immunity............................................................ 4
Flanking Sensor Suppression (FSS) ........................... 4
Touch Feedback.......................................................... 4
General-Purpose Outputs (GPOs) .............................. 4
Buzzer Drive................................................................ 4
Register Configurability ............................................... 5
Communication to Host ............................................... 5
System Diagnostics..................................................... 5
Ultra-Low Power Consumption.................................... 5
Pinouts .............................................................................. 6
CY8CMBR3116 (16 Sensing Inputs)........................... 6
CY8CMBR3106S (16 Sensing Inputs; Sliders Supported) 7
CY8CMBR3108 (8 Sensing Inputs)............................. 8
CY8CMBR3110 (10 Sensing Inputs)........................... 9
CY8CMBR3102 (2 Sensing Inputs)........................... 10
CY8CMBR3002 (2 Sensing Inputs)........................... 10
CY8CMBR3xxx Ecosystem............................................ 11
Documentation ............................................................... 11
Design Guides........................................................... 11
Registers TRM .......................................................... 11
Software Utility ............................................................... 11
EZ-Click Customizer Tool.......................................... 11
Tools ................................................................................ 11
Design Toolbox ......................................................... 11
Evaluation Kits........................................................... 11
Online ........................................................................ 11
Training ..................................................................... 11
Technical Support ..................................................... 11
Device Feature Details ................................................... 12
Automatic Threshold ................................................. 12
Sensitivity Control...................................................... 12
Sensor Auto Reset .................................................... 12
Noise Immunity.......................................................... 13
Flanking Sensor Suppression ................................... 13
General-Purpose Outputs ......................................... 13
Document Number: 001-85330 Rev. *G
LED ON Time ............................................................
Toggle .......................................................................
Buzzer Signal Output ................................................
Host Interrupt.............................................................
Latch Status Output...................................................
Analog Voltage Output ..............................................
System Diagnostics...................................................
Example Application Schematics .................................
Power Supply Information .............................................
Electrical Specifications ................................................
Absolute Maximum Ratings.......................................
Operating Temperature .............................................
DC Electrical Characteristics.....................................
AC Electrical Specifications.......................................
I2C Specifications......................................................
System Specifications ...................................................
Power Consumption and Operational States ..............
Response Time ...............................................................
CY8CMBR3xxx Resets ...................................................
Host Communication Protocol......................................
I2C Slave Address.....................................................
I2C Communication Guidelines.................................
Write Operation .........................................................
Setting the Device Data Pointer ................................
Read Operation .........................................................
Layout Guidelines and Best Practices .........................
Ordering Information......................................................
Packaging Dimensions ..................................................
Thermal Impedances.................................................
Solder Reflow Specifications.....................................
Appendix .........................................................................
Units of Measure .......................................................
Glossary ..........................................................................
Reference Documents....................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Page 2 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
System Overview
A capacitive sensor detects changes in capacitance to determine
the presence of a touch or proximity to conductive objects. The
capacitive sensor can be a capacitive button that replaces the
traditional mechanical buttons, a capacitive slider that replaces
mechanical knobs, or a proximity sensor that replaces an
infrared sensor in a user interface solution. A typical capacitive
user interface system consists of the following:
■
A capacitive sensor
■
An audio-visual output, such as a buzzer or an LED
■
A capacitive sensing controller connected to the sensor
■
A host processor
The capacitive controller connects the sensor and the output to
the host processor through a communication interface, such as
an I2C or a GPO.
The capacitive user interface system serves as a
human-machine interface that takes the user’s touch inputs and
provides audio-visual feedback through a buzzer or an LED.
CY8CMBR3xxx is a family of capacitive sensing controllers,
which senses the change in capacitance based on touch or
proximity, and controls the user interface system accordingly.
The sensing algorithm, built in the controllers, determines the
presence of touch and drives the outputs or sends signals to the
host processor. This algorithm can distinguish between the
signal (based on touch or proximity) and noise, which can be
caused by environmental or electrical conditions.
Figure 1 shows a typical user interface system with capacitive
buttons connected to a CY8CMBR3xxx CapSense Express
controller, which controls the system and also communicates
with the host processor through I2C.
Traditionally, capacitive sensing controllers require firmware
development to perform specific user interface functions and
manual system tuning to achieve optimal performance.
However, the CY8CMBR3xxx CapSense Express family of
controllers does not require any firmware development, accelerating time-to-market. These devices feature SmartSense
Auto-tuning, which eliminates the need for manual tuning,
providing optimal performance even under extremely noisy
conditions.
Figure 1. Typical CapSense System
CapSense Buttons
Linear Slider
Radial Slider
I2C
HI
CapSense Sensors
CY8CMBR3xxx
CapSense Controller
Host Interrupt
Host
Processor
Buzzer
LEDs
Outputs
Document Number: 001-85330 Rev. *G
Page 3 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Features Overview
The CY8CMBR3xxx family offers water-tolerance to liquids such
as water, ketchup, oil, and blood.
CapSense Sensors
Enable the shield electrode through the register map, using
EZ-Click, to prevent false touches under wet conditions and
enable both the shield electrode and guard sensor to prevent
false touches in streaming water conditions. The shield electrode
and guard sensor consume a port pin each in the CapSense
controller. Refer to the CY8CMBR3xxx CapSense Design Guide
for best practices and design guidelines for implementing
water-tolerant designs.
The CY8CMBR3xxx family of controllers supports up to 16
capacitive sensors. These can be configured as follows:
■
Up to 16 CapSense buttons
■
Up to two sliders: Configurable as linear or radial sliders
■
Up to two proximity sensors that can detect up to 30-cm
proximity distance
Sliders
■
Supports up to two 5-segment sliders
■
Configures each slider individually as linear or radial
■
Combines both sliders to form one 10-segment slider
■
Slider resolution is user-configurable
Proximity Sensors
■
The CY8CMBR3xxx family supports up to two proximity
sensors with a detection range of up to 30 cm. These proximity
sensors are capable of detecting both proximity and touch
events.
■
The wake-on-approach feature wakes the devices from a
low-power state to Active mode on a proximity event.
■
The device also features driven shield, which enhances the
proximity sensing range in the presence of metal objects.
■
The device supports proximity sensors with CP ranging from
8 pF to 45 pF.
SmartSense Auto-tuning
The CY8CMBR3xxx family features SmartSense Auto-tuning,
Cypress's patented CapSense algorithm, which continuously
compensates for system and environmental changes during run
time. SmartSense Auto-tuning has the following advantages:
■
Reduces design effort by eliminating manual tuning
■
Adapts to variations in PCB, overlay, paint, and manufacturing
that degrade touch-sensing performance
■
Eliminates manual tuning in production
■
Adapts to changes in the system environment due to noise
■
Allows a platform design approach with different overlays,
button shapes, and trace lengths
Water Tolerance
The CY8CMBR3xxx family delivers water-tolerant designs that
eliminate false touches due to wet conditions, such as water
droplets, moisture, mist, steam, or even wet hands. The
CapSense controller locks up the user interface in firmware to
prevent touch inputs in streaming water.
Document Number: 001-85330 Rev. *G
Noise Immunity
The CY8CMBR3xxx family features the robust CSD PLUS
capacitive sensing algorithm. Additionally, it implements the
advanced noise immunity algorithm, EMC, for stable operation
in extremely noisy conditions.
The EMC algorithm has higher average power consumption. For
low-power applications, where noise conditions are not extreme,
you can disable this feature through the I2C interface.
Flanking Sensor Suppression (FSS)
This feature distinguishes between signals from closely spaced
buttons, eliminating false touches. It ensures that the system
recognizes only the first button touched.
Touch Feedback
The CY8CMBR3xxx family has pins that you can configure for
audio-visual feedback through a buzzer or an LED.
General-Purpose Outputs (GPOs)
The GPOs are high-sink current, open-drain outputs that can
drive most LEDs. The GPO status can be controlled directly by
the CapSense sensors so that a sensor 'ON' status automatically
turns ON a corresponding LED. Alternatively, GPOs can be
controlled by the host through the I2C interface.
The GPOs also support advanced features, such as:
■
CSx to GPOx Direct Drive: Directly control the GPOs upon
button touch or proximity event.
■
Pulse width modulation (PWM): Controls LED brightness.
■
Toggle: The GPO status is toggled upon every touch event on
the button sensors, and proximity event on proximity sensors,
to mimic the functionality of the mechanical toggle switch.
■
Voltage output: Analog voltage that represents the button
status.
Buzzer Drive
The output pins of the CY8CMBR3xxx controllers can be
configured for driving a single-input DC Piezo-electric buzzer
through a PWM. The PWM frequency and buzzer activation
duration are configurable. The buzzer output is activated for a
finite amount of time when a finger touch is detected.
Page 4 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Register Configurability
The CY8CMBR3xxx registers may be configured through the I2C
The built-in system diagnostics detects the following fault conditions at power-up and helps to monitor the following:
interface. Device features may be enabled, disabled, or modified
by writing appropriate values to the I2C configurable register
map. This register map also provides various status outputs to
indicate the touch/release status and system performance and
debug parameters.
■
Improper value of the modulating capacitor (CMOD)
■
CP value out of range
■
Sensor shorts
You can access the register map of the device through the I2C
interface by a host controller, such as a microcontroller or the
EZ-Click Customizer.
Ultra-Low Power Consumption
The CY8CMBR3xxx devices feature a safe register map update
mechanism to overcome configuration data corruption, which
can occur due to power failure during flash writes or any other
spurious events. If the configuration data is corrupted during a
register map update, the devices reconfigure themselves to the
last known valid configuration.
For low-power applications, such as those operated by a battery,
select a capacitive sensing controller that has ultra-low average
power consumption.
The CY8CMBR3xxx controllers draw an average current of
22 µA per sensor at 1.8 V.
The CY8CMBR3xxx family supports two operating modes:
■
Active: The sensors are scanned periodically for power
optimization.
■
Deep Sleep: The sensors are not scanned until a command
from the host is received to resume sensor scanning.
Communication to Host
The CY8CMBR3xxx family communicates to a host processor
through the following methods:
■
■
■
The I2C interface allows the host to configure parameters and
receive status information on touch events
The host interrupt alerts the host when a new touch event
occurs. This helps to build effective communication between
the host and the CapSense controller. Alternatively, the CPU
can poll the device status by reading through I2C.
The GPO provides the ON or OFF sensor status to the host.
The GPO ports can also be used to implement analog voltage
and DC output (DCO) using an external resistor network.
In the Active mode, CY8CMBR3xxx family implements additional
techniques, such as optimizing the average power consumption
and providing a smooth user interface experience without
increasing the refresh interval.
In addition to these modes, the device has a wake-on approach
feature, which uses proximity sensing to reduce the average
power consumption, ensuring power saving when the system is
inactive.
Details of all features are documented in Device Feature Details
on page 12.
System Diagnostics
The CY8CMBR3xxx devices are equipped with a system
diagnostics feature to detect system-level fault conditions and to
avoid failure of the user interface design. The system diagnostic
features also help to monitor system-level parameters to debug
the design during development.
Document Number: 001-85330 Rev. *G
Page 5 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Pinouts
CY8CMBR3116 (16 Sensing Inputs)
Table 1. Pin Diagram and Definitions - CY8CMBR3116
24-QFN
1
CS0/PS0
–
CapSense button / proximity sensor,
controls GPO0
Ground/Ground
CS0
2
CS1/PS1
–
CapSense button / proximity sensor,
controls GPO1
Ground/Ground
CS1
3
CS2/GUARD
–
CapSense button / guard sensor,
controls GPO2
Ground/Ground
CS2
4
CS3
–
CapSense button, controls GPO3
Ground
CS3
5
CMOD
–
External modulator capacitor. Connect NA
2.2 nF/5 V/X7R or NPO capacitor
6
VCC
Power Internal regulator output. Connect a
NA
0.1-µF decoupling capacitor if VDD >
1.8 V. If VDD is 1.71 V to 1.89 V, short
this pin to VDD.
VCC
7
VDD
Power Power
NA
VDD
Power Ground
NA
VSS
CMOD
8
VSS
9
CS15/SH/HI
I/DO
CapSense button / shield electrode/
Host Interrupt (SPO1 in the register
map)
Ground/Leave
open/Leave open
10
CS14/GPO6
I/DO
CapSense button / general purpose
output (GPO)
Ground/Leave open
GPO6
11
CS13/GPO5
I/DO
CapSense button / GPO
Ground/Leave open
GPO5
12
CS12/GPO4
I/DO
CapSense button / GPO
Ground/Leave open
GPO4
13
CS11/GPO3
I/DO
CapSense button / GPO
Ground/Leave open
GPO3
14
CS10/GPO2
I/DO
CapSense button / GPO
Ground/Leave open
GPO2
15
CS9/GPO1
I/DO
CapSense button / GPO
Ground/Leave open
GPO1
16
CS8/GPO0
I/DO
CapSense button / GPO
Ground/Leave open
GPO0
17
CS7
–
CapSense button, controls GPO7
Ground
CS7
18
CS6
–
CapSense button, controls GPO6
Leave open
CS6
19
CS5
–
CapSense button, controls GPO5
Ground
CS5
CS0/PS0
CS1/PS1
CS2/GUARD
CS3
CMOD
VCC
1
2
3
4
5
6
18
17
16
QFN
(Top View) 15
14
13
CS6
CS7
CS8/GPO0
CS9/GPO1
CS10/GPO2
CS11/GPO3
HI
20
CS4
–
CapSense button, controls GPO4
Ground
21
I2C SDA
DIO
I2C data
Leave open
I2C SDA
22
I2C SCL
DIO
I2C clock
Leave open
I2C SCL
23
HI/BUZ/
GPO7
DO
Host Interrupt/buzzer output/ GPO
(SPO0 in the register map)
Leave open/ leave
open/ leave open
24
XRES
25
Center Pad[1]
CS4
GPO7
XRES Active Low external reset (an active low Leave open
pulse on this pin resets the CapSense
Controller)
XRES
E-pad Connect to VSS for best mechanical,
thermal, and electrical performance
E-pad
Floating, not
connected to any
other signal
Pin Diagram
XRES
HI/BUZ/GPO7
I2C SCL
I2C SDA
CS4
CS5
If unused
24
23
22
21
20
19
Type
7
8
9
10
11
12
Pin Name
VDD
VSS
5/SH/HI
4/GPO6
3/GPO5
2/GPO4
Description
Default
Configuration
Pin #
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, DO = Digital Output, CS = CapSense Button, PS = Proximity Sensor
SH = Shield Electrode, BUZ = Buzzer Output, GPO = General Purpose Output, GUARD = Guard Sensor, SPO = Special purpose output.
Note
1. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If it is not connected to ground,
it should be left floating without being connected to any other signal.
Document Number: 001-85330 Rev. *G
Page 6 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CY8CMBR3106S (16 Sensing Inputs; Sliders Supported)
Table 2. Pin Diagram and Definitions - CY8CMBR3106S
24-QFN
1
CS0/PS0
–
CapSense button / proximity
sensor
Ground/Ground
CS0
2
CS1/PS1
–
CapSense button / proximity
sensor
Ground/Ground
CS1
3
CS2
–
CapSense button
Ground
CS2
4
CS3
–
CapSense button
Ground
5
CMOD
–
External modulator capacitor.
Connect 2.2 nF/ 5 V/X7R or
NPO capacitor
NA
6
VCC
Power
Internal regulator output.
NA
Connect a 0.1-µF decoupling
capacitor if VDD > 1.8 V. If VDD
is 1.71 V to 1.89 V, short this pin
to VDD.
VCC
7
VDD
Power
Power
NA
VDD
CS3
CMOD
8
VSS
Power
Ground
NA
9
SLD10
–
Slider1, segment0
Ground
SLD10
10
SLD11
–
Slider1, segment1
Ground
SLD11
11
SLD12
–
Slider1, segment2
Ground
SLD12
12
SLD13
–
Slider1, segment3
Ground
SLD13
13
SLD14
–
Slider1, segment4
Ground
SLD14
14
CS11/SLD20
–
CapSense button / Slider2,
segment0
Ground/Ground
SLD20
15
CS12/SLD21
–
CapSense button / Slider2,
segment1
Ground/Ground
SLD21
16
CS13/SLD22
–
CapSense button / Slider2,
segment2
Ground/Ground
SLD22
17
CS14/SLD23
–
CapSense button / Slider2,
segment3
Ground/Ground
SLD23
18
CS15/SLD24
–
CapSense button / Slider2,
segment4
Leave open/Leave open
SLD24
19
CS5/SH/HI
–
CapSense button / shield
electrode/host interrupt.
(SPO1 in the register map)
Ground/Leave open/Leave
open
CS4
–
CapSense Button
Ground
I2C SDA
DIO
I2C Data
Leave open
I2C SDA
22
I2C SCL
DIO
I2C Clock
Leave open
I2C SCL
23
HI/BUZ
O
Host interrupt / buzzer output.
This pin acts as SPO0 for this
device (SPO0 in register map).
Leave open/Leave open
24
XRES
XRES
External reset
Leave open
XRES
E-pad
Connect to VSS for best
mechanical, thermal and
electrical performance
Floating, not connected to
any other signal
E-pad
Center
1
2
3
4
5
6
18
17
16
QFN
(Top View) 15
14
13
CS15/SLD24
CS14/SLD23
CS13/SLD22
CS12/SLD21
CS11/SLD20
SLD14
CS5
21
25
CS0/PS0
CS1/PS1
CS2
CS3
CMOD
VCC
VSS
20
Pad[2]
Pin Diagram
XRES
HI/BUZ
I2C SCL
I2C SDA
CS4
CS5/SH/HI
If unused
24
23
22
21
20
19
Type
7
8
9
10
11
12
Pin Name
VDD
VSS
SLD10
SLD11
SLD12
SLD13
Description
Default
Configuration
Pin #
CS4
HI
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, CS = CapSense Button,
PS = Proximity Sensor, SH = Shield Electrode, BUZ = Buzzer Output, SPO = Special Purpose Output.
Note
2. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If it is not connected to ground,
it should be left floating without being connected to any other signal.
Document Number: 001-85330 Rev. *G
Page 7 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CY8CMBR3108 (8 Sensing Inputs)
Table 3. Pin Diagram and Definitions - CY8CMBR3108
16-QFN
CapSense button / proximity
sensor, controls GPO0
Ground/Ground
CS0
2
CS1/PS1
–
CapSense button / proximity
sensor, controls GPO1
Ground/Ground
CS1
3
CMOD
–
External modulator capacitor.
Connect 2.2 nF/5 V/X7R or
NPO capacitor
NA
CMOD
CS0/PS0
VCC
Power
Internal regulator output.
NA
Connect a 0.1-µF decoupling
capacitor if VDD > 1.8 V. If VDD
is 1.71 V to 1.89 V, short this pin
to VDD
VCC
5
VDDIO
Power
Power for I2C and HI lines
Connect to VDD
6
VDD
Power
Power
NA
VDD
7
VSS
Power
Ground
NA
VSS
8
CS4/GPO0
I/DO
CapSense button / GPO
Ground/Leave open
GPO0
VDDIO
9
CS5/GPO1
–
CapSense button / GPO
Ground/Leave open
GPO1
10
CS6/GPO2
I/DO
CapSense button / GPO
Ground/Leave open
GPO2
11
CS7/GPO3/
SH
I/DO
CapSense button / GPO/ shield Ground/Leave open
electrode.
(SPO1 in the register map)
GPO3
12
CS2/GUARD
–
CapSense button, controls
GPO2 / guard sensor
Leave open/Leave open
CS2
13
CS3
–
CapSense button, controls
GPO3
Ground
CS3
14
I2C SDA
DIO
I2C data
Leave open
I2C SDA
15
I2C SCL
DIO
I2C clock
Leave open
I2C SCL
16
HI/BUZ
DO
Host interrupt / buzzer output
Leave open/leave open
Supply voltage for buzzer and
pull-up resistor on HI should be
equal to VDDIO
(SPO0 in the register map).
17
Center Pad[3]
E-pad
Floating, not connected to
any other signal
1
2
3
4
QFN
(Top View)
12
11
10
9
CS2/GUARD
CS7/GPO3/SH
CS6/GPO2
CS5/GPO1
5
6
7
8
4
CS1/PS1
CMOD
VCC
CS3
–
I2C SCL
I2C SDA
CS0/PS0
14
13
1
Connect to VSS for best
mechanical, thermal and
electrical performance
Pin Diagram
VDD
VSS
CS4/GPO0
If unused
HI/BUZ
Type
16
15
Pin Name
VDDIO
Description
Default
Configuration
Pin #
HI
E-pad
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, CS = CapSense Button, PS = Proximity Sensor
SH = Shield Electrode, BUZ = Buzzer Output, GPO = General Purpose Output, GUARD = Guard Sensor, SPO = Special Purpose Output.
Note
3. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If it is not connected to ground,
it should be left floating without being connected to any other signal.
Document Number: 001-85330 Rev. *G
Page 8 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CY8CMBR3110 (10 Sensing Inputs)
Table 4. Pin Diagram and Definitions - CY8CMBR3110
16-SOIC
Pin Name
Type
1
I2C SDA
DIO
I2C data
Leave open
I2C SDA
2
I2C SCL
DIO
I2C clock
Leave open
I2C SCL
3
CS0/PS0
–
4
5
CS1/PS1
CMOD
–
–
Description
If unused
Default
Configuration
Pin #
CapSense button / proximity Ground/Ground
sensor, controls GPO0
CS0
CapSense button / proximity Ground/Ground
sensor, controls GPO1
CS1
External modulator capacitor. NA
Connect 2.2 nF/5 V/X7R or
NPO capacitor
CMOD
6
VCC
Power
Internal regulator output.
NA
Connect a 0.1-µF decoupling
capacitor if VDD > 1.8 V. If
VDD is 1.71 V to 1.89 V, short
this pin to VDD
VCC
7
VDD
Power
Power
NA
VDD
8
VSS
Power
9
CS5/GPO0
I/DO
Ground
NA
CapSense button / GPO
Ground/Leave open
GPO0
Pin Diagram
I2C SDA
1
16
I2C SCL
2
15
CS3
CS0/PS0
3
14
CS9/GPO4/HI/BUZ
CS1/PS1
4
13
CS2/GUARD
CMOD
5
12
VCC
6
11
CS8/GPO3
CS7/GPO2
VDD
7
10
CS6/GPO1
VSS
8
9
CS5/GPO0
SOIC
CS4/SH
VSS
10
CS6/GPO1
I/DO
CapSense button / GPO
Ground/Leave open
GPO1
11
CS7/GPO2
I/DO
CapSense button / GPO
Ground/Leave open
GPO2
12
CS8/GPO3
I/DO
CapSense button / GPO
Ground/Leave open
GPO3
13
CS2/GUARD
–
CapSense button, controls
GPO2 / guard sensor
Ground/Leave open
CS2
14
CS9/GPO4/HI/
BUZ
I/DO
CapSense button / GPO /
host interrupt/buzzer output.
(SPO1 in the register map)
Leave open/Leave
open/Leave
open/Leave open
GPO4
15
CS3
–
CapSense button, controls
GPO3
Ground
CS3
16
CS4/SH
I/O
CapSense button, controls
GPO4/ shield electrode
(SPO0 in the register map).
Ground/Leave open
CS4
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, CS = CapSense Button, PS = Proximity Sensor
SH = Shield Electrode, BUZ = Buzzer Output, GPO = General Purpose Output, GUARD = Guard Sensor, SPO = Special Purpose Output.
Document Number: 001-85330 Rev. *G
Page 9 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CY8CMBR3102 (2 Sensing Inputs)
Table 5. Pin Diagram and Definitions - CY8CMBR3102
8-SOIC
Pin #
Pin Name
Type
1
I2C SCL
DIO
2
CMOD
–
VCC
3
4
Description
Power
VDD
Default
Configuration
If unused
I2C clock
Leave open
External modulator capacitor.
Connect 2.2 nF/5 V/X7R or NPO
capacitor
NA
I2C SCL
CMOD
Internal regulator output. Connect a NA
0.1-µF decoupling capacitor if VDD
> 1.8 V. If VDD is 1.71 V to 1.89 V,
short this pin to VDD.
VCC
Power
Power
NA
VDD
NA
5
VSS
Power
Ground
6
CS1/PS1/
GPO0/SH
I/DO/O
CapSense button / proximity sensor/ Ground/Ground/
GPO/ shield electrode (SPO0 in the Leave open/leave
register map).
Open
GPO0
7
CS0/PS0
–
CapSense button / proximity sensor, Leave open/Leave
open
controls GPO0
CS0
8
I2C SDA
DIO
I2C data
Pin Diagram
SCL
, I,I2C
P0[5]
, I,CMOD
P0[3]
CL, P1[1]
VCC
VDD
Vss
1
2
3
4
SOIC
8
7
6
5
I2C
SDA
Vdd
CS0/PS0
P0[4], A,
I
P0[2], A, I
CS1/PS1/GPO0/SH
VSS
P1[0],
I2C SDA
VSS
Leave open
I2C SDA
Legend: I = Analog Input, O = Analog Output, DIO = Digital Input/Output, CS = CapSense Button, PS = Proximity Sensor,
SH = Shield Electrode, GPO = General Purpose Output, SPO = Special Purpose Output.
CY8CMBR3002 (2 Sensing Inputs)
Table 6. Pin Diagram and Definitions - CY8CMBR3002
8-SOIC
Pin #
Pin Name
Type
1
GPO1
DO
GPO
2
CMOD
I/O
External modulator capacitor.
Connect 2.2 nF/5 V/X7R or NPO
capacitor
NA
Internal regulator output. Connect
a 0.1-µF decoupling capacitor if
VDD > 1.8 V. If VDD is 1.71 V to
1.89 V, short this pin to VDD.
NA
3
VCC
Power
Description
If unused
Pin Diagram
Leave open
4
VDD
Power
Power
NA
5
VSS
Power
Ground
NA
6
CS1
–
CapSense button, controls GPO1
Ground
7
CS0
–
CapSense button, controls GPO0
Leave open
8
GPO0
DO
GPO
Leave open
, I,GPO1
P0[5]
, I,CMOD
P0[3]
CL, P1[1]
VCC
VDD
Vss
1
2
3
4
8
7
SOIC
6
5
GPO0
Vdd
CS0
P0[4],
A, I
A, I
VSS
P1[0], I2C
P0[2],
CS1
Legend: I = Analog Input, DO = Digital Output, CS = CapSense Button, GPO = General Purpose Output
Document Number: 001-85330 Rev. *G
Page 10 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CY8CMBR3xxx Ecosystem
Tools
Cypress provides a complete ecosystem to enable a quick development cycle with the CY8CMBR3xxx CapSense controller
family. This ecosystem includes simple tools for device configuration, design validation, and diagnostics.
Design Toolbox
Documentation
Design Guides
Design guides are an excellent introduction to a variety of
possible CapSense-based designs. They provide an introduction to the solution and complete system design guidelines.
Refer to the following design guides for CY8CMBR3xxx:
1. Getting Started with CapSense – an ideal starting point for all
CapSense users
2. CY8CMBR3xxx CapSense Design Guide – provides
complete system design guidelines for CY8CMBR3xxx
You can download these design guides from our website:
www.cypress.com/go/capsense.
Registers TRM
The CY8CMBR3xxx Registers TRM lists and details all the
registers of the CY8CMBR3xxx family of controllers in order of
their addresses. These registers may be accessed through an
I2C interface with the host.
Software Utility
EZ-Click Customizer Tool
The EZ-Click Customizer Tool is a simple, GUI-based software
utility that can be used to customize the CY8CMBR3xxx device
configurations.
Use this GUI-based tool to do the following:
■
Select the appropriate part number based on an
end-application requirement using the Product Selector
■
Configure the device features
■
Observe CapSense data for button and proximity sensors
■
Use the System Diagnostics and built-in test self-test (BIST)
features for debug and production-line testing
Document Number: 001-85330 Rev. *G
The Design Toolbox is an interactive spreadsheet tool that
provides application-specific design guidelines for capacitive
buttons. It is used to configure and validate the CapSense
system.
The Design Toolbox:
■
Provides general layout guidelines for a CapSense PCB
■
Estimates button dimensions based on end-application
requirements
■
Calculates power consumption based on button dimensions
■
Validates layout design
Evaluation Kits
The CY3280-MBR3 Evaluation Kit can be used to quickly
evaluate the various features of the CY8CMBR3xxx solution.
The kit also functions as an Arduino shield, making it compatible
with the various Arduino-based controllers in the market. You can
purchase this kit at the Cypress online store.
Online
In addition to print documentation, there are abundant web
resources. The dedicated web page for the CY8CMBR3xxx
family has all the current information.
Training
Free PSoC and CapSense technical training (on-demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and supports different skill levels to assist you in your
designs.
Technical Support
For assistance with technical issues, search the Knowledge
Base articles and forums at www.cypress.com/support. If you
cannot find an answer to your question, create a technical
support case or call technical support at 1-800-541-4736.
Page 11 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Device Feature Details
Automatic Threshold
Table 7. Device Feature Benefits
■
Dynamically sets all threshold parameters for button sensors,
depending on the noise in the environment.
■
Applicable only to button sensors.
■
Mutually exclusive from the EMC feature. If EMC is enabled,
automatic threshold is automatically disabled.
Feature
Benefits
Automatic Threshold
Automatically tunes all the threshold
parameters of the sensors for
different noise settings
Sensitivity Control
Maintains optimal button
performance for different overlay
and noise conditions
Sensor Auto Reset
Noise Immunity
Flanking Sensor
Suppression (FSS)
Host Controlled GPOs
Recalibrates the sensor when a
stuck-sensor (fault) condition
occurs, and avoids invalid sensor
output status to host
Provides immunity against external
noise and the ability to detect
touches without false trigger in noisy
environments
Avoids multiple button triggers in a
design with closely spaced buttons
GPO pins, which can be controlled
by the host processor through I2C
LED On time
GPO output status stays ON for a
set duration after the touch is
released to provide better visual
feedback to the user
Toggle
Sensor output status toggles on
every sensor activation to mimic the
mechanical toggle button
functionality
Buzzer Signal Output
Provides audio feedback on button
touch
Host Interrupt
Provides interrupt to host when
there is a change in sensor status
Latch Status Output
Latches the sensor status changes
in the register until the host reads
the activated sensor status; this
ensures that the sensor status is
always read by the host even if the
host is late to service the host
interrupt signal from CY8CMBR3xxx
Analog Voltage Output
Indicates the button status through
voltage levels
System Diagnostics
Supports production testing and
debugging
Sensitivity Control
This feature allows specification of the minimum change in
sensor capacitance that can trigger a sensor state change (OFF
to ON or vice-versa).
■
Sensitivity can be specified individually for each CapSense
button and slider.
■
Sensitivity can be specified as one of the four available values:
0.1 pF, 0.2 pF, 0.3 pF, and 0.4 pF.
■
Higher sensitivity values can be used for thick overlays or small
button diameters.
■
Lower sensitivity values should be used for large buttons or
thin overlays to minimize power consumption.
Sensor Auto Reset
This feature resets the CapSense sensors to the OFF state after
a specific time period, even though they continue to be activated.
■
Resets the sensor baseline to the current raw count after a
specific time period, even though the sensors continue to be
activated.
■
Prevents a stuck sensor when a metal object is placed close
to that sensor.
■
The Auto Reset period can be set to 5 or 20 seconds and can
be configured through two global settings provided in the
register map:
❐ Global setting for all proximity sensors
❐ Global setting for all CapSense buttons and slider segments
■
The guard sensor does not undergo Auto Reset.
Figure 2. Example of Button Auto Reset on GPO0 (DC Active
Low Output)
Sensor
Activated
Auto Reset Period
CSx
Touch on Sensor
GPOx
GPOx turns inactive as Auto
Reset period expired for CSx
Low-Power Sleep Mode Reduces power consumption
and Deep Sleep Mode
Document Number: 001-85330 Rev. *G
Page 12 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Noise Immunity
General-Purpose Outputs
■
The CY8CMBR3xxx family features the robust CSD PLUS
capacitive sensing algorithm.
■
Supports up to eight GPOs, multiplexed with sensor inputs or
other functionality, depending on the part number.
■
Uses pseudo-random sequence (PRS) clock source to
minimize electromagnetic interference.
■
■
Provides advanced noise immunity algorithm, that is, electromagnetic compatibility (EMC), for superior noise immunity
against external radiated and conducted noise
❐ EMC algorithm has higher average power consumption. For
low-power applications, where noise conditions are not extreme, this feature can be disabled using the EZ-Click tool.
Provides GPO status control. GPOs can be configured to be
controlled by the sensor input or the host through the I2C
interface.
■
Allows for configurable Active LOW or Active HIGH logic output.
The Active LOW logic output can be configured to directly drive
LEDs in the current sink mode. The Active HIGH logic output
can be configured to interface the GPOs with the host and other
circuits.
■
The GPOx status will not be retained in the Deep Sleep mode.
The GPOx output state will be reset to default during deep sleep
and upon wake-up from deep sleep.
Flanking Sensor Suppression
■
Distinguishes between signals from closely spaced buttons,
eliminating false touches.
■
Can be enabled or disabled individually on each CapSense
button.
■
On touch detection by two or more sensors on which FSS is
enabled, only the first touched sensor reports active status.
■
Allows only one button at a time to be in the Touch state.
■
Supported only on CapSense buttons.
Figure 4. CSx Controls GPOx (Active HIGH Logic)
Sensor
Activated
CSx
Figure 3. Reported Sensor Status with FSS Enabled
CS0
CS0
CS1
CS1
CS2
CS2
CS3
CS3
GPOx
No sensor touched
■
Supports two drive modes:
❐ Open-drain drive mode (HIGH-Z and GND) for analog voltage outputs and LED direct drive
❐ Strong drive mode (VDD and GND) to interface with the host
and other circuits
■
Supports PWM on GPOs for LED brightness control. Two
different duty cycles can be configured for Sensor Touch and
No Touch states (Active and Inactive state duty cycles). When
the GPO is host-controlled, and if the PWM control is enabled
for the GPO, the same Touch and No Touch duty cycles will be
used for the On and Off states of the host-controlled GPO.
■
When the proximity sensor is enabled, the proximity event
controls the respective GPOs. A touch event on a proximity
sensor is indicated only through the I2C register map.
■
Sensor fault conditions are indicated with the pulse signal on
the respective GPOs at power-up by system diagnostics.
CS1 is touched, CS1 reported ON
CS2 also touched along with CS1,
CS0
CS0
CS1
CS1
CS2
C
S2
CS2
CS3
CS3
Sensor
Deactivated
CS1 is reported ON
Only CS2 is touched; reported ON
LED ON Time
■
Document Number: 001-85330 Rev. *G
Keeps the GPO status ON for a particular period of time after
the falling edge of a sensor, for better visual indication through
LEDs
Page 13 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Figure 5. CSx Controls GPOx with LED ON Time Enabled
Sensor
Activated
CSx physical
status
Sensor
Deactivated
BUTTON_STAT
register shows
sensor inactivation
Buzzer Signal Output
■
Produces a PWM signal to drive a Piezo-Buzzer that generates
audio feedback when a touch is detected on a CapSense button
or a guard sensor.
■
Supports buzzer connection, as shown in the following figure.
Figure 7. Buzzer Connection[4]
CSx bit in
BUTTON_STAT
VDDIO
GPOx
Buzzer
LED ON Time
Button response time
CY8CMBR3xxx
BUZ
■
Can be enabled only when the GPO is directly controlled by a
CapSense sensor
■
Can be enabled or disabled on each sensor and the ON Time
duration can be configured from 0 to 2 seconds in 20-ms increments
■
Can be enabled in all configurations of GPOs except the Toggle
mode
■
Not applicable when the sensor status is turned off by Sensor
Auto Reset
■
PWM frequency is configurable: The buzzer frequency is
configurable to meet different Piezo-Buzzer drive requirements
and to provide different tones. The buzzer frequency may be
configured either by using the EZ-Click tool or by writing to the
corresponding control register. Refer to System Specifications
on page 23 for the supported buzzer frequencies.
■
Generates PWM output for a fixed duration (ON time) when a
touch is detected. The ON time is configurable through
EZ-Click, from 100 ms to 12.7 s, in steps of 100 ms,
■
Buzzer signal output and EMC (refer to the CY8CMBR3xxx
Registers TRM) are mutually exclusive features. These must
not be enabled simultaneously.
Toggle
■
The controller can toggle the GPO state at every rising edge
of a sensor activation event to mimic the functionality of a
mechanical toggle switch (a touch event for a button sensor
and a proximity event for proximity sensors activates a sensor).
Figure 6. CSx Controls GPOx with the Toggle Enabled
Sensor
Activated
Sensor
Deactivated
Sensor
Activated
Figure 8. Buzzer Activation on a Touch Event
Sensor
Activated
CSx
GPOx
■
Can be enabled only when the GPO is directly controlled by a
capacitive sensor.
CSx
■
Can be enabled or disabled individually on each capacitive
sensor.
BUZ
■
Can be enabled in all configurations of GPOs—that is, Active
LOW and Active HIGH DC output, PWM output, open-drain,
and strong drive modes.
CSx Active
Buzzer ON Time
The buzzer output does not restart if multiple trigger events occur
before the Buzzer ON Time elapses.
Note
4. Buzzer must be connected between VDDIO and the BUZ pin. If VDDIO is not available on the device, connect the buzzer to VDD instead of VDDIO.
Document Number: 001-85330 Rev. *G
Page 14 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Figure 9. Buzzer Operation with Consecutive Touches
Sensor
Activated
Sensor
Re‐activated
Latch Status Output
■
Allows to read both current status (CS) and latch status (LS)
to avoid missing button touches.
■
CS and LS can be read through registers, BUTTON_STAT, and
LATCHED_BUTTON_STAT respectively.
Table 8 explains the various combinations of CS and LS.
CSx
Table 8. Latch Status Read
BUZ
CS LS
If the buzzer is not currently active, the buzzer output starts on
each trigger event.
■
■
When the buzzer is enabled, the buzzer output toggles between
a Logic HIGH state and a Logic LOW state, to drive the buzzer
when active. When the buzzer is inactive, the buzzer output
maintains a Logic HIGH state.
The buzzer ON Time has a range of (1 to 127) × 100 ms.
Host Interrupt
This feature generates a pulse signal on any change in the
CapSense sensors' status.
■
The host interrupt is an active LOW pulse signal generated on
the HI pin during any change in the sensor status or slider
position.
■
The duration of the active LOW host interrupt pulse is THI (refer
to System Specifications on page 23).
■
The minimum time between two HI pulses is equal to one
refresh interval.
Description
0
0
CSx is not touched during the current I2C read
Host has already acknowledged any previous CSx touch in
the previous I2C read
0
1
CSx was touched before the current I2C read
This CSx touch was missed by the host
Analog Voltage Output
Some of the applications use analog voltage as an effective
method to indicate the sensor status to the host controller. A
simple external resistor network can be used with GPOs of
CY8CMBR3xxx to generate analog voltage output upon touch
detection for such applications.
The CY8CMBR3xxx GPOs support the open-drain low-drive
mode. In this mode, the sensor “touch” state is indicated by a
logic LOW signal on the GPO and a "no touch" state is indicated
by the HIGH-Z signal. With the external resistor shown in Figure
11, when a sensor is touched, the respective GPO is driven to a
logic LOW signal. This forms a simple voltage divider and
produces a voltage output. All the other GPOs are in HIGH-Z
states because their respective sensors are in the "no touch"
state.
Figure 11. Voltage Output Using GPO and Resistor Network
Figure 10. Host Interrupt Line with CSx Buttons Touched
Separately
R0
CS0
Sensor
Activated
Sensor
Deactivated
CS1
CS2
CS4
CS6
■
The host interrupt pin has the open-drain low-drive mode.
■
This pin is powered by VDDIO in CY8CMBR3108. This allows
communication with a host processor at voltage levels lower
than the chip VDD.
■
Only one pin can be configured as the host interrupt on devices
that have a host interrupt functionality on multiple pins.
Document Number: 001-85330 Rev. *G
GPO1
CS3
CS5
CS6
CS7
THI
CS1
CS4
CS5
HI
GPO0
CS2
CS3
CSx
CS0
CS7
R1
CY8CMBR3xxx
Buzzer ON Tim e
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
R
R2
R3
VOUT
R4
R5
R6
R7
The output analog voltage can be calculated based on the
following equation:
Here, Rn represents the series resistor value of any given GPO.
Page 15 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Note If more than one button is activated at the same time, the
Rn becomes equivalent (parallel) to all Rn resistors.
■
■
For the circuit represented in Figure 11 to work, GPOs should
be configured in the Active LOW logic, open-drain drive mode.
PWM must be disabled and the CSx-to-GPOx direct drive must
be enabled (that is, GPOs must be configured as
sensor-controlled).
The FSS feature can be enabled so only one button is reported
ON at a time.
System Diagnostics
System Diagnostics is a BIST feature that tests for faulty sensor,
shield, or CMOD conditions at device resets.
■
If any sensor fails these tests, a 50-ms pulse is sent out on the
corresponding GPO (that is, the pulse is observed on GPOx if
CSx fails the test), and the sensor is disabled.
■
If the shield fails the tests, a 50-ms pulse is sent out on all GPOs
and all the sensors are disabled.
■
If CMOD fails the tests, a 50-ms pulse is sent out on all GPOs
and all the sensors are disabled.
■
System Diagnostics failure pulses are sent within device
boot-up time.
■
The System Diagnostics status is also updated in the register
map. Therefore, the host can also read test results through the
I2C interface.
Document Number: 001-85330 Rev. *G
Sensor CP > 45 pF
If the parasitic capacitance of a sensor is more than 45 pF, the
sensor is disabled.
Improper value of CMOD
If the value of CMOD is less than 1 nF or greater than 4 nF, all
sensors are disabled (the recommended value of CMOD is
2.2 nF).
Sensor shorts
System Diagnostics also checks for the following errors:
■
Sensor shorted to Vss
■
Sensor shorted to VDD
■
Sensor shorted to another sensor
■
Sensor shorted to shield
Page 16 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Example Application Schematics
Figure 12. Example Schematics Demonstrating Four Buttons and Four GPOs
CS3
560E
R3
1
CS1
560E
R5
2
CMOD
3
VCC
4
I2C_SDA
330E
560E
14
13
CS1/PS1
CS7/GPO3/SH
CMOD
CS6/GPO2
VCC
CS5/GPO1
8
VDD
VSS
7
VDD_IO
C1
0.1uF
C2
1uF
C6
0.1uF
CS3
I2C_SCL
CS2/GUARD
5
2.2nF
CS0/PS0
6
C3
C4
0.1uF
12
R4
560E
11
D4
R9
1K
10
D1
R6
1K
9
D2
R7
1K
CS2
VDD
CS4/GPO0
CS0
I2C_SDA
HI
330E
HI/BUZ
U1
16
I2C HEADER
15
I2C_SCL
I2C_SDA
C5
1uF
VDD
R10
R1
VDD
1
2
3
4
5
R2
(TO HOST)
J1
I2C_SCL
VDDIO
CY8CMBR3108(16-QFN)
VDDIO
D3
VDD
R8
1K
In Figure 12[5, 6], the CY8CMBR3108 device is configured in the
following manner:
■
CS0–CS3: CapSense buttons
❐ All CapSense pins must have a 560-ohm series resistance
(placed close to the chip) for improved noise immunity.
■
GPO0–GPO3: To external LEDs
❐ LEDs are connected in sinking mode because the
CY8MBR3xxx devices have high sink current capability.
❐ Series resistances are connected to limit the GPO current to
be with IIL limits.
■
CMOD pin: 2.2 nF to ground
■
VCC pin: 0.1 µF to ground
VDD
■
VDD pin: To external supply voltage
❐ 1-µF and 0.1-µF decoupling capacitors connected to VDD
■
VDDIO pin: To supply voltage, which is ≤ VDD
2
❐ VDDIO powers I C and HI lines.
❐ 1-µF and 0.1-µF decoupling capacitors connected to VDDIO.
■
■
I2C_SCL and I2C_SDA pins: 330 ohms to the I2C header
2
2
❐ For I C communication: It is assumed that the I C line pull-up
resistors are present on the host side outside the I2C header.
HI pin: To host
2
❐ To prompt the host to initiate an I C transaction for reading
the changed sensor status.
Notes
5. VCC should be connected to VDD for 1.71 V ≤ VDD ≤ 1.89 V.
6. Proper ground layout is important for better SNR performance. Refer to the CY8CMBR3xxx CapSense Design Guide and Getting started with CapSense guide for all
layout guidelines.
Document Number: 001-85330 Rev. *G
Page 17 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
CS4
Figure 13. Example Schematics Demonstrating Multiple Sensor Types
I2C_SCL
I2C_SDA
330E
I2C_SCL
I2C_SDA
330E
XRES
VDD
BUZZER
CSS1
VDD
SLD10
VDD
I2C HEADER
R18
R3
SLD11
HI
1
2
3
4
5
(TO HOST)
J1
C1
C4
1uF
0.1uF
SLD12
C3
0.1uF
100E
19
CS5/SH/BUZ
560E
R2
21
20
CS4
R1
22
23
SLD14
7
C2
2.2nF
VCC
VDD
18
R5
560E
SLD24
17
R7
560E
SLD23
16
R9
560E
SLD22
15
R11
560E
SLD21
14
R12
560E
SLD20
13
R13
560E
SLD14
SLD13
6
CS10/SLD20
12
VCC
CMOD
560E
5
CS9/SLD21
SLD12
CMOD
CS3
11
4
560E
R10
I2C_SCL
560E
CS8/SLD22
SLD11
CS3
CS6/SLD24
CS2
SLD10
3
9
R8
CapSense Linear Slider 5 Seg
CS7/SLD23
10
560E
SLD14
CS1/PS1
560E
CS2
CS0/PS0
560E
2
VSS
1
R6
VDD
R4
560E
8
560E
CS1
I2C_SDA
XRES
PSO
HI/BUZ
U1
24
SLD13
SLD20
SLD21
CY8CMBR3106S(24-QFN)
R15
R14
R16
R17
SLD10
SLD11
SLD12
SLD13
SLD22
SLD23
SLD24
CapSense Radial slider 5-Seg
In Figure 13[7, 9], the CY8CMBR3106S device is configured in
the following manner:
■
PS0: CapSense proximity sensor
■
CS1–CS4: CapSense buttons[8]
■
CMOD pin: 2.2 nF to ground
■
VCC pin: 0.1 uF to ground
■
VDD pin: To external supply voltage
❐ 1-µF and 0.1-µF decoupling capacitors connected to VDD
■
SLD10-SLD14: CapSense linear slider segments
■
SLD20-SLD24: CapSense radial slider segments
■
BUZ: To buzzer
❐
❐
■
AC buzzer (1-pin).
Buzzer second pin to ground.
I2C_SCL and I2C_SDA pins: 330 ohm to the I2C header. It is
assumed that the I2C line pull-up resistors are present on the
host side outside the I2C header.
❐ For I2C communication.
■
HI pin: To host
2
❐ To prompt the host to initiate an I C transaction for reading
the changed sensor status.
■
XRES pin: Floating
❐ For external reset.
Notes
7. VCC should be shorted to VDD for 1.71 V ≤ VDD ≤ 1.89 V.
8. All CapSense pins have 560-ohm series resistance (placed close to the chip) for improved noise immunity.
9. Proper ground layout is important for better SNR performance. Refer to the CY8CMBR3xxx CapSense Design Guide and Getting started with CapSense guide for
all layout guidelines.
Document Number: 001-85330 Rev. *G
Page 18 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Power Supply Information
■
The CY8CMBR3xxx family of controllers contains three supply
domains: VDD, VCC, and VDDIO.
■
■
■
■
VDD: This is the primary supply to the chip and can be powered
from 1.8 V ±5% or 1.8 to 5.5 V. The CapSense controller is
powered by the VDD supply, and all the I/O signal levels (except
I2C lines, HI, and XRES) are referenced with respect to the VDD
supply. For packages and MPNs that do not have VDDIO, the
I2C SDA, I2C SCL, HI, and XRES signal levels are also referenced with respect to the VDD supply.
Note: If EZ-Click is used to configure the device, it automatically
takes care of the required register settings based on the voltage
settings selected in EZ-Click.
VDDIO: This is the supply input for I2C SDA, I2C SCL, HI, and
XRES lines. The signal levels of these I/Os are referenced with
respect to VDDIO. The VDDIO supply can be as low as 1.71 V
and as high as the voltage of the VDD supply. The VDDIO should
not be powered at a voltage higher than that of the VDD supply.
The VDDIO is available only on select packages. For a package
that does not have VDDIO, the I2C SDA, I2C SCL, HI, and XRES
signal levels are referenced with respect to the VDD supply.
VCC: This is the internal regulator output, which powers the
core and capacitive sensing circuits. A 0.1-µF, 5-V ceramic
capacitor should be connected close to the VCC pin for better
performance.
Power sequencing: The CY8CMBR3xxx device does not
require any power supply sequencing for the VDD and VDDIO
supplies. Either of these supplies can ramp earlier or later than
the other. The only requirement is that VDDIO should not be
greater than VDD.
1.8-V externally regulated operation: When VDD is powered
with a 1.8 V ±5% supply, the VCC and VDD pins should be
shorted externally and the SUPPLY_LOW_POWER bit in the
DEVICE_CFG3 register should be set to 1 through the I2C
interface (refer to the CY8CMBR3xxx Registers TRM for details
on the register). When the VCC and VDD pins are shorted, this
bypasses the internal voltage regulator. Under this condition,
make certain that VDD does not exceed 1.89 V.
The CY8CMBR3xxx family of controllers is factory-configured for
1.8-V to 5.5-V operation. To configure a factory-configured
device for 1.8-V externally regulated operation, you can use the
following procedure:
■
Short VDD and VCC.
■
Power the device at 1.8 V (note that regardless of the value of
the SUPPLY_LOW_POWER bit, the device can be powered at
1.8 V for configuring the device; only CapSense operation is
not guaranteed if the SUPPLY_LOW_POWER bit is not
properly configured)
■
Use EZ-Click to configure the device for 1.8-V operation.
■
Save and reset the device.
■
Ground consideration: Both the VSS pin and the metal pad
(E-pad) of the device should be connected to board ground.
Figure 14. Power Supply Connections for CY8CMBR3xxx CapSense Controllers[10]
Power supply connections when 1.8 < VDD < 5.5 V
Power supply connections* when 1.71 < VDD < 1.89 V
1.8 V to 5.5 V
VDD
0.1 μF
CY8CMBR3xxx
1.71 V to 1.89 V
VDD
0.1 μF
1 μF
VCC
VCC
1 μF
0.1 μF
1.71 V < VDDIO < VDD
1 μF
CY8CMBR3xxx
VDDIO
0.1 μF
1.71 V < VDDIO < VDD
1 μF
VSS
VDDIO
0.1 μF
VSS
*SUPPLY_LOW_POWER bit in DEVICE_CFG3 register should be set to 1
to operate device at 1.8V (±5%)
Note
10. Proper ground layout is important for best performance. Refer to the layout guidelines mentioned in the CY8CMBR3xxx CapSense Design Guide and Getting started
with CapSense guide.
Document Number: 001-85330 Rev. *G
Page 19 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings[11]
Parameter
Description
Conditions
Min
VDD_MAX Max voltage on the VDD pin relative to VSS –40 °C to +85 °C TA, absolute maximum –0.5
VDDIO_MAX Max voltage on the VDDIO pin relative to VSS –40 °C to +85 °C TA, absolute maximum
DC input voltage relative to VSS on I/O
Max
Units
–
6
V
0.5
–
6
V
–0.5
–
1.89
V
–40 °C to +85 °C TA, absolute maximum –0.5
–
VDD+0.5
V
2200
–
–
V
VCC_MAX Max voltage on the VCC pin relative to VSS Absolute maximum
VIO
Typ
ESD_HBM Electrostatic discharge, human body model Human body model ESD.
Electrostatic discharge, charged device
model
Charged device model ESD
500
–
–
V
ILU
Latch-up current limits
Maximum/minimum current to any input
or output, pin-to-pin or pin-to-supply
–140
–
140
mA
IIO
Current per GPIO
–
–
25
mA
Min
Typ
Max
Units
–40
25
85
°C
–40
–
100
°C
ESD_CDM
Operating Temperature
Table 10. Operating Temperature
Parameter
Description
TO
Operation temperature
TJ
Junction temperature
Conditions
Ambient temperature inside system
enclosure
DC Electrical Characteristics
DC Chip-Level Specifications
The specifications in Table 11 are valid under these conditions: –40 °C ≤ TA ≤ 85 °C. Typical values are specified at TA = 25 °C,
VDD = 3.3 V, and are for design guidance only.
Table 11. DC Chip-Level Specifications
Parameter
Description
VDD
Chip supply voltage
VDDIO
Supply voltage I/O
VDD_RIPPLE
Maximum allowed ripple on power
supply, DC to 10 MHz
Conditions/Details
VCC shorted to VDD
Min
1.71
Typ
1.8
Max
1.89
Units
V
VCC not shorted to VDD. VCC connected
to 0.1 µF decoupling capacitor
1.8
–
5.5
V
1.71 V < VDD < 1.89 V
1.71
–
VDD
V
1.8 V < VDD < 5.5 V
1.71
–
VDD
V
+25 °C TA, VDD > 2 V, sensitivity ≥ 0.1 pF
–
–
±50
mV
+25 °C TA, VDD > 1.75 V, CP < 20 pF,
sensitivity = 0.4 pF
–
–
±25
mV
CEFC
External regulator voltage bypass
X5R ceramic ±10% or better
(capacitor to be connected to the VCC pin)
–
0.1
–
µF
CEXC
Power supply decoupling capacitor on
VDD
–
1
–
µF
X5R ceramic or better
Note
11. Usage above the absolute maximum conditions listed in Table 9 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions, but above normal operating conditions, the device may not operate to specification.
Document Number: 001-85330 Rev. *G
Page 20 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
XRES DC Specifications
Table 12. XRES DC Specifications
Parameter
Description
Conditions/Details
Min
Typ
Max
Units
VIH_XRES
Input voltage high threshold on XRES pin CMOS input
0.7*VDD
–
–
V
VIL_XRES
Input voltage low threshold on XRES pin CMOS input
–
–
0.3*VDD
V
CIN_XRES
Input capacitance on XRES pin
–
–
7
pF
VDD ≤ 4.5 V
–
0.05*VDD
–
mV
VDD > 4.5 V
200
–
–
mV
VHYSXRES Input voltage hysteresis on XRES pin
DC I/O Port Specifications
The specifications in Table 13 are valid at –40 °C ≤ TA ≤ +85 °C. Typical parameters are specified at TA = 25 °C and are for design
guidance only.
Table 13. DC I/O Port Specifications
Parameter
Description
VOH
Output voltage HIGH level
VOL
Output voltage LOW level
CPIN
ITOT_GPIO
RPU
Pin capacitance
Conditions
Min
Typ
Max
Units
IOH = –4 mA at 3 V VDD
VDD–0.6
–
–
V
IOH = –1 mA at 1.8 V VDD
VDD–0.5
–
–
V
IOL = 4 mA at 1.8 V VDD
–
–
0.6
V
IOL = 10 mA at 3 V VDD
–
–
0.6
V
All VDD, all packages, all I/Os
–
3
7
pF
Maximum total sink chip current
+25 °C TA, All VDD
Pull-up resistor
–
–
85
mA
3.5
5.6
8.5
kΩ
AC Electrical Specifications
Table 14. AC Chip-Level Specifications
Parameter
Description
Conditions
TSR_POWER_UP Power supply slew rate during power-up –40 °C ≤ TA ≤ 85 °C, all VDD
Min
Typ
Max
Units
1
–
67
V/ms
Min
Typ
Max
Units
5
–
–
µs
XRES AC Specifications
Table 15. XRES AC Specifications
Parameter
TXRES
Description
External reset pulse width
Conditions/Details
–40 °C ≤ TA ≤ 85 °C, all VDD
Note
12. VIH must not exceed VDD + 0.2 V.
Document Number: 001-85330 Rev. *G
Page 21 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
I2C Specifications
Table 16. I2C Specifications
Parameter
Description
FSCLI2C_FM
I2 C
Conditions
Min
Typ
Max
Units
0
–
400
kHz
THDSTAI2C_FM
Hold time (repeated) START condition; after this
period, the first clock pulse is generated
0.6
–
–
µs
TSUSTAI2C_FM
SCL clock frequency
Setup time for a repeated START condition
0.6
–
–
µs
TLOWI2C_FM
LOW period of the SCL clock
1.3
–
–
µs
THIGHI2C_FM
HIGH period of the SCL clock
0.6
–
–
µs
µs
THDDATI2C
Data hold time
0
–
–
TSUDATI2C_FM
Data setup time
100
–
–
ns
TSUSTOI2C_FM
Setup time for I2C STOP condition
0.6
–
–
µs
CB_FM
Capacitive load for each I2C bus line
–
–
400
pF
TVDDATI2C_FM
Data valid time
–
–
0.9
µs
TVDACKI2C_FM
µs
Data valid acknowledge time
–
–
0.9
TSPI2C_FM
Pulse width of spikes suppressed by the input filter
–
–
50
ns
TBUFI2C_FM
Bus-free time between STOP and START condition
1.3
–
–
µs
VIL_I2C
Input LOW voltage
2-mA sink
–0.5
–
0.3 * VDD
V
VIH_I2C
Input HIGH Voltage
3-mA sink
0.7* VDD
–
–
V
Output LOW voltage, low supply range
VDD < 2 V, 3-mA sink
–
–
0.2 * VDD
V
Output LOW voltage, high supply range
VDD > 2 V, 3-mA sink
–
–
0.4
V
I2C output low current
Fast Mode, 1.71 V ≤ VDD ≤
5.5 V, load = CB_SM, VOL =
0.6 V
6
–
–
mA
I2C_VHYS_HV
I2C input hysteresis
Fast and standard mode I2C
speeds. 2 V ≤ VDD ≤ 4.5 V
0.05 * VDD
–
–
mV
I2C_VHYS_5V5
I2C input hysteresis
Fast and standard mode I2C
speeds. 4.5 V < VDD < 5.5 V
200
–
–
mV
I2C_VHYS_LV
I2C input hysteresis
Fast and standard mode I2C
speeds. VDD < 2 V
0.1 * VDD
–
–
mV
VOL_I2C_L
VOL_I2C_H
IOL_I2C_FM
Figure 15. I2C Bus Timing Diagram for Fast or Standard Modes
TBUFI2C
SDA
P
TSUSTAI2C
S
TLOWI2C
TSUDATI2C
TSUSTOI2C
S
SCL
THDSTAI2C
THIGHI2C
Document Number: 001-85330 Rev. *G
THDDATI2C
Page 22 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
System Specifications
The specifications in the following table are valid at TA = 25 °C and VDD = 5 V, unless otherwise specified.
Table 17. System Specifications
Parameter
Min
Typ
Max
Units
0.2-pF sensitivity, SNR 5:1
5
–
45
pF
Supported parasitic capacitance range of
0.1-pF sensitivity, SNR 5:1
sensors
12
–
35
pF
0.1-pF sensitivity, SNR 4:1
5
–
45
pF
5-V rating, X7R or NP0 Cap.
CP ≤ 45 pF
–
2.2
–
nF
IAVG_NT
VDD = 5 V, 3.3 V, 2.5 V, 1.8 V,
Average current per button with no finger CP = 10 pF, 2 buttons,
touch
Refresh interval = 120 ms, EMC
disabled, 0.4-pF sensitivity
–
–
22
μA
IAVG_WT
Average current with finger touch
VDD = 5 V, 3.3 V, 2.5 V, 1.8 V,
CP = 10 pF, 8 buttons,
Refresh interval =120 ms, EMC
disabled, 0.4-pF sensitivity
–
–
600
μA
Average current with EMC
VDD = 5 V, 3.3 V, 2.5 V, 1.8 V,
CP = 10 pF, 8 buttons,
Refresh interval =120 ms, EMC
enabled, 0.4-pF sensitivity
–
–
300
μA
Average current without EMC
VDD = 5 V, 3.3 V, 2.5 V, 1.8 V,
CP = 10 pF, 8 buttons,
Refresh interval = 120 ms, EMC
disabled
–
–
100
μA
Deep Sleep current with I2C on
VDD ≤ 3.3 V, TA = 25 °C, I2C Enabled
–
2.5
–
μA
TBOOT_SYS
Boot-up time (time from power-up to first
sensor scan) with system diagnostics
enabled and EMC disabled
16 buttons, CP ≤ 18 pF
–
–
900
ms
TBOOT_WF
Boot-up time (time from power-up to first
sensor scan) with no system diagnostics
and EMC enabled
10 buttons, CP ≤ 18 pF
–
–
850
ms
TBOOT
Boot-up time (time from power-up to first
sensor scan) with no system diagnostics
and EMC disabled
16 buttons, CP ≤ 18 pF
–
–
400
ms
Boot-up time (time from power-up to first
TBOOT_SYS_WF sensor scan) with both system
diagnostics and EMC enabled.
10 buttons, CP ≤ 18 pF
–
–
1350
ms
–
–
15
ms
–
–
50
ms
CP
CMOD
IAVG_WF
IAVG_NF
IDS
Description
Value for CMOD external capacitor
Boot up time (time from power to I2C
ready)
Time between I2C command and
TI2C_LATENCY_ execution (for all commands except the
MAX
"Save"[13] command)
TI2CBOOT
Conditions/Details
Note
13. Save command takes 220 ms to execute.
Document Number: 001-85330 Rev. *G
Page 23 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Table 17. System Specifications (continued)
Parameter
Description
Conditions/Details
Min
Typ
Max
Units
THI
Host interrupt pulse width
5 V, 1.8 V
200
–
700
μs
FBUZ_4
Buzzer output frequency
5 V, 1.8 V
–
4.00
–
kHz
FBUZ_2.67
Buzzer output frequency
5 V, 1.8 V
–
2.67
–
kHz
FBUZ_2
Buzzer output frequency
5 V, 1.8 V
–
2.00
–
kHz
FBUZ_1.60
Buzzer output frequency
5 V, 1.8 V
–
1.60
–
kHz
FBUZ_1.33
Buzzer output frequency
5 V, 1.8 V
–
1.33
–
kHz
FBUZ_1.143
Buzzer output frequency
5 V, 1.8 V
–
1.14
–
kHz
FBUZ_1
Buzzer output frequency
5 V, 1.8 V
–
1.00
–
kHz
FPWM
GPO PWM frequency
5 V, 1.8 V
–
106.7
–
Hz
TSNS_RST5
Sensor auto-reset interval 5 sec
5 V, 1.8 V
–
5
–
sec
TSNS_RST20
Sensor auto-reset interval 20 sec
5 V, 1.8 V
–
20
–
sec
Pulse width on GPOx when the
corresponding CSx fails the system
diagnostics test
–
50
–
ms
Maximum CP supported for shield
electrode
–
–
100
pF
TFAULTY_SNS_P
ULSE
CP_SHIELD
Document Number: 001-85330 Rev. *G
Page 24 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Power Consumption and Operational States
The CY8CMBR3xxx family of controllers is designed with
multiple low-power operational states to meet the low-power
requirements of battery-powered applications. These controllers
have the following operational states (see Figure 16):
1. Boot: The devices load the last-known configuration data and
run system diagnostics tests.
2. Active: The sensors are scanned at a speed set by the refresh
interval to determine the presence of touch, proximity, or
finger position on a slider, and any configured outputs (GPOs,
buzzer, and HI) are driven. The refresh interval can be
configured from 20 ms to 500 ms in steps of 20 ms, either
using the EZ-Click tool or by configuring the register.
3. Look-for-Touch: All the sensors are scanned at a much
slower, user-configured refresh interval, and any enabled
GPOs (such as PWM or DC Toggle) are driven.
4. Look-for-Proximity: Only proximity sensors enabled for
wake-on approach are scanned. No outputs are driven in this
state.
5. Deep Sleep: No sensors are scanned, and the
CY8CMBR3xxx devices are in a low-power state with no
processing. The GPO status is reset to the default value in the
Deep Sleep mode.
6. Configuration: No scanning or reporting occurs and the
devices wait for a reset for the configuration settings to take
effect.
The CY8CMBR3xxx controllers automatically manage
transitions between four operational states (Boot, Active,
Look-for-Touch, and Look-for-Proximity). The host can force
transition in and out of the Deep Sleep state. A host command
can alter the configuration data, causing a transition to the
Configuration state. A transition can also occur automatically
after boot.
controllers enter the Look-for-Touch state, in which they scan all
sensors at a slow, user-configured refresh interval. If a touch is
present, the controllers either enter or remain in the Active state,
in which they update the sensor status and drive the corresponding outputs. A transition from Active to Look-for-Touch
occurs when no touch is detected and the buzzer is not driven.
Similarly, a transition from Look-for-Touch to Look-for-Proximity
occurs when no proximity is detected.
The following parameters configure the operational states:
■
State timeout (Register STATE_TIMEOUT) defines the
following:
❐ Minimum time (in seconds) of no touch activity in the Active
state
❐ Minimum time to trigger a transition to the Look-for-Touch
state
❐ Minimum time of no touch activity in the Look-for-Touch state
❐ Minimum time to trigger a transition to the Look-for-Proximity
state
■
Refresh Interval (Register REFRESH_CTRL) defines the
minimum time between the start of subsequent scans in the
Look for Touch and Look-for-Proximity states.
■
The Refresh Interval for the Active state is fixed at 20 ms.
During all three states—Active, Look-for-Touch, and
Look-for-Proximity—the devices enter standby mode after
scanning and processing the requisite sensors. This helps to
maintain the lowest power consumption within any refresh
interval.
The following guidelines result in the lowest operating current:
■
Ground all unused CapSense inputs (CSx)
■
Minimize CP
■
Reduce CSx button sensitivity
The Active state emphasizes a high refresh rate (that is, low
refresh interval) for fast responses to button touches and
proximity events. The Look-for-Touch state enables low power
consumption during periods of no-touch activity.
■
Configure the design to be optimized for power consumption
■
Avoid using a high noise immunity level in a low-noise
environment
The Look-for-Proximity state allows ultra-low power
consumption when a human body is not in close proximity. This
state is entered only if the wake-on-approach feature is enabled
(and the toggle is disabled). In this state, the CY8CMBR3xxx
controllers periodically scan proximity sensors to determine the
presence of a human body. If they detect human presence, the
■
Use a higher Button Scan Rate or Deep Sleep operating mode
Document Number: 001-85330 Rev. *G
Page 25 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Figure 16. CY8CMBR3xxx Operational States and Transitions
Deep Sleep
(S)
SLEEP Command
SLEEP Command
SLEEP Command
I2C Address Match
No Touch
No Touch
Reset
Boot
(B)
Active
(A)
Look-for-Touch
(T)
Touch Detected
Configuration Corrupted
I2C Commands
I2C Commands
Proximity
Detected
Look-for-Proximity
(P)
I2C Commands
Configuration
(C)
Reset
Document Number: 001-85330 Rev. *G
Page 26 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Response Time
Host Communication Protocol
Response time for button and proximity sensors is the minimum
amount of time for which the sensor must be active/inactive
(touched or proximity present), for the device to detect it as a
valid activation or deactivation event.
The CY8CMBR3xxx CapSense controllers communicate to the
host through the I2C interface. I2C is a simple two-wire
synchronous communication protocol that uses the following two
lines:
For the CY8CMBR3xxx device family, response time numbers
for different sensors can be estimated using the design toolbox.
The following response time numbers are provided in the
toolbox:
■
RFBT: This value represents the response time for first button
touch when the device is in the Look-for-Touch or
Look-for-Proximity operational states.
■
RCBT: This value represents the response time for consecutive
button touches when the device is in the Active operational
state.
■
RFST: This value represents the response time for the first slider
touch when the device is in the Look-for-touch operational
state.
■
RCST: This value represents the response time for consecutive
slider touches when the device is in the Active operational state.
■
RBSR: This value represents the response time for button and
slider release events when the device is in the Active operational state.
■
RProx: This value represents the response time for detecting
valid proximity events on a proximity sensor.
■
RProx_release: This value represents the response time for
proximity release events on a proximity sensor.
■
Serial Clock (SCL) –This line is used to synchronize the slave
with the master.
■
Serial Data (SDA) – This line is used to send data between the
master and the slave.
The CY8CMBR3xxx I2C interface has the following features:
■
Bit rate of 400 kbps
■
Configurable I2C slave address (7-bit)
■
No bus-stalling or clock-stretching during transactions
■
Register-based access to the I2C master for reads and writes
■
Repeated START support
The CY8CMBR3xxx CapSense controllers can be part of a
single-slave or a multi-slave environment.
Figure 17. I2C Communication Between One Master
and One Slave
VDD
CY8CMBR3xxx Resets
The CY8CMBR3xxx family of CapSense controllers has three
reset options – two hardware resets and one software reset.
■
Hardware Resets
❐ Power reset –Toggling the power on the VDD pin of the
CapSense controller resets the controller.
❐ XRES reset – Pull the device XRES pin LOW for TXRES duration and then pull it HIGH.
■
Software Reset
To reset the software, write one SW_RESET command to the
command register. All three resets are functionally equivalent,
and the CapSense controllers enter the Boot state (refer to the
Power Consumption and Operational States section) after any
reset.
Document Number: 001-85330 Rev. *G
VDD VDD
HI
HOST
CY8CMBR3xxx
SCL
SDA
I2C Slave Address
To identify each device on the I2C bus, a unique 7-bit I2C slave
address is used. When the master wants to communicate with a
slave on the bus, it sends a START condition followed by the
appropriate I2C address. The START condition alerts all slaves
on the bus when a new transaction starts. The slave with the
specified I2C address acknowledges the master. All the other
slaves ignore further traffic on the bus until the next START
condition is detected.
Page 27 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
I2C Communication Guidelines
Write Operation
1. After device reset, the host should wait for TI2CBOOT time
before initiating any I2C communication. The CY8CMBR3xxx
CapSense controller family will generate a NACK if the host
tries to communicate before this period.
2. The CY8CMBR3xxx controller is expected to NACK the
address match event if it is in the standby mode (during any
of the operational states – Deep Sleep, Look-for-Touch,
Look-for-Proximity, or Active). The controller wakes up from
the standby mode on an address match but sends NACK until
it transitions into the Active state. When the device NACKs a
transaction the host is expected to retry the transaction until
it receives an ACK.
3. If there is a delay of more than 340 ms between two subsequent bytes within an I2C transaction, the device may go into
standby mode and the host may get a NACK.
4. When the host sends the SAVE_CHECK_CRC command, the
device will send a NACK on any subsequent I2C transactions
until the command execution is completed. The time taken to
complete the SAVE_CHECK_CRC command is 220 ms typ.
5. The host must not write to read-only registers. All write operations directed to such read-only registers are ignored.
A host performs the following steps during a write operation:
1. The host sends the START condition.
2. The host specifies the slave address, followed by the
read/write bit to specify a write operation.
3. The device may NACK the host.
4. The host sends a Repeat Start (or a stop followed by a start
condition), followed by the address and read/write bit, to
specify a write operation. The host keeps sending the Repeat
Start with the address and read/write bits until the device
sends an ACK. The device ACKs the host.
5. The host specifies the register address to which it has to write.
6. The device ACKs the host.
7. The host starts sending the data to the device, which is written
to the register address specified by the host. This is followed
by an ACK from the device.
8. If the write operation includes more bytes, each one is written
to the successive register address. Each successive byte is
followed by an ACK from the device.
9. After the write operation is complete, the host sends the STOP
condition to the device. This marks the end of the communication (see Figure 18).
Figure 18. Host Writing x Bytes to the Device
Slave
Address
Slave
Address
`
`
S
Register
Address (n)
AAAAAAA R
N
65 43 210W
NS
Data[n]
Data[n+1]
Data[n+x]
A A A A A A A R R R R R R R R R D D D D D D D D D D D D D D D D DD D D D D D D
AP
A
A
A
A
6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 76 5 4 3 2 1 0
Stop
ACK
ACK
ACK
The host sets the device data pointer to specify the starting point
for future read operations. Setting the device data pointer
involves the following steps:
1. The host sends the START condition.
2. The host specifies the slave address, followed by the
read/write bit to specify a write operation.
3. The device may NACK the host.
ACK
ACK
Write
Start
NACK
Start
NACK
Start
Setting the Device Data Pointer
4. The host sends a Repeat Start, followed by the address and
read/write bit, to specify a write operation. The host keeps
sending the repeat start with the address and read/write bit
until the device sends an ACK.
5. The device ACKs the host.
6. The host specifies the register address. Any further read
operation will take place from this address.
7. The host sends the STOP condition (see Figure 19).
Figure 19. Host Setting the Device Data Pointer
Slave
Address
S
`
`
AAAAAAA R
N
6 5 4 3 2 1 0W
Stop
ACK
ACK
Write
Start
NACK
Start
NACK
Start
Document Number: 001-85330 Rev. *G
Slave
Register
Address
pointer
AAAAAAA R R R R R R RRR
N S
A
AP
6 5 4 3 2 1 0W 7 6 5 4 3 2 10
Page 28 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Read Operation
The host performs the following steps for a read operation:
1. The host sends the START condition.
2. The host specifies the slave address, followed by the
read/write bit to specify a write operation.
3. The device may NACK the host.
4. The host sends a repeat start followed by the address and
read/write bit to specify a write operation. The host keeps
sending the repeat start with the address and read/write bits
until the device sends an ACK.
5. The device ACKs the host.
6. The device retrieves the byte from the pre-specified register
address and sends it to the host. The host ACKs the device.
7. Each successive byte is retrieved from the successive
register address and sent to the host, followed by ACKs from
the host.
8. After the host receives the required bytes, it NACKs the
device.
9. The host sends the STOP condition to the device. This marks
the end of the communication (see Figure 20).
Figure 20. Host Reading x Bytes from the Device
Slave
Address
S
Slave
Address
`
AAAAAAA R
N
6 5 4 3 2 1 0W
NS
Data[n]
Data[n+2]
Data[n+1]
Data[n+x]
`
A A A A A A A R D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D
NP
A
A
A
A
6 5 4 3 2 1 0W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 76 5 4 3 2 1 0
Stop
NACK
ACK
ACK
ACK
ACK
Read
Start
NACK
Start
NACK
Start
Legend:
CY8CMBR3xxx to Host
HOST to CY8CMBR3xxx
Document Number: 001-85330 Rev. *G
Page 29 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Layout Guidelines and Best Practices
Cypress provides an extensive set of design guidelines for CapSense board designs. Refer to the CY8CMBR3xxx CapSense Design
Guide for complete system guidelines.
Ordering Information
The CY8CMBR3xxx family consists of six parts that vary depending on the parameters. The following table lists all the parts and a
summary of the features supported.
Table 18. Ordering Information
Ordering Code
Package
Type
Operating
Total
CapSense
Temperature Capacitive Buttons
Sensing
Inputs
Sliders
Proximity
Sensors
GPOs
Shield
Communication
Interface
CY8CMBR3116-LQXI
24-pin QFN
Industrial
Up to 16
Up to 16
0
Up to 2
Up to 8
1
I2C / GPO
CY8CMBR3106S-LQXI
24-pin QFN
Industrial
Up to 16
Up to 11
Up to 2
Up to 2
0
1
I 2C
CY8CMBR3110-SX2I
16-pin SOIC
Industrial
Up to 10
Up to 10
0
Up to 2
Up to 5
1
I2C / GPO
CY8CMBR3108-LQXI
16-pin QFN
Industrial
Up to 8
Up to 8
0
Up to 2
Up to 4 + HI
1
I2C / GPO
CY8CMBR3102-SX1I
8-pin SOIC
Industrial
Up to 2
Up to 2
0
Up to 2
Up to 1
1
I2C/GPO
CY8CMBR3002-SX1I
8-pin SOIC
Industrial
2
2
0
0
2
0
GPO
Document Number: 001-85330 Rev. *G
Page 30 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Packaging Dimensions
Figure 21. 24-Pin QFN (Sawn) 4 × 4 × 0.55 mm
001-13937 *E
Document Number: 001-85330 Rev. *G
Page 31 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Figure 22. 16-Pin QFN 3 × 3 × 0.6 mm
001-87187 **
Figure 23. 16-Pin SOIC (150 mil)
51-85068 *E
Document Number: 001-85330 Rev. *G
Page 32 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Figure 24. 8-Pin SOIC (150 mil)
51-85066 *F
Thermal Impedances
Table 19. Thermal Impedances
Package
Typical θJA (°C/W)
8-pin SOIC
127 °C/W
16-pin SOIC
80 °C/W
16-pin QFN
33 °C/W
24-pin QFN
21 °C/W
Solder Reflow Specifications
Table 20 illustrates the minimum solder reflow peak temperature to achieve good solderability.
Table 20. Solder Reflow Specifications
Package
Maximum Peak Temperature
Time at Maximum Temperature
8-pin SOIC
260 °C
30 s
16-pin SOIC
260 °C
30 s
16-pin QFN
260 °C
30 s
24-pin QFN
260 °C
30 s
Document Number: 001-85330 Rev. *G
Page 33 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Appendix
Units of Measure
Table 21. Units of Measure
Symbol
Units of Measure
°C
degrees Celsius
fF
femtofarad
Hz
hertz
kbps
kilobits per second
kHz
kilohertz
kΩ
kilo ohm
MHz
megahertz
µA
microampere
µF
microfarad
µs
microsecond
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
Ω
ohm
pp
peak-to-peak
pF
picofarad
s
second
V
volt
Document Number: 001-85330 Rev. *G
Page 34 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Glossary
CP
Parasitic capacitance.
EZ-Click
The customizer tool (GUI) that enables easy register configurability and debugging for the
CY8CMBR3xxx family of controllers.
GPO
General Purpose Output – that is, an output pin on a chip that the user can configure.
FSS
Flanking Sensor Suppression. An algorithm that distinguishes between signals from closely spaced
buttons, eliminating false touches. It ensures that the system recognizes only the first button touched.
SmartSense
Cypress CapSense algorithm that continuously compensates for system, manufacturing, and
environmental changes.
SNR
A ratio of the sensor signal, when touched, to the noise signal of an untouched sensor.
Toggle
An MBR device feature that toggles the state of GPOs on every sensor activation.
Open-Drain Low-Drive
mode
An output pin drive mode wherein logic 0 is represented by a low voltage (that is, Voltage < VOL), whereas
logic 1 is represented by floating the output line to a HIGH impedance state.
Strong Drive mode
An output pin drive mode where logic 0 is represented by a low voltage (that is, Voltage < VOL), whereas
logic 1 is represented by a high voltage (that is, Voltage V > VOH).
Raw counts
A count value representing a digital count equivalent of sensed capacitance.
Baseline
A filtered version of the raw counts. The baseline essentially tracks the value of the parasitic capacitance
in the system but does not track the value of the finger capacitance.
Parasitic capacitance
The intrinsic capacitance of PC board traces to sensors.
Finger capacitance
Additional capacitance introduced on a CapSense sensor when a finger approaches/touches the sensor.
Global setting
A setting value that is common for all elements of a set.
Active LOW signal
A signal that indicates the active state by logic 0 and the inactive state by logic 1 values.
Active HIGH signal
A signal that indicates the active state by logic 1 and the inactive state by logic 0 values.
Reference Documents
Document Title
Description
CapSense CY8CMBR3xxx Design Guide
Provides design guidance for using capacitive touch sensing (CapSense) functionality with the CY8CMBR3xxx family of CapSense controllers.
Getting Started with CapSense®
Provides a starting point for anyone who is new to capacitive touch sensing
(CapSense) and for anyone learning key design considerations and layout best
practices.
Design Toolbox
Includes four sections – General Layout Guidelines for a CapSense PCB, a layout
estimator for estimating button dimensions, a power consumption calculator (based
on button dimensions), and the Design Validation tool to validate the layout design.
EZ-Click User Guide
Gives instructions on how to install and uninstall the EZ-Click Customizer tool and
describes how to set up the boards. It also includes detailed descriptions of all the
tabs in the GUI.
CY8CMBR3xxx Programming Specifications
Gives the information necessary to program the nonvolatile memory of the
CY8CMBR3xxx devices. It describes the communication protocol required for
access by an external programmer, explains the programming algorithm, and gives
electrical specifications of the physical connection.
CapSense® Express™ Controllers Registers Lists and details all registers of CY8CMBR3102, CY8CMBR3106S,
TRM
CY8CMBR3108, CY8CMBR3110, and CY8CMBR3116 CapSense® Express™
controllers. All registers are listed in the order of address.
Document Number: 001-85330 Rev. *G
Page 35 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Document History Page
Document Title: CY8CMBR3002, CY8CMBR3102, CY8CMBR3106S, CY8CMBR3108, CY8CMBR3110, CY8CMBR3116
CapSense® Express™ Controllers with SmartSense™ Auto-tuning 16 Buttons, 2 Sliders, Proximity Sensors
Document Number: 001-85330
Revision
ECN
Orig. of
Change
*G
4359354
DCHE
Submission
Date
Description of Change
05/06/2014 Updated links to the following web pages: EZ-Click, Cypress online store, and
MBR3 Evaluation Kit.
Changed time at max temperature from 20 seconds to 30 seconds.
Document Number: 001-85330 Rev. *G
Page 36 of 37
CY8CMBR3002, CY8CMBR3102
CY8CMBR3106S, CY8CMBR3108
CY8CMBR3110, CY8CMBR3116 Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2013-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-85330 Rev. *G
Revised May 6, 2014
Page 37 of 37
PSoC® and CapSense® are registered trademarks and PSoC Designer™, SmartSense™, EZ-Click™, CapSense Express™, and Programmable System-on-Chip™ are trademarks and of Cypress
Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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