CY8C40xx
PSoC™ 4 MCU: PS oC™ 4000S
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4000S product family is a member of the PSoC™ 4 platform
architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a
capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4000S products
are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 32 KB of flash with read accelerator
- Up to 4 KB of SRAM
• Programmable analog
- Single-slope 10-bit ADC function provided by Capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5 µA digital system current
• Capacitive sensing
- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 programmable GPIO pins
- 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 32-kHz watch crystal oscillator (WCO)
- ±2% internal main oscillator (IMO)
- 32-kHz internal low-power oscillator (ILO)
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital
automatic routing
- Application programming interface (API) components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................3
1 Development ecosystem .................................................................................................................4
1.1 PSoC™ 4 MCU resources .........................................................................................................................................4
1.2 ModusToolbox™ software ......................................................................................................................................5
1.3 PSoC™ Creator ........................................................................................................................................................6
Block diagram...................................................................................................................................7
2 Functional description ....................................................................................................................9
3 Functional definition.....................................................................................................................10
3.1 CPU and memory subsystem ...............................................................................................................................10
3.2 System resources..................................................................................................................................................10
3.3 Analog blocks ........................................................................................................................................................12
3.4 Programmable digital blocks ...............................................................................................................................12
3.5 Fixed function digital ............................................................................................................................................13
3.6 GPIO.......................................................................................................................................................................14
3.7 Special function peripherals ................................................................................................................................14
4 Pinouts ........................................................................................................................................15
4.1 Alternate pin functions .........................................................................................................................................17
5 Power ..........................................................................................................................................19
5.1 Mode 1: 1.8 V to 5.5 V external supply ..................................................................................................................19
5.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................20
6 Electrical specifications.................................................................................................................21
6.1 Absolute maximum ratings ..................................................................................................................................21
6.2 Device level specifications....................................................................................................................................22
6.3 Analog peripherals................................................................................................................................................27
6.4 Digital peripherals.................................................................................................................................................32
6.5 Memory..................................................................................................................................................................36
6.6 System resources..................................................................................................................................................37
7 Ordering information ....................................................................................................................41
8 Packaging ....................................................................................................................................43
8.1 Package diagrams.................................................................................................................................................44
9 Acronyms .....................................................................................................................................49
10 Document conventions................................................................................................................53
10.1 Units of measure .................................................................................................................................................53
Revision history ..............................................................................................................................54
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1
Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.cypress.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ Portfolio, PSoC™ Roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
- AN79953: Getting Started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software or PSoC™ Creator.
- AN91184: PSoC™ 4 BLE - Designing BLE Applications
- AN88619: PSoC™ 4 hardware design considerations
- AN73854: Introduction To bootloaders
- AN89610: Arm® Cortex® code optimization
- AN86233: PSoC™ 4 MCU power reduction techniques
- AN57821: Mixed signal circuit board layout
- AN85951: PSoC™ 4, PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub
repositories.
• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU
non-volatile memory.
• Development tools
- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™
3, PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture
and over 150 pre-verified, production-ready peripheral components.
- CY8CKIT-145-40XX PSoC™ 4000S CAPSENSE™ prototyping kit, is a low-cost and easy-to-use evaluation
platform. This kit provides easy access to all the device I/Os in a breadboard-compatible format.
- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also
available.
• Training Videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.
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Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon’ comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub, including:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox™ software, and AN79953: Getting Started with PSoC™ 4.
Figure 1
Datasheet
ModusToolbox™ software tools
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Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems
concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Co-design your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
6. Prototype your solution with the PSoC™ 4 Pioneer kits. If a design change is needed, PSoC™ Creator and
components enable you to make changes on-the-fly without the need for hardware revisions.
1
2
3
4
5
Figure 2
Datasheet
Multiple-sensor example project in PSoC™ Creator
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
SPCIF
Cortex® M0+
48 MHz
FLASH
32 KB
SRAM
4 KB
ROM
8 KB
FAST MUL
NVIC, IRQMUX
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
Test
TestMode Entry
Digital DFT
Analog DFT
WCO
Reset
Reset Control
XRES
Peripheral Interconnect (MMIO)
PCLK
2x LP Comparator
Clock
Clock Control
WDT
ILO
IMO
Peripherals
IO S S G PIO (5x ports)
Power
Sleep Control
WIC
POR
REF
PWRSYS
System Interconnect (Single Layer AHB)
2x S C B-I2 C/S PI/UA R T
AHB-Lite
SWD/TC
CAPSENSE ™ (v2)
32-bit
CPU Subsystem
5x T C P W M
PSoC™ 4000S
Architecture
High Speed I/O Matrix & 2 x Programmable I/O
Power Modes
Active/Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S provides a level
of security not possible with multi-chip application solutions or with microcontrollers.
It has the following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
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Based on Arm® Cortex®-M0+ CPU
Block diagram
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
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Based on Arm® Cortex®-M0+ CPU
Functional description
2
Functional description
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S family provides
a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following
advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3
Functional definition
3.1
CPU and memory subsystem
3.1.1
CPU
The Cortex®-M0+ CPU in the PSoC™ 4000S is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of
the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt
inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep
mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.
The debug configuration used for PSoC™ 4000S has four breakpoint (address) comparators and two watchpoint
(data) comparators.
3.1.2
Flash
The PSoC™ 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
3.1.3
SRAM
Four KB of SRAM are provided with zero wait-state access at 48 MHz.
3.1.4
SROM
A supervisory ROM that contains boot and configuration routines is provided.
3.2
System resources
3.2.1
Power system
The power system is described in detail in the section “Power” on page 19. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out
detection). The PSoC™ 4000S operates with a single external supply over the range of either 1.8 V ±5% (externally
regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which
are managed by the power system. The PSoC™ 4000S provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs.
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Functional definition
3.2.2
Clock system
The PSoC™ 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In addition, the clock system ensures that there are
no metastable conditions.
The clock system for the PSoC™ 4000S consists of the internal main oscillator (IMO), internal low-frequency
oscillator (ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are
provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to
enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.
There are eight clock dividers for the PSoC™ 4000S, two of those are fractional dividers. The 16-bit capability
allows flexible generation of fine-grained frequency values, and is fully supported in PSoC™ Creator.
HFCLK
IMO
Divide By
2,4,8
External Clock
LFCLK
ILO
Prescaler
SYSCLK
HFCLK
Integer
Dividers
Fractional
Dividers
6X 16-bit
2X 16.5-bit
Figure 3
PSoC™ 4000S MCU clocking architecture
3.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4000S. It is trimmed during testing to achieve the
specified accuracy. The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2%.
3.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
3.2.5
Watch crystal oscillator (WCO)
The PSoC™ 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can
be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator. The
WCO on PSoC™ 4000S series devices does not connect to the LFCLK or WDT. Due to this, RTC functionality is not
supported.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
3.2.6
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause Register, which is firmware readable.
3.2.7
Reset
The PSoC™ 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous
and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset
and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it
active low. The XRES pin has an internal pull-up resistor that is always enabled.
3.2.8
Voltage reference
The PSoC™ 4000S reference system generates all internally required references. A 1.2-V voltage reference is
provided for the comparator. The IDACs are based on a ±5% reference.
3.3
Analog blocks
3.3.1
Low-power comparators (LPC)
The PSoC™ 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
3.3.2
Current DACs
The PSoC™ 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
3.3.3
Analog multiplexed buses
The PSoC™ 4000S has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal
resources (IDACs, comparator) to connect to any pin on the I/O Ports.
3.4
Programmable digital blocks
The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows boolean functions to be
performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on
input pins to the chip and on signals going out as outputs.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
3.5
Fixed function digital
3.5.1
Timer/Counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4000S.
3.5.2
Serial communication block (SCB)
The PSoC™ 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of the PSoC™ 4000S and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
The PSoC™ 4000S is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
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Functional definition
3.6
GPIO
The PSoC™ 4000S has up to 36 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for ports 2 and 3). During
power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4000S).
3.7
Special function peripherals
3.7.1
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4000S through a CAPSENSE™ Sigma-Delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield
capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit slope ADC function, which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.
3.7.2
LCD segment drive
The PSoC™ 4000S has an LCD controller, which can drive up to 8 commons and up to 28 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays.
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Based on Arm® Cortex®-M0+ CPU
Pinouts
4
Pinouts
The following table provides the pin list for PSoC™ 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN,
24-pin QFN, 32-pin TQFP, and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the
48-TQFP.
Table 1
PSoC™ 4000S pin list
48-pin TQFP
32-pin QFN
24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
28
P0.0
17
P0.0
13
P0.0
D1
P0.0
22
P0.0
17
P0.0
29
P0.1
18
P0.1
14
P0.1
C3
P0.1
23
P0.1
18
P0.1
30
P0.2
19
P0.2
24
P0.2
19
P0.2
31
P0.3
20
P0.3
25
P0.3
20
P0.3
32
P0.4
21
P0.4
15
P0.4
C2
P0.4
26
P0.4
21
P0.4
33
P0.5
22
P0.5
16
P0.5
C1
P0.5
27
P0.5
22
P0.5
34
P0.6
23
P0.6
17
P0.6
B1
P0.6
28
P0.6
23
P0.6
35
P0.7
B2
P0.7
29
P0.7
36
XRES
24
XRES
18
XRES
B3
XRES
30
XRES
24
XRES
37
VCCD
25
VCCD
19
VCCD
A1
VCCD
31
VCCD
25
VCCD
38
VSSD
26
VSSD
20
VSSD
A2
VSS
26
VSSD
39
VDDD
27
VDD
21
VDD
A3
VDD
32
VDDD
27
VDD
40
VDDA
27
VDD
21
VDD
A3
VDD
33
VDDA
27
VDD
41
VSSA
28
VSSA
22
VSSA
A2
VSS
34
VSSA
28
VSSA
42
P1.0
29
P1.0
35
P1.0
29
P1.0
43
P1.1
30
P1.1
36
P1.1
30
P1.1
44
P1.2
31
P1.2
23
P1.2
A4
P1.2
37
P1.2
31
P1.2
45
P1.3
32
P1.3
24
P1.3
B4
P1.3
38
P1.3
32
P1.3
46
P1.4
39
P1.4
47
P1.5
48
P1.6
1
P1.7
1
P1.7
1
P1.7
A5
P1.7
40
P1.7
1
P1.7
2
P2.0
2
P2.0
2
P2.0
B5
P2.0
1
P2.0
2
P2.0
3
P2.1
3
P2.1
3
P2.1
C5
P2.1
2
P2.1
3
P2.1
4
P2.2
4
P2.2
3
P2.2
4
P2.2
5
P2.3
5
P2.3
4
P2.3
5
P2.3
6
P2.4
5
P2.4
7
P2.5
6
P2.5
6
P2.5
6
P2.5
8
P2.6
7
P2.6
4
P2.6
D5
P2.6
7
P2.6
7
P2.6
9
P2.7
8
P2.7
5
P2.7
C4
P2.7
8
P2.7
8
P2.7
10
VSSD
A2
VSS
9
VSSD
12
P3.0
9
P3.0
E5
P3.0
10
P3.0
9
P3.0
13
P3.1
10
P3.1
D4
P3.1
11
P3.1
10
P3.1
Datasheet
6
P3.0
15
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2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
PSoC™ 4000S pin list (continued)
48-pin TQFP
32-pin QFN
24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
14
P3.2
11
P3.2
7
P3.2
E4
P3.2
12
P3.2
11
P3.2
16
P3.3
12
P3.3
8
P3.3
D3
P3.3
13
P3.3
12
P3.3
17
P3.4
14
P3.4
18
P3.5
15
P3.5
19
P3.6
16
P3.6
20
P3.7
17
P3.7
21
VDDD
22
P4.0
13
P4.0
9
P4.0
E3
P4.0
18
P4.0
13
P4.0
23
P4.1
14
P4.1
10
P4.1
D2
P4.1
19
P4.1
14
P4.1
24
P4.2
15
P4.2
11
P4.2
E2
P4.2
20
P4.2
15
P4.2
25
P4.3
16
P4.3
12
P4.3
E1
P4.3
21
P4.3
16
P4.3
Note: Pins 11, 15, 26, and 27 are No connects (NC) on the 48-pin TQFP.
Descriptions of the pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Datasheet
16
002-00123 Rev. *P
2023-01-23
Table 2
Pin assignments
Port/Pin
Analog
P0.0
lpcomp.in_p[0]
Smart I/O
Alternate Function 1
Alternate Function 2 Alternate Function 3
tcpwm.tr_in[0]
Deep Sleep 1
scb[0].spi_select1:0
Deep Sleep 2
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
P0.3
lpcomp.in_n[1]
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
scb[0].spi_select3:0
P0.6
srss.ext_clk
P0.7
scb[1].uart_cts:0
scb[1].spi_clk:1
scb[1].uart_rts:0
scb[1].spi_select0:1
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[0].spi_clk:1
P1.3
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[0].spi_select0:1
17
P1.0
P1.4
scb[0].spi_select1:1
P1.5
scb[0].spi_select2:1
P1.6
scb[0].spi_select3:1
P1.7
002-00123 Rev. *P
2023-01-23
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
P2.1
prgio[0].io[1]
tcpwm.line_compl[4]:0
P2.2
prgio[0].io[2]
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
scb[1].spi_clk:2
P2.3
prgio[0].io[3]
scb[1].spi_select0:2
PSoC™ 4 MCU: PSoC™ 4000S
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CAPSENSE™
pin. The pin assignments are shown in the following table.
Based on Arm® Cortex®-M0+ CPU
Alternate pin functions
Pinouts
Datasheet
4.1
Analog
Alternate Function 1
prgio[0].io[4]
tcpwm.line[0]:1
Alternate Function 2 Alternate Function 3
Deep Sleep 1
scb[1].spi_select1:1
Deep Sleep 2
P2.5
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
prgio[0].io[6]
tcpwm.line[1]:1
scb[1].spi_select3:1
P2.7
prgio[0].io[7]
tcpwm.line_compl[1]:1
P3.0
prgio[1].io[0]
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
prgio[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
P3.4
prgio[1].io[4]
tcpwm.line[2]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
P3.5
prgio[1].io[5]
tcpwm.line_compl[2]:0
tcpwm.tr_in[7]
scb[1].spi_select2:0
P3.6
prgio[1].io[6]
tcpwm.line[3]:0
tcpwm.tr_in[8]
scb[1].spi_select3:0
P3.7
prgio[1].io[7]
tcpwm.line_compl[3]:0
tcpwm.tr_in[9]
lpcomp.comp[1]:1
lpcomp.comp[0]:1
18
P4.0
csd.vref_ext
scb[0].uart_rx:0
tcpwm.tr_in[10]
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
tcpwm.tr_in[11]
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
PSoC™ 4 MCU: PSoC™ 4000S
Smart I/O
P2.4
Based on Arm® Cortex®-M0+ CPU
Port/Pin
Pin assignments (continued)
Pinouts
Datasheet
Table 2
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5
Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4000S.
The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog
circuits run directly from the VDD input.
VDDA
VDDD
VDDA
VSSA
VDDD
Analog
Domain
Digital
Domain
VSSD
1.8 Volt
Regulator
Figure 4
VCCD
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ± 5% (externally regulated; 1.71 V
to 1.89 V, internal regulator bypassed).
5.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that can be anywhere in the range of
1.8 V to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered
from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the
PSoC™ 4000S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to
anything else.
Datasheet
19
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2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5.2
Mode 2: 1.8 V ± 5% external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that must be within the range of 1.71 V to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in the following diagram.
Power supply bypass connections example
1.8V to 5.5V
VDD
PSoCTM 4000S
1.8V to 5.5V
VDDA
1 mF
0.1mF
0.1mF
VCCD
0.1mF
VSS
Figure 5
Datasheet
External supply range from 1.8 V to 5.5 V with internal regulator active
20
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2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6
Electrical specifications
6.1
Absolute maximum ratings
Table 3
Absolute maximum ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID1
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage
input relative to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD + 0.5
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
–
SID5
GPIO injection current,
IGPIO_injection Max for VIH > VDDD, and
Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge
human body model
2200
–
–
BID45
ESD_CDM
Electrostatic discharge
charged device model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
V
mA
–
Current injected
per pin
–
V
–
mA
–
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but
above normal operating conditions, the device may not operate to specification.
Datasheet
21
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2
Device level specifications
All specifications are valid for –40°C TA 105°C and TJ 125°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/conditions
Internally regulated
supply
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage
(VCCD = VDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage
(for core logic)
–
1.8
–
–
SID55
CEFC
External regulator voltage
bypass
–
0.1
–
X5R ceramic or better
SID56
CEXC
Power supply bypass
capacitor
–
1
–
V
Internally unregulated
supply
µF
X5R ceramic or better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
IDD5
Execute from flash;
CPU at 6 MHz
–
1.2
2.0
SID16
IDD8
Execute from flash;
CPU at 24 MHz
–
2.4
4.0
SID19
IDD11
Execute from flash;
CPU at 48 MHz
–
4.6
5.9
1.1
1.6
–
mA
–
–
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
I2C wakeup WDT, and
comparators on
–
IDD20
I2C wakeup, WDT, and
comparators on
–
6 MHz
mA
1.4
1.9
12 MHz
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
–
0.7
0.9
mA
6 MHz
SID28A
IDD23A
I2C wakeup, WDT, and
Comparators on
–
0.9
1.1
mA
12 MHz
–
2.5
60
µA
–
–
2.5
60
µA
–
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
60
µA
–
Supply current while XRES
asserted
–
2
5
mA
–
XRES Current
SID307
Datasheet
IDD_XR
22
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 5
Spec ID
SID48
SID49[2]
AC specifications
Parameter
Description
Min
Typ
Max
Units Details/conditions
DC
–
48
MHz 1.71 V VDD 5.5 V
FCPU
CPU frequency
TSLEEP
Wakeup from Sleep mode
–
0
–
Wakeup from Deep Sleep
mode
–
35
–
SID50[2] TDEEPSLEEP
–
µs
–
Note
2. Guaranteed by characterization.
Datasheet
23
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2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.1
GPIO
Table 6
GPIO DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID57
VIH[3]
Input voltage high
threshold
0.7 VDDD
–
–
CMOS input
SID58
VIL
Input voltage low
threshold
–
–
0.3 VDDD
CMOS input
SID241
VIH[3]
LVTTL input,
VDDD < 2.7 V
0.7 VDDD
–
–
–
SID242
VIL
LVTTL input,
VDDD < 2.7 V
–
–
0.3 VDDD
–
SID243
VIH[3]
LVTTL input,
VDDD 2.7 V
2.0
–
–
–
SID244
VIL
LVTTL input,
VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high
level
VDDD – 0.6
–
–
IOH = 4 mA
at 3 V VDDD
SID60
VOH
Output voltage high
level
VDDD – 0.5
–
–
IOH = 1 mA
at 3 V VDDD
SID61
VOL
Output voltage low
level
–
–
0.6
IOL = 4 mA
at 1.8 V VDDD
SID62
VOL
Output voltage low
level
–
–
0.6
IOL = 10 mA
at 3 V VDDD
SID62A
VOL
Output voltage low
level
–
–
0.4
IOL = 3 mA
at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current
(absolute value)
–
–
2
nA
25°C, VDDD = 3.0 V
SID66
CIN
Input capacitance
–
–
7
pF
–
VHYSTTL
Input hysteresis LVTTL
25
40
–
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
200
–
–
SID67[4]
SID68[4]
SID68A[4]
VHYSCMOS5V5 Input hysteresis CMOS
V
kΩ
–
–
–
VDDD 2.7 V
mV
VDD < 4.5 V
VDD > 4.5 V
SID69[4]
IDIODE
Current through
protection diode to
VDD/VSS
–
–
100
µA
–
SID69A[4]
ITOT_GPIO
Maximum total source
or sink chip current
–
–
200
mA
–
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
24
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2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC Specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
–
12
3.3 V VDDD,
Cload = 25 pF
TRISEF
Rise time in fast strong
mode
2
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong
mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong
mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT;
3.3 V VDDD 5.5 V;
fast strong mode
–
–
33
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT;
1.71 VVDDD3.3 V;
fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT;
3.3 V VDDD 5.5 V;
slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT;
1.71 V VDDD 3.3 V;
slow strong mode
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
SID70
Datasheet
ns
25
MHz
3.3 V VDDD,
Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.2
XRES
Table 8
XRES DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID77
VIH
Input voltage high threshold 0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 × VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5] VHYSXRES
Input voltage hysteresis
–
100
–
mV
Typical hysteresis
is 200 mV for
VDD > 4.5 V
SID82
Current through protection
diode to VDD/VSS
–
–
100
µA
–
Min
Typ
Max
TRESETWIDTH Reset pulse width
1
–
–
µs
–
TRESETWAKE
–
–
2.7
ms
–
Table 9
Spec ID
SID83[5]
BID194[5]
IDIODE
V
CMOS Input
XRES AC specifications
Parameter
Description
Wake-up time from reset
release
Units Details/conditions
Note
5. Guaranteed by characterization.
Datasheet
26
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3
Analog peripherals
6.3.1
Comparator
Table 10
Comparator DC specifications
Spec ID
SID84
VOFFSET1
Description
Input offset voltage, factory
trim
SID85
VOFFSET2
Input offset voltage, custom
trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode
voltage in normal mode
0
–
VDDD – 0.1
SID247
VICM2
Input common mode
voltage in low power mode
0
–
VDDD
SID247A VICM3
Input common mode
voltage in ultra low power
mode
0
–
VDDD – 1.15
SID88
CMRR
Common mode rejection
ratio
50
–
–
SID88A
CMRR
Common mode rejection
ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power
mode
–
–
100
SID259
ICMP3
Block current in ultra
low-power mode
–
6
28
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
Min
Typ
Max
–
38
110
Table 11
Spec ID
SID91
Parameter
Min
Typ
Max
–
–
±10
–
mV
–
–
Modes 1 and 2
V
–
VDDD ≥ 2.2 V at
–40°C
dB
VDDD ≥ 2.7V
VDDD ≤ 2.7V
–
µA
–
VDDD ≥ 2.2 V at
–40°C
MΩ
–
Comparator AC specifications
Parameter
TRESP1
Description
Response time, normal
mode, 50 mV overdrive
Units Details/conditions
–
ns
SID258
TRESP2
Response time, low power
mode, 50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low
power mode, 200 mV
overdrive
–
2.3
15
Datasheet
Units Details/conditions
27
–
µs
VDDD ≥ 2.2 V at
–40°C
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.2
CSD and IDAC
Table 12
CSD and IDAC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Max allowed ripple
on power supply,
DC to 10 MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25°C TA,
Sensitivity = 0.1 pF
mV
VDD > 1.75 V (with
ripple), 25°C TA,
Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SYS.PER#3
VDD_RIPPLE
SYS.PER#16
Max allowed ripple
VDD_RIPPLE_1.8 on power supply,
DC to 10 MHz
–
–
±25
Details/conditions
SID.CSD.BLK ICSD
Maximum block
current
–
–
4000
µA
Maximum block current
for both IDACs in
dynamic (switching)
mode including
comparators, buffer,
and reference
generator.
SID.CSD#15
Voltage reference
for CSD and
comparator
0.6
1.2
VDDA – 0.6
V
VDDA – 0.6 or 4.4 V,
whichever is lower
SID.CSD#15A VREF_EXT
External Voltage
reference for CSD
and comparator
0.6
–
VDDA – 0.6
V
VDDA – 0.6 or 4.4 V,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block
current
–
–
1750
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block
current
–
–
1750
µA
–
SID308
VCSD
Voltage range of
operation
1.71
–
5.5
V
1.8 V ± 5% or 1.8 V to
5.5 V
SID308A
VCOMPIDAC
Voltage
compliance range
of IDAC
0.6
–
VDDA – 0.6
V
VDDA – 0.6 or 4.4 V,
whichever is lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB –
SID310
IDAC1INL
INL
–2
–
2
LSB
SID311
IDAC2DNL
DNL
–1
–
1
LSB –
SID312
IDAC2INL
INL
–2
–
2
LSB INL is ±5.5 LSB for
VDDA < 2 V
SID313
SNR
Ratio of counts of
finger to noise.
Guaranteed by
characterization
Capacitance range of
5 pF to 35 pF, 0.1-pF
Ratio
sensitivity. All use cases.
VDDA > 2 V.
SID314
IDAC1CRT1
SID314A
IDAC1CRT2
Datasheet
VREF
INL is ±5.5 LSB for
VDDA < 2 V
5
–
–
Output current of
IDAC1 (7 bits) in low
range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
Output current of
IDAC1 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
28
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
CSD and IDAC specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/conditions
275
–
330
µA
LSB = 2.4-µA typ.
SID314B
IDAC1CRT3
Output current of
IDAC1 (7 bits) in
high range
SID314C
IDAC1CRT12
Output current of
IDAC1 (7 bits) in low
range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
IDAC1CRT22
Output current of
IDAC1 (7 bits) in
medium range, 2X
mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of
IDAC1 (7 bits) in
high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of
IDAC2 (7 bits) in low
range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of
IDAC2 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of
IDAC2 (7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of
IDAC2 (7 bits) in low
range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
IDAC2CRT22
Output current of
IDAC2 (7 bits) in
medium range, 2X
mode
69
–
82
µA
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of
IDAC2 (7 bits) in
high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315F
IDAC3CRT13
Output current of
IDAC in 8-bit mode
in low range
8
–
10.5
µA
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of
IDAC in 8-bit mode
in medium range
69
–
82
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of
IDAC in 8-bit mode
in high range
540
–
660
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
SID321
IDACGAIN
Full-scale error less
offset
–
–
±10
SID322
Mismatch between
IDACMISMATCH1 IDAC1 and IDAC2 in
Low mode
–
–
9.2
SID314D
SID315D
Datasheet
29
Polarity set by Source or
LSB Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
%
–
LSB LSB = 37.5-nA typ.
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
CSD and IDAC specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID322A
Mismatch between
IDACMISMATCH2 IDAC1 and IDAC2 in
Medium mode
–
–
5.6
LSB LSB = 300-nA typ.
SID322B
Mismatch between
IDACMISMATCH3 IDAC1 and IDAC2 in
High mode
–
–
6.8
LSB LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to
0.5 LSB for
8-bit IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID324
IDACSET7
Settling time to
0.5 LSB for
7-bit IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID325
CMOD
External modulator
capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0
cap.
Datasheet
30
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.3
10-bit CAPSENSE™ ADC
Table 13
10-bit CAPSENSE™ ADC specifications
Spec ID
Parameter
Description
Min
Typ
Max
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
SIDA98
A_GAINERR
Gain error
–
–
±2
Units Details/conditions
Auto-zeroing is
bits required every
millisecond
Defined by AMUX
Bus.
Yes
–
%
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
–
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
–
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
–
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
A_CONV8
Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
µs
Does not include
acquisition time.
Equivalent to
44.8 ksps including
acquisition time.
A_CONV10
Conversion time for 10-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
µs
Does not include
acquisition time.
Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and
Distortion ratio (SINAD)
–
61
–
dB
With 10-Hz input
sine wave, external
2.4-V reference,
VREF (2.4 V) mode
SIDA110
A_BW
Input bandwidth without
aliasing
–
–
22.4
SIDA111
A_INL
Integral Non Linearity.
1 ksps
–
–
2
LSB
SIDA112
A_DNL
Differential Non Linearity.
1 ksps
–
–
1
LSB –
SIDA108
SIDA108A
Datasheet
31
–
–
–
–
21.3
85.3
kHz 8-bit resolution
VREF = 2.4 V or
greater
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4
6.4.1
Digital peripherals
Timer counter pulse-width modulator (TCPWM)
Table 14
Spec ID
TCPWM specifications
Parameter
Description
Block current
SID.TCPWM.1 ITCPWM1
consumption at 3 MHz
Block current
SID.TCPWM.2 ITCPWM2
consumption at 12 MHz
Block current
SID.TCPWM.2A ITCPWM3
consumption at 48 MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse
width
Min
Typ
Max
Units Details/conditions
–
–
45
–
–
155
–
–
650
All modes (TCPWM)
–
–
Fc
MHz Fc max = CLK_SYS
Maximum = 48 MHz
2/Fc
–
–
For all trigger
events[6]
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
All modes (TCPWM)
µA
All modes (TCPWM)
Output trigger pulse
widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse
width of PWM
Output
SID.TCPWM.5C QRES
Quadrature inputs
resolution
–
Minimum pulse
width between
Quadrature phase
inputs
SID.TCPWM.5
TPWMEXT
1/Fc
–
ns
Minimum time
between
successive counts
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Datasheet
32
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.2
I2C
Table 15
Fixed I2C DC specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID149
II2C1
Block current consumption
at 100 kHz
–
–
50
SID150
II2C2
Block current consumption
at 400 kHz
–
–
135
SID151
II2C3
Block current consumption
at 1 Mbps
–
–
310
–
SID152
II2C4
I2C enabled in Deep Sleep
mode
–
–
1.4
–
Min
Typ
Max
–
–
1
SID153
–
µA
Fixed I2C AC specifications[7]
Table 16
Spec ID
–
Parameter
FI2C1
Description
Bit rate
Units Details/conditions
Msps –
Note
7. Guaranteed by characterization.
Datasheet
33
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.3
SPI
Table 17
SPI DC specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current consumption
at 1 Mbps
–
–
360
SID164
ISPI2
Block current consumption
at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption
at 8 Mbps
–
–
600
Table 18
Spec ID
SID166
Units Details/conditions
–
µA
–
–
SPI AC specifications[7]
Parameter
FSPI
Description
Min Typ
SPI operating frequency
(Master; 6X Oversampling)
Max
Units Details/conditions
–
–
8
MHz –
–
Fixed SPI Master Mode AC specifications
SID167
TDMO
MOSI valid after SClock
driving edge
–
–
15
SID168
TDSI
MISO valid before SClock
capturing edge
20
–
–
SID169
THMO
Previous MOSI data hold
time
0
–
–
Referred to Slave
capturing edge
–
ns
Full clock, late
MISO sampling
Fixed SPI Slave Mode AC specifications
SID170
TDMI
MOSI valid before Sclock
capturing edge
40
–
–
SID171
TDSO
MISO valid after Sclock
driving edge
–
–
42 + (3 × Tcpu)
SID171A
TDSO_EXT
MISO valid after Sclock
driving edge in External
Clock mode
–
–
48
–
SID172
THSO
Previous MISO data hold
time
0
–
–
–
SID172A
TSSELSSCK
SSEL valid to first SCK valid
edge
100
–
–
Datasheet
TCPU = 1/FCPU
ns
34
ns
–
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.4
UART
Table 19
UART DC specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID160
IUART1
Block current consumption
at 100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption
at 1000 Kbps
–
–
312
µA
–
Min
Typ
Max
–
–
1
Min
Typ
Max
UART AC specifications[8]
Table 20
Spec ID
SID162
Parameter
FUART
Description
Bit rate
6.4.5
LCD direct drive
Table 21
LCD direct drive DC specifications[8]
Spec ID
Parameter
Description
Units Details/conditions
Mbps –
Units Details/conditions
SID154
ILCDLOW
Operating current in low
power mode
–
5
–
µA
16 × 4 small
segment disp.
at 50 Hz
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID156
LCDOFFSET
Long-term segment offset
–
20
–
mV
–
SID157
ILCDOP1
LCD system operating
current Vbias = 5 V
–
2
–
mA
32 × 4 segments.
50 Hz. 25°C
SID158
ILCDOP2
LCD system operating
current Vbias = 3.3 V
–
2
–
Min
Typ
Max
10
50
150
LCD direct drive AC specifications[8]
Table 22
Spec ID
SID159
32 × 4 segments.
50 Hz. 25°C
Parameter
FLCD
Description
LCD frame rate
Units Details/conditions
Hz
–
Note
8. Guaranteed by characterization.
Datasheet
35
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.5
Memory
6.5.1
Flash
Table 23
Flash DC specifications
Spec ID
SID173
Parameter
VPE
Table 24
Description
Min
Typ
Max
Erase and program voltage
1.71
–
5.5
Min
Typ
Max
Units Details/conditions
V
–
Flash AC specifications
Spec ID
Parameter
Description
Units
Details/conditions
SID174
TROWWRITE[9]
Row (block) write
time (erase and
program)
–
–
20
SID175
TROWERASE[9]
Row erase time
–
–
16
SID176
TROWPROGRAM[9]
Row program time
after erase
–
–
4
–
SID178
TBULKERASE[9]
Bulk erase time
(32 KB)
–
–
35
–
SID180[10]
TDEVPROG[9]
Total device
program time
–
–
7
Seconds –
SID181[10]
FEND
Flash endurance
100 K
–
–
SID182[10]
FRET
Flash retention.
TA 55°C,
100 K P/E cycles.
20
–
–
SID182A[10]
–
Flash retention.
TA 85°C,
10 K P/E cycles.
10
–
–
SID182B[10]
FRETQ
Flash retention.
TA ≤ 105°C,
10 K P/E cycles,
≤ three years
at TA ≥ 85 °C.
10
–
20
Guaranteed by
Characterization
SID256
TWS48
Number of Wait
states at 48 MHz
2
–
–
CPU execution
from Flash
SID257
TWS24
Number of Wait
states at 24 MHz
1
–
–
CPU execution
from Flash
Row (block) =
128 bytes
ms
Cycles
–
–
–
Years
–
Notes
9. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or Flash operations may be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
10.Guaranteed by characterization.
Datasheet
36
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6
System resources
6.6.1
Power-on reset (POR)
Table 25
Power-on reset (PRES)
Spec ID
Description
Min
Typ
Max
SID.CLK#6 SR_POWER_UP
Power supply slew rate
1
–
67
SID185[10] VRISEIPOR
Rising trip voltage
0.80
–
1.5
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
–
1.62
SID186[10]
Table 26
Spec ID
Parameter
Parameter
Description
BOD trip voltage in active
and sleep modes
1.48
SID192[10] VFALLDPSLP
BOD trip voltage in Deep
Sleep
1.11
–
–
–
Typ
Max
3.3 V VDD 5.5 V
–
–
14
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
–
SWD interface specifications
F_SWDCLK1
–
V
Min
Table 27
Parameter
Units Details/conditions
1.5
SWD interface
Description
Units Details/conditions
MHz
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
SID215[13]
T_SWDI_SETUP
T = 1/f SWDCLK
0.25 × T
–
–
SID216[13]
T_SWDI_HOLD
T = 1/f SWDCLK
0.25 × T
–
–
SID217[13]
T_SWDO_VALID
T = 1/f SWDCLK
–
–
0.5 × T
SID217A[13]
T_SWDO_HOLD
T = 1/f SWDCLK
1
–
–
Datasheet
V
At power-up and
power-down
–
6.6.2
SID213
V/ms
Brown-out detect (BOD) for VCCD
SID190[10] VFALLPPOR
Spec ID
Units Details/conditions
37
ns
SWDCLK ≤ 1/3 CPU
clock frequency
–
–
–
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.3
Internal main oscillator (IMO)
Table 28
IMO DC specifications
(Guaranteed by design)
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID218
IIMO1
IMO operating current
at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current
at 24 MHz
–
–
180
µA
–
Min
Typ
Max
SID223[12]
–
–
±2.0
SID223A[11, 12]
–
–
±2.5
–
–
±2.0
SID223C[11, 12]
–
–
±1.5
SID223D[11, 12]
–
–
±1.25
–
–
–
145
7
–
Table 29
Spec ID
SID223B[11, 12]
SID226
SID228
IMO AC specifications
Parameter
FIMOTOL1
TSTARTIMO
TJITRMSIMO2
Description
Frequency variation at
24, 32, and 48 MHz
(trimmed)
IMO startup time
RMS jitter at 24 MHz
Units Details/conditions
At –40°C to 85°C, for
industrial
temperature range
%
and original
extended industrial
range parts
At –40°C to 105°C,
for all extended
% industrial
temperature range
parts
At –30°C to 105°C,
for enhanced IMO
% extended industrial
temperature range
parts
At –20°C to 105°C,
for enhanced IMO
% extended industrial
temperature range
parts
At 0°C to 85°C, for
enhanced IMO
% extended industrial
temperature range
parts
µs –
ps –
Notes
11.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details
on how to identify enhanced IMO extended temperature range parts, please refer to KBA235887.
12.Evaluated by characterization. Does not take into account soldering or board-level effects.
Datasheet
38
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.4
Internal low-speed oscillator (ILO)
Table 30
ILO DC specifications
(Guaranteed by design)
Spec ID
Parameter
[13]
Description
SID231
IILO1
Table 31
ILO AC specifications
Spec ID
ILO operating current
Parameter
[13]
SID234
Description
Min
Typ
Max
–
0.3
1.05
Min
Typ
Max
Units Details/conditions
µA
–
Units Details/conditions
TSTARTILO1
ILO startup time
–
–
2
ms
–
SID236
TILODUTY
ILO duty cycle
40
50
60
%
–
SID237
FILOTRIM1
ILO frequency range
20
40
80
6.6.5
Watch crystal oscillator (WCO)
Table 32
Watch crystal oscillator (WCO) specifications
Min
Typ
Max
[13]
Spec ID
Parameter
Description
kHz –
Units Details/conditions
SID398
FWCO
Crystal frequency
–
32.768
–
SID399
FTOL
Frequency tolerance
–
50
250
ppm
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal load capacitance
6
–
12.5
pF
–
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating current (high
power mode)
–
–
8
µA
–
SID406
IWCO2
Operating current (low
power mode)
–
–
1
µA
–
6.6.6
External clock
Table 33
External clock specifications
Spec ID
Parameter
Description
Min
Typ
Max
SID305[15] ExtClkFreq
External clock input
frequency
0
–
48
SID306[15] ExtClkDuty
Duty cycle; measured at
VDD/2
45
–
55
kHz –
With 20-ppm
crystal
Units Details/conditions
MHz –
%
–
Notes
13.Guaranteed by characterization.
14.For industrial temperature range parts, the maximum temperature is 85°C.
Datasheet
39
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.7
Clock
Table 34
Clock specs
Spec ID
Parameter
SID262[15] TCLKSWITCH
Description
System clock source
switching time
Min
Typ
Max
3
–
4
6.6.8
Smart I/O Pass-through Time
Table 35
Smart I/O pass-through time (Delay in Bypass Mode)
Spec ID
SID252
Parameter
PRG_BYPASS
Description
Max delay added by Smart
I/O in Bypass Mode
Units
Details/conditions
Periods –
Min
Typ
Max
–
–
1.6
Units Details/conditions
ns
–
Note
15.Guaranteed by characterization.
Datasheet
40
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
7
Ordering information
The PSoC™ 4000S part numbers and features are listed in the following table.
PSoC™ 4000S ordering information
4024
4025
4045
Datasheet
WLCSP (0.35-mm pitch)
24-pin QFN
32-pin QFN
32-pin TQFP
40-pin QFN
48-pin TQFP
2
8
21
✔
–
–
–
–
–
5
2
8
19
–
✔
–
–
–
–
CY8C4024LQI-S402
24
16
2
0
0
1
0
2
5
2
16
27
–
–
✔
–
–
–
CY8C4024AXI-S402
24
16
2
0
0
1
0
2
5
2
16
27
–
–
–
✔
–
–
Smart I/Os
5
2
SCB Blocks
2
0
TCPWM Blocks
0
1
LP Comparators
1
0
12-bit SAR ADC
0
0
10-bit CSD ADC
0
2
CAPSENSE™
2
16
Opamp (CTBm)
16
24
SRAM (KB)
24
CY8C4024LQI-S401
Flash (KB)
CY8C4024FNI-S402
MPN
Max CPU speed (MHz)
Category
Package
GPIO
Features
CY8C4024LQI-S403
24
16
2
0
0
1
0
2
5
2
16
34
–
–
–
–
✔
CY8C4024AZI-S403
24
16
2
0
0
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4024FNI-S412
24
16
2
0
1
1
0
2
5
2
8
21
✔
–
–
–
–
–
–
CY8C4024LQI-S411
24
16
2
0
1
1
0
2
5
2
8
19
–
✔
–
–
–
CY8C4024LQI-S412
24
16
2
0
1
1
0
2
5
2
16
27
–
–
✔
–
–
–
CY8C4024AXI-S412
24
16
2
0
1
1
0
2
5
2
16
27
–
–
–
✔
–
–
CY8C4024LQI-S413
24
16
2
0
1
1
0
2
5
2
16
34
–
–
–
–
✔
–
CY8C4024AZI-S413
24
16
2
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4024AZQ-S413
24
16
2
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4025FNI-S402
24
32
4
0
0
1
0
2
5
2
8
21
✔
–
–
–
–
–
CY8C4025LQI-S401
24
32
4
0
0
1
0
2
5
2
8
19
–
✔
–
–
–
–
CY8C4025LQI-S402
24
32
4
0
0
1
0
2
5
2
16
27
–
–
✔
–
–
–
CY8C4025AXI-S402
24
32
4
0
0
1
0
2
5
2
16
27
–
–
–
✔
–
–
CY8C4025LQI-S403
24
32
4
0
0
1
0
2
5
2
16
34
–
–
–
–
✔
–
CY8C4025AZI-S403
24
32
4
0
0
1
0
2
5
2
16
36
–
–
–
–
–
✔
24
32
4
0
0
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4025FNI-S412
24
32
4
0
1
1
0
2
5
2
8
21
✔
–
–
–
–
–
CY8C4025LQI-S411
24
32
4
0
1
1
0
2
5
2
8
19
–
✔
–
–
–
–
CY8C4025LQI-S412
24
32
4
0
1
1
0
2
5
2
16
27
–
–
✔
–
–
–
CY8C4025AXI-S412
24
32
4
0
1
1
0
2
5
2
16
27
–
–
–
✔
–
–
CY8C4025LQI-S413
24
32
4
0
1
1
0
2
5
2
16
34
–
–
–
–
✔
–
CY8C4025AZI-S413
24
32
4
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4025AZQ-S413
24
32
4
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4045FNI-S412
48
32
4
0
1
1
0
2
5
2
8
21
✔
–
–
–
–
–
48
32
4
0
1
1
0
2
5
2
8
19
–
✔
–
–
–
–
CY8C4045LQI-S412
48
32
4
0
1
1
0
2
5
2
16
27
–
–
✔
–
–
–
CY8C4045AXI-S412
48
32
4
0
1
1
0
2
5
2
16
27
–
–
–
✔
–
–
–40°C to 105°C
–40°C to 105°C
–40°C to 85°C
–40°C to 105°C
–40°C to 85°C
CY8C4045LQI-S413
48
32
4
0
1
1
0
2
5
2
16
34
–
–
–
–
✔
–
CY8C4045AZI-S413
48
32
4
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
CY8C4045AZQ-S413
48
32
4
0
1
1
0
2
5
2
16
36
–
–
–
–
–
✔
41
–40°C to 85°C
–40°C to 85°C
CY8C4025AZQ-S403
CY8C4045LQI-S411
Temperature range
Table 36
–40°C to 105°C
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
Description
Values
Meaning
Prefix
4
Architecture
4
PSoC™ 4
A
Family
0
4000 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
C
DE
F
S
XYZ
Flash Capacity
Package Code
Temperature Range
Series Designator
Attributes Code
I
Industrial
Q
Extended Industrial
S
PSoC™ 4 S-Series
M
PSoC™ 4 M-Series
L
PSoC™ 4 L-Series
BL
PSoC™ 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
Example
CY8C 4 A B C DE F – S XYZ
Cypress Prefix
4: PSoC 4
1:
4100
Family
2:
4200Family
Family
0: 4000
4: 48 MHz
Architecture
Family within Architecture
CPU Speed
5: 32 KB
Flash Capacity
AZ: TQFP
AX:
TQFP
Package Code
I: Industrial
Temperature Range
Silicon Family
Attributes Code
Datasheet
42
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
8
Packaging
The PSoC™ 4000S is offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP
packages.
Package dimensions and Infineon drawing numbers are in the following table.
Table 37
Package list
Spec ID
Package
Description
Package drawing
BID20
48-pin TQFP
7 × 7 × 1.4 mm height with 0.5-mm pitch
51-85135
BID27
40-pin QFN
6 × 6 × 0.6 mm height with 0.5-mm pitch
001-80659
BID34A
32-pin QFN
5 × 5 × 0.6 mm height with 0.5-mm pitch
001-42168
BID34
24-pin QFN
4 × 4 × 0.6 mm height with 0.5-mm pitch
001-13937
BID34G
32-pin TQFP
7 × 7 × 1.4 mm height with 0.8-mm pitch
51-85088
BID34F
25-ball WLCSP
2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch
002-09957
Table 38
Package thermal characteristics
Parameter
Description
Package
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package θJA
48-pin TQFP
–
73.5
–
°C/W
TJC
Package θJC
48-pin TQFP
–
33.5
–
°C/W
TJA
Package θJA
40-pin QFN
–
17.8
–
°C/W
TJC
Package θJC
40-pin QFN
–
2.8
–
°C/W
TJA
Package θJA
32-pin QFN
–
20.8
–
°C/W
TJC
Package θJC
32-pin QFN
–
5.9
–
°C/W
TJA
Package θJA
24-pin QFN
–
21.7
–
°C/W
TJC
Package θJC
24-pin QFN
–
5.6
–
°C/W
TJA
Package θJA
32-pin TQFP
–
29.4
–
°C/W
TJC
Package θJC
32-pin TQFP
–
3.5
–
°C/W
TJA
Package θJA
25-ball WLCSP
–
40
–
°C/W
TJC
Package θJC
25-ball WLCSP
–
0.5
–
°C/W
Table 39
Solder reflow peak temperature
Package
Maximum peak temperature
Maximum time at peak temperature
All
260 °C
30 seconds
Datasheet
43
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Table 40
8.1
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
MSL 3
25-ball WLCSP
MSL 1
Package diagrams
51-85135 *C
Figure 6
Datasheet
48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135
44
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
001-80659 *A
Figure 7
Datasheet
40-pin QFN ((6 × 6 × 0.6 mm) 4.6 × 4.6 E-Pad (Sawn)) package outline, 001-80659
45
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
DIMENSIONS
1.
SYMBOL
A
A1
NOM.
MAX.
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
0.045
4. DIMENSIONS ARE IN MILLIMETERS
-
A2
0.020
2. BASED ON REF JEDEC # MO-248
0.15 BSC
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
HATCH AREA IS SOLDERABLE EXPOSED PAD
MIN.
0.50 TYP
001-42168 *F
Figure 8
Datasheet
32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) package outline, 001-42168
46
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
001-13937 *H
Figure 9
24-pin QFN ((4 × 4 × 0.60 mm) 2.65 × 2.65 E-Pad (Sawn)) package outline, 001-13937
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and
electrical performance. If not connected to ground, it should be electrically floating and not connected to any
other signal.
Datasheet
47
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85088 *E
Figure 10
32-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85088
002-09957 **
Figure 11
Datasheet
25-ball WLCSP (2.02 × 1.93 × 0.48 mm) package outline, 002-09957
48
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
9
Acronyms
Table 41
Acronyms used in this document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
®
application program status register
ARM
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications protocol
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking protocol
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
Datasheet
49
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C, or IIC
Inter-Integrated Circuit, a communications protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
PHUB
peripheral hub
PHY
physical layer
PICU
port interrupt control unit
Datasheet
50
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
PLA
programmable logic array
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration datasheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC™
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a communications protocol
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Document conventions
10
Document conventions
10.1
Units of measure
Table 42
Units of measure
Symbol
Unit of measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision histor y
Document
version
Date of release Description of changes
**
2015-08-28
New datasheet.
*A
2015-10-30
Removed 20-ball WLCSP package related information in all instances across
the document.
Added 25-ball WLCSP package related information in all instances across
the document.
Updated Pinouts:
Updated Table 1.
Updated Electrical specifications:
Updated Analog peripherals:
Updated Comparator:
Updated Table 10 (Updated details in “Details/Conditions” column corresponding to VICM3, ICMP3 parameters (Added VDDD ≥ 2.2V at –40 °C)).
Updated Table 11 (Updated details in “Details/Conditions” column
corresponding to TRESP3 parameter (Added VDDD ≥ 2.2V at –40 °C)).
Updated CSD and IDAC:
Updated Table 13.
Updated Ordering information:
Updated part numbers.
*B
2015-12-08
Changed status from Advance to Preliminary.
*C
2016-01-27
Updated Packaging:
Updated Table 38 (Replaced TBD with values for Theta JA and Theta JC
parameters).
Updated Package diagrams:
Replaced TBD with spec 002-09957 **.
Added Errata.
*D
2016-02-16
Updated to new template.
2016-03-15
Updated Pinouts:
Updated Table 1.
Updated Electrical specifications:
Updated Device level specifications:
Updated XRES:
Updated Table 8 (Updated all values corresponding to RPULLUP parameter).
Updated Table 9 (Updated all values corresponding to TRESETWAKE
parameter).
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12.
Updated 10-bit CAPSENSE™ ADC:
Updated Table 13.
Updated Memory:
Updated Flash:
Updated Table 24 (Updated all values corresponding to TROWERASE,
TROWPROGRAM parameters).
*E
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
version
Date of release Description of changes
2016-05-12
Updated Pinouts:
Updated Alternate pin functions:
Updated Table 2.
Updated Electrical specifications:
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated all values corresponding to IDAC1INL,
IDAC2INL, SNR, IDAC1CRT1, IDAC1CRT12, IDAC1CRT22, IDAC1CRT32,
IDAC2CRT1, IDAC2CRT12, IDAC2CRT22, IDAC2CRT32, IDACMISMATCH2,
IDACMISMATCH3 parameters).
Updated 10-bit CAPSENSE™ ADC:
Updated Table 13 (Updated all values corresponding to A_SND parameter).
Removed Errata.
Updated to new template.
2016-07-27
Changed status from Preliminary to Final.
Updated Functional definition:
Updated Special function peripherals:
Updated LCD segment drive:
Updated description.
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17,
IDD20, IDD23, IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated GPIO:
Updated Table 6 (Updated details in “Details/Conditions” column corresponding to VOH parameter and spec ID SID60).
Updated Packaging:
Updated Table 37 (Updated details in “Description” column corresponding
to 25-Ball WLCSP package (Updated package dimensions)).
Updated Table 40 (Added 25-ball WLCSP package and its corresponding
details).
Completing Sunset Review.
*H
2016-09-14
Added 40-pin QFN package related information in all instances across the
document.
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17,
IDD20, IDD23, IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated Packaging:
Updated Package diagrams:
Added spec 001-80659 *A.
*I
2017-01-09
Updated Electrical specifications:
Replaced PRGIO with Smart I/O in all instances.
*J
2017-04-26
Updated Cypress Logo and Copyright.
*F
*G
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
version
*K
*L
Datasheet
Date of release Description of changes
2017-11-17
Updated Document Title to read as “PSoC® 4: PSoC 4000S Datasheet
Programmable System-on-Chip (PSoC®)”.
Added 32-pin TQFP Package related information in all instance across the
document.
Updated Ordering information:
Updated part numbers.
Updated Packaging:
Updated Package diagrams:
spec 001-42168 – Changed revision from *E to *F.
Added spec 51-85088 *E.
2019-07-31
Updated Features:
Updated 32-bit MCU subsystem:
Updated description.
Added Development ecosystem.
Added PSoC™ Creator.
Updated Functional definition:
Updated System resources:
Updated Power system:
Updated description.
Updated Watch crystal oscillator (WCO):
Updated description.
Updated Fixed function digital:
Updated Serial communication block (SCB):
Updated description.
Updated Special function peripherals:
Updated LCD segment drive:
Updated description.
Updated Pinouts:
Added Note below Table 1.
Updated Electrical specifications:
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated details in “Details/Conditions” column
corresponding to VREF, VREF_EXT and VCOMPIDAC parameters).
Updated Digital peripherals:
Updated SPI:
Updated Table 18 (Updated all values corresponding to TSSELSSCK
parameter).
Updated Ordering information:
Updated part numbers.
Updated Packaging:
Updated Package diagrams:
spec 001-13937 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
version
Date of release Description of changes
*M
2020-11-20
Updated Features:
Added “Clock sources”.
Added “ModusToolbox™ software”.
Updated Development ecosystem:
Replaced “More Information” with “Development ecosystem” in heading.
Updated description.
Added ModusToolbox™ software.
Updated Electrical specifications:
Updated Device level specifications:
Updated temperature range in description below heading.
Updated System resources:
Updated Power-on reset (POR):
Updated Table 25.
Updated Ordering information:
Updated Table 36:
Added Q-temp MPNs for the 48-pin TQFP package.
Updated Packaging:
Updated Table 38.
Updated to new template.
*N
2020-12-23
Updated Ordering information:
Updated Nomenclature:
Updated details under Temperature Range to show “Extended Industrial”.
*O
2022-07-28
Updated Table 29: Updated spec SID223 and SID223A. Added specs
SID223B through SID223D.
Migrated to Infineon template.
*P
2023-01-23
Updated the footnotes in IMO AC specifications.
Datasheet
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Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2023-01-23
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email:
erratum@infineon.com
Document reference
002-00123 Rev. *P
IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
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