Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 4: PSoC 4000S Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products are
upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
Timing and Pulse-Width Modulation
32-bit MCU Subsystem
■
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■
48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
■
Up to 32 KB of flash with Read Accelerator
■
Center-aligned, Edge, and Pseudo-random modes
■
Up to 4 KB of SRAM
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Programmable Analog
■
Single-slope 10-bit ADC function provided by Capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
Up to 36 Programmable GPIO Pins
■
48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin
TQFP, and 25-ball WLCSP packages
■
Any GPIO pin can be CapSense, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Clock Sources
Programmable Digital
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
■
32-kHz Watch Crystal Oscillator (WCO)
■
±2% Internal Main Oscillator (IMO)
Low-Power 1.71-V to 5.5-V Operation
■
32-kHz Internal Low-power Oscillator (ILO)
■
Deep Sleep mode with operational analog and 2.5 µA digital
system current
Capacitive Sensing
ModusToolbox™ Software
■
Comprehensive collection of multi-platform tools and software
libraries
Includes board support packages (BSPs), peripheral driver
library (PDL), and middleware such as CapSense
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
■
Cypress-supplied software component makes capacitive
sensing design easy
PSoC Creator Design Environment
■
Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■
Integrated development environment (IDE) provides schematic
design entry and build, with analog and digital automatic routing
■
Application programming interface (API) Components for all
fixed-function and programmable peripherals
LCD segment drive capability on GPIOs
Industry-Standard Tool Compatibility
Serial Communication
■
Two independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-00123 Rev. *N
•
■
198 Champion Court
After schematic entry, development can be done with
Arm-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 23, 2020
PSoC 4: PSoC 4000S Datasheet
Development Ecosystem
PSoC 4 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 4 MCU:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Code Examples demonstrate product features and usage, and
are also available on Cypress GitHub repositories.
Development Tools
❐ ModusToolbox™ Software enables cross platform code
development with a robust suite of tools and software
libraries.
❐ PSoC Creator is a free Windows-based IDE. It enables
concurrent hardware and firmware design of PSoC 3, PSoC
4, PSoC 5LP, and PSoC 6 MCU based systems. Applications
are created using schematic capture and over 150
pre-verified, production-ready peripheral Components.
❐ CY8CKIT-145-40XX PSoC 4000S CapSense Prototyping
Kit, is a low-cost and easy-to-use evaluation platform. This
kit provides easy access to all the device I/Os in a
breadboard-compatible format.
❐ MiniProg4
and MiniProg3 all-in-one development
programmers and debuggers.
❐ PSoC 4 MCU CAD libraries provide footprint and schematic
support for common tools. IBIS models are also available.
■
Product Selectors: PSoC 4 MCU
■
Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN79953: Getting Started With PSoC 4. This application note
has a convenient flow chart to help decide which IDE to use:
ModusToolbox™ Software or PSoC Creator.
❐ AN91184: PSoC 4 BLE - Designing BLE Applications
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
❐ AN86233: PSoC 4 MCU Power Reduction Techniques
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN85951: PSoC 4, PSoC 6 CapSense Design Guide
■
■
■
Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 4 MCU architecture and registers.
Training Videos are available on a wide range of topics
including the PSoC 4 MCU 101 series.
■
■
PSoC 4 MCU Programming Specification provides the information necessary to program PSoC 4 MCU nonvolatile
memory.
Cypress Developer Community enables connection with
fellow PSoC developers around the world, 24 hours a day, 7
days a week, and hosts a dedicated PSoC 4 MCU Community.
Document Number: 002-00123 Rev. *N
Page 2 of 42
PSoC 4: PSoC 4000S Datasheet
ModusToolbox™ Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■
Comprehensive - it has the resources you need
■
Flexible - you can use the resources in your own workflow
■
Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub, including:
■
Board Support Packages (BSPs) aligned with Cypress kits
■
Low-level resources, including a peripheral driver library (PDL)
■
Middleware enabling industry-leading features such as CapSense
■
An extensive set of thoroughly tested code example applications
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as
Figure 1 shows. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and
AN79953: Getting Started with PSoC 4.
Figure 1. ModusToolbox Software Tools
Document Number: 002-00123 Rev. *N
Page 3 of 42
PSoC 4: PSoC 4000S Datasheet
PSoC Creator
PSoC Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on
PSoC 4 MCU. As Figure 2 shows, with PSoC Creator you can:
1. Drag and drop Component icons to build your hardware system design in the main design workspace
2. Co-design your application firmware with the PSoC hardware, using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
6. Prototype your solution with the PSoC 4 Pioneer kits. If a design change is needed, PSoC Creator and Components enable you
to make changes on-the-fly without the need for hardware revisions.
Figure 2. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 002-00123 Rev. *N
Page 4 of 42
PSoC 4: PSoC 4000S Datasheet
Logic Block Diagram
CPU Subsystem
SWD/TC
32-bit
48 MHz
System Resources
Lite
SRAM Controller
ROM Controller
WCO
2x LP Comparator
Peripheral Interconnect (MMIO)
PCLK
2x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
ROM
8 KB
Peripherals
5x TCPWM
Reset
Reset Control
XRES
Read Accelerator
SRAM
4 KB
System Interconnect ( Single Layer AHB)
IOSS GPIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
FLASH
32 KB
FAST MUL
NVIC, IRQMUX
AHB- Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
SPCIF
Cortex
M0+
CapSense
PSoC 4000S
Architecture
High Speed I/ O Matrix & 2x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC 4000S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000S provides a level of security not possible
with multi-chip application solutions or with microcontrollers.
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000S allows the
customer to make.
It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00123 Rev. *N
Page 5 of 42
PSoC 4: PSoC 4000S Datasheet
Functional Description
PSoC 4000S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00123 Rev. *N
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000S allows the
customer to make.
Page 6 of 42
PSoC 4: PSoC 4000S Datasheet
Contents
Functional Definition ........................................................ 8
CPU and Memory Subsystem ..................................... 8
System Resources ...................................................... 8
Analog Blocks .............................................................. 9
Programmable Digital Blocks ...................................... 9
Fixed Function Digital .................................................. 9
GPIO ......................................................................... 10
Special Function Peripherals ..................................... 10
Pinouts ............................................................................ 11
Alternate Pin Functions ............................................. 12
Power ............................................................................... 14
Mode 1: 1.8 V to 5.5 V External Supply .................... 14
Mode 2: 1.8 V ±5% External Supply .......................... 14
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ....................................... 15
Device Level Specifications ....................................... 16
Analog Peripherals .................................................... 19
Document Number: 002-00123 Rev. *N
Digital Peripherals ..................................................... 23
Memory ..................................................................... 26
System Resources .................................................... 26
Ordering Information ...................................................... 29
Packaging ........................................................................ 31
Package Diagrams .................................................... 32
Acronyms ........................................................................ 36
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
Document History Page ................................................. 39
Sales, Solutions, and Legal Information ...................... 42
Worldwide Sales and Design Support ....................... 42
Products .................................................................... 42
PSoC® Solutions ...................................................... 42
Cypress Developer Community ................................. 42
Technical Support ..................................................... 42
Page 7 of 42
PSoC 4: PSoC 4000S Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4000S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4000S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
Clock System
The PSoC 4000S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4000S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4000S, two of those are
fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in
PSoC Creator.
Figure 3. PSoC 4000S MCU Clocking Architecture
The PSoC 4000S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
IMO
Divide By
2,4,8
HFCLK
External Clock
ILO
LFCLK
SRAM
Four KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
HFCLK
SYSCLK
Prescaler
Integer
Dividers
Fractional
Dividers
6X 16-bit
2X 16.5-bit
Power System
The power system is described in detail in the section Power on
page 14. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000S provides
Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs.
Document Number: 002-00123 Rev. *N
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4000S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications. The WCO block allows locking
the IMO to the 32-kHz oscillator. The WCO on PSoC 4000S
series devices does not connect to the LFCLK or WDT. Due to
this, RTC functionality is not supported.
Page 8 of 42
PSoC 4: PSoC 4000S Datasheet
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4000S reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
Analog Blocks
Low-power Comparators (LPC)
The PSoC 4000S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
The PSoC 4000S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4000S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4000S.
Serial Communication Block (SCB)
The PSoC 4000S has two serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4000S and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4000S is not completely compliant with the I2C spec
in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
Document Number: 002-00123 Rev. *N
Page 9 of 42
PSoC 4: PSoC 4000S Datasheet
GPIO
Special Function Peripherals
The PSoC 4000S has up to 36 GPIOs. The GPIO block
implements the following:
CapSense
■
■
Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■
Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4000S).
Document Number: 002-00123 Rev. *N
CapSense is supported in the PSoC 4000S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function,
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and Ground to null out power-supply
related noise.
LCD Segment Drive
The PSoC 4000S has an LCD controller, which can drive up to
8 commons and up to 28 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays.
Page 10 of 42
PSoC 4: PSoC 4000S Datasheet
Pinouts
The following table provides the pin list for PSoC 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP,
and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP.
Table 1. PSoC 4000S Pin List
48-pin TQFP
32-pin QFN
24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
28
P0.0
17
P0.0
13
P0.0
D1
P0.0
22
P0.0
17
P0.0
29
P0.1
18
P0.1
14
P0.1
C3
P0.1
23
P0.1
18
P0.1
30
P0.2
19
P0.2
24
P0.2
19
P0.2
31
P0.3
20
P0.3
25
P0.3
20
P0.3
32
P0.4
21
P0.4
15
P0.4
C2
P0.4
26
P0.4
21
P0.4
33
P0.5
22
P0.5
16
P0.5
C1
P0.5
27
P0.5
22
P0.5
34
P0.6
23
P0.6
17
P0.6
B1
P0.6
28
P0.6
23
P0.6
35
P0.7
B2
P0.7
29
P0.7
36
XRES
24
XRES
18
XRES
B3
XRES
30
XRES
24
XRES
37
VCCD
25
VCCD
19
VCCD
A1
VCCD
31
VCCD
25
VCCD
38
VSSD
26
VSSD
20
VSSD
A2
VSS
26
VSSD
39
VDDD
27
VDD
21
VDD
A3
VDD
32
VDDD
27
VDD
40
VDDA
27
VDD
21
VDD
A3
VDD
33
VDDA
27
VDD
41
VSSA
28
VSSA
22
VSSA
A2
VSS
34
VSSA
28
VSSA
42
P1.0
29
P1.0
35
P1.0
29
P1.0
43
P1.1
30
P1.1
36
P1.1
30
P1.1
44
P1.2
31
P1.2
23
P1.2
A4
P1.2
37
P1.2
31
P1.2
45
P1.3
32
P1.3
24
P1.3
B4
P1.3
38
P1.3
32
P1.3
46
P1.4
39
P1.4
47
P1.5
48
P1.6
1
P1.7
1
P1.7
1
P1.7
A5
P1.7
40
P1.7
1
P1.7
2
P2.0
2
P2.0
2
P2.0
B5
P2.0
1
P2.0
2
P2.0
3
P2.1
3
P2.1
3
P2.1
C5
P2.1
2
P2.1
3
P2.1
4
P2.2
4
P2.2
3
P2.2
4
P2.2
5
P2.3
5
P2.3
4
P2.3
5
P2.3
6
P2.4
5
P2.4
7
P2.5
6
P2.5
6
P2.5
6
P2.5
8
P2.6
7
P2.6
4
P2.6
D5
P2.6
7
P2.6
7
P2.6
9
P2.7
8
P2.7
5
P2.7
C4
P2.7
8
P2.7
8
P2.7
10
VSSD
A2
VSS
9
VSSD
12
P3.0
9
P3.0
E5
P3.0
10
P3.0
9
P3.0
13
P3.1
10
P3.1
14
P3.2
11
16
P3.3
12
6
P3.0
D4
P3.1
11
P3.1
10
P3.1
P3.2
7
P3.2
E4
P3.2
12
P3.2
11
P3.2
P3.3
8
P3.3
D3
P3.3
13
P3.3
12
P3.3
Document Number: 002-00123 Rev. *N
Page 11 of 42
PSoC 4: PSoC 4000S Datasheet
Table 1. PSoC 4000S Pin List (continued)
48-pin TQFP
Pin
Name
17
32-pin QFN
Pin
Name
24-pin QFN
Pin
Name
25-ball CSP
Pin
Name
40-pin QFN
Pin
Name
P3.4
14
P3.4
18
P3.5
15
P3.5
19
P3.6
16
P3.6
20
P3.7
17
P3.7
21
VDDD
32-pin TQFP
Pin
Name
22
P4.0
13
P4.0
9
P4.0
E3
P4.0
18
P4.0
13
P4.0
23
P4.1
14
P4.1
10
P4.1
D2
P4.1
19
P4.1
14
P4.1
24
P4.2
15
P4.2
11
P4.2
E2
P4.2
20
P4.2
15
P4.2
25
P4.3
16
P4.3
12
P4.3
E1
P4.3
21
P4.3
16
P4.3
Note: Pins 11, 15, 26, and 27 are No connects (NC) on the 48-pin TQFP.
Descriptions of the pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Alternate Pin Functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD
pin, or a CapSense pin. The pin assignments are shown in the following table.
Table 2. Pin Assignments
Port/
Pin
Analog
P0.0
lpcomp.in_p[0]
tcpwm.tr_in[0]
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
P0.2
lpcomp.in_p[1]
P0.3
lpcomp.in_n[1]
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
P0.6
srss.ext_clk
P0.7
scb[1].uart_cts:0
scb[1].spi_clk:1
scb[1].uart_rts:0
scb[1].spi_select0:1
P1.0
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
P1.3
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
P1.4
Document Number: 002-00123 Rev. *N
scb[0].spi_clk:1
scb[0].spi_select0:1
scb[0].spi_select1:1
Page 12 of 42
PSoC 4: PSoC 4000S Datasheet
Table 2. Pin Assignments (continued)
Port/
Pin
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
P1.5
scb[0].spi_select2:1
P1.6
scb[0].spi_select3:1
P1.7
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
P2.1
prgio[0].io[1]
tcpwm.line_compl[4]:0
P2.2
prgio[0].io[2]
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
scb[1].spi_clk:2
P2.3
prgio[0].io[3]
P2.4
prgio[0].io[4]
tcpwm.line[0]:1
scb[1].spi_select0:2
scb[1].spi_select1:1
P2.5
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
prgio[0].io[6]
tcpwm.line[1]:1
P2.7
prgio[0].io[7]
tcpwm.line_compl[1]:1
P3.0
prgio[1].io[0]
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
prgio[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
P3.4
prgio[1].io[4]
tcpwm.line[2]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
P3.5
prgio[1].io[5]
tcpwm.line_compl[2]:0
tcpwm.tr_in[7]
scb[1].spi_select2:0
P3.6
prgio[1].io[6]
tcpwm.line[3]:0
tcpwm.tr_in[8]
P3.7
prgio[1].io[7]
tcpwm.line_compl[3]:0
tcpwm.tr_in[9]
scb[1].spi_select3:1
lpcomp.comp[0]:1
cpuss.swd_clk
scb[1].spi_select0:0
scb[1].spi_select3:0
lpcomp.comp[1]:1
P4.0
csd.vref_ext
scb[0].uart_rx:0
tcpwm.tr_in[10]
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
tcpwm.tr_in[11]
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-00123 Rev. *N
Page 13 of 42
PSoC 4: PSoC 4000S Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4000S. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the VDD
input.
Figure 4. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
Analog
Domain
In this mode, the PSoC 4000S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, the PSoC 4000S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4000S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
An example of a bypass scheme is shown in the following
diagram.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8V to 5.5V
V DD
PSoC 4000S
1.8V to 5.5V
VDDA
F
0.1F
0.1F
V CCD
0.1F
V SS
Document Number: 002-00123 Rev. *N
Page 14 of 42
PSoC 4: PSoC 4000S Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
V
SID1
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input
relative to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD + 0.5
Maximum current per GPIO
SID4
IGPIO_ABS
–25
–
25
SID5
IGPIO_injection GPIO injection current, Max for
VIH > VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human
body model
2200
–
–
BID45
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
Details/Conditions
–
–
–
mA
–
Current injected per pin
V
–
–
mA
–
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-00123 Rev. *N
Page 15 of 42
PSoC 4: PSoC 4000S Datasheet
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 4. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units
V
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage
(VCCD = VDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
Details/Conditions
Internally regulated
supply
Internally unregulated
supply
–
µF
X5R ceramic or better
X5R ceramic or better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash;
CPU at 6 MHz
–
1.2
2.0
SID16
IDD8
Execute from flash;
CPU at 24 MHz
–
2.4
4.0
SID19
IDD11
Execute from flash;
CPU at 48 MHz
–
4.6
5.9
mA
–
–
–
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and
Comparators on
–
1.1
1.6
SID25
IDD20
I2C wakeup, WDT, and
Comparators on
–
1.4
1.9
mA
6 MHz
12 MHz
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
–
0.7
0.9
mA
6 MHz
SID28A
IDD23A
I2C wakeup, WDT, and
Comparators on
–
0.9
1.1
mA
12 MHz
–
2.5
60
µA
–
–
2.5
60
µA
–
–
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
60
µA
Supply current while XRES
asserted
–
2
5
mA
XRES Current
SID307
IDD_XR
–
Table 5. AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
SID48
FCPU
CPU frequency
DC
–
48
SID49[2]
TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[2]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
Units Details/Conditions
MHz 1.71 VDD 5.5
µs
–
–
Note
2. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 16 of 42
PSoC 4: PSoC 4000S Datasheet
GPIO
Table 6. GPIO DC Specifications
Spec ID#
Parameter
Min
Typ
Max
Input voltage high threshold
0.7 VDDD
–
–
VIL
Input voltage low threshold
–
–
SID241
LVTTL input, VDDD < 2.7 V
0.7 VDDD
0.3 VDDD
VIH[3]
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3 VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
–
SID59
VOH
Output voltage high level
VDDD – 0.6
–
–
IOH = 4 mA
at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD – 0.5
–
–
IOH = 1 mA
at 3 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA
at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA
at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA
at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current (absolute
value)
–
–
2
SID66
CIN
Input capacitance
–
–
7
pF
–
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDD 2.7 V
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
VDD < 4.5 V
VHYSCMOS5V5
Input hysteresis CMOS
200
–
–
VDD > 4.5 V
SID69
IDIODE
Current through protection diode
to VDD/VSS
–
–
100
µA
–
SID69A[4]
ITOT_GPIO
Maximum total source or sink
chip current
–
–
200
mA
–
SID57
VIH[3]
SID58
SID68A
[4]
[4]
Description
Units Details/Conditions
V
CMOS Input
CMOS Input
kΩ
–
nA
25 °C, VDDD = 3.0 V
–
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 17 of 42
PSoC 4: PSoC 4000S Datasheet
Table 7. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
ns
Details/Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
3.3 V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
90/10%, 25 pF load,
60/40 duty cycle
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD
3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
3.3 V VDDD,
Cload = 25 pF
MHz 90/10%, 25 pF load,
60/40 duty cycle
XRES
Table 8. XRES DC Specifications
Min
Typ
Max
Units
SID77
Spec ID#
VIH
Parameter
Input voltage high threshold
Description
0.7 × VDDD
–
–
V
CMOS Input
Details/Conditions
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Typical hysteresis is
200 mV for VDD > 4.5 V
SID82
IDIODE
Current through protection diode
to VDD/VSS
–
–
100
µA
–
Table 9. XRES AC Specifications
Spec ID#
Parameter
SID83[5]
TRESETWIDTH
BID194[5]
TRESETWAKE
Description
Min
Typ
Max
Units Details/Conditions
Reset pulse width
1
–
–
µs
–
Wake-up time from reset release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 18 of 42
PSoC 4: PSoC 4000S Datasheet
Analog Peripherals
Comparator
Table 10. Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
–
±10
Units Details/Conditions
SID84
VOFFSET1
Input offset voltage, Factory trim
–
mV
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
–
SID86
VHYST
Hysteresis when enabled
–
10
35
–
SID87
VICM1
Input common mode voltage in
normal mode
0
–
VDDD – 0.1
SID247
VICM2
Input common mode voltage in
low power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in
ultra low power mode
0
–
VDDD – 1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
–
SID259
ICMP3
Block current in ultra low-power
mode
–
6
28
VDDD ≥ 2.2 V at
–40 °C
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
Min
–
Typ
38
Max
110
V
–
Modes 1 and 2
–
VDDD ≥ 2.2 V at
–40 °C
dB
VDDD ≥ 2.7V
µA
–
VDDD ≤ 2.7V
MΩ –
Table 11. Comparator AC Specifications
Spec ID#
SID91
Parameter
Description
TRESP1
Response time, normal mode,
50 mV overdrive
SID258
TRESP2
Response time, low power mode,
50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power
mode, 200 mV overdrive
–
2.3
15
Document Number: 002-00123 Rev. *N
Units Details/Conditions
ns –
–
µs
VDDD ≥ 2.2 V at
–40 °C
Page 19 of 42
PSoC 4: PSoC 4000S Datasheet
CSD and IDAC
Table 12. CSD and IDAC Specifications
SPEC ID#
Parameter
Description
Min
Typ
Max
Units Details/Conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±50
mV
VDD > 2 V (with
ripple), 25 °C TA,
Sensitivity = 0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±25
mV
VDD > 1.75V (with
ripple), 25 °C TA,
Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK
ICSD
Maximum block current
–
–
4000
µA
Maximum block
current for both
IDACs in dynamic
(switching) mode
including
comparators, buffer,
and reference
generator.
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID.CSD#15A VREF_EXT
External Voltage reference for
CSD and Comparator
0.6
–
VDDA - 0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
µA
–
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to
5.5 V
SID308A
VCOMPIDAC
Voltage compliance range of
IDAC
0.6
–
VDDA –
0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB –
SID310
IDAC1INL
INL
–2
–
2
LSB INL is ±5.5 LSB for
VDDA < 2 V
SID311
IDAC2DNL
DNL
–1
–
1
LSB –
SID312
IDAC2INL
INL
–2
–
2
LSB INL is ±5.5 LSB for
VDDA < 2 V
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio Capacitance range of
5 to 35 pF, 0.1-pF
sensitivity. All use
cases. VDDA > 2 V.
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
Document Number: 002-00123 Rev. *N
Page 20 of 42
PSoC 4: PSoC 4000S Datasheet
Table 12. CSD and IDAC Specifications (continued)
Description
Min
Typ
Max
SID315A
SPEC ID#
IDAC2CRT2
Parameter
Output current of IDAC2 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit
mode in low range
8
–
10.5
µA
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC in 8-bit
mode in medium range
69
–
82
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit
mode in high range
540
–
660
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
SID322
IDACMISMATCH1
Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
LSB LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
5.6
LSB LSB = 300-nA typ.
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.8
LSB LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit
IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit
IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or
NP0 cap.
Document Number: 002-00123 Rev. *N
Units Details/Conditions
LSB Polarity set by Source
or Sink. Offset is 2
LSBs for 37.5 nA/LSB
mode
%
–
Page 21 of 42
PSoC 4: PSoC 4000S Datasheet
10-bit CapSense ADC
Table 13. 10-bit CapSense ADC Specifications
Min
Typ
Max
SIDA94
Spec ID#
A_RES
Parameter
Resolution
Description
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
SIDA98
A_GAINERR
Gain error
–
–
±2
%
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
–
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
–
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
–
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
SIDA108
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
–
–
21.3
µs
Does not include
acquisition time.
Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
–
–
85.3
µs
Does not include
acquisition time.
Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and Distortion
ratio (SINAD)
–
61
–
dB
With 10-Hz input sine
wave, external 2.4-V
reference, VREF
(2.4 V) mode
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
kHz 8-bit resolution
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB VREF = 2.4 V or
greater
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB –
Document Number: 002-00123 Rev. *N
Units Details/Conditions
bits
Auto-zeroing is
required every
millisecond
Defined by AMUX
Bus.
Yes –
Page 22 of 42
PSoC 4: PSoC 4000S Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 14. TCPWM Specifications
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Min
–
Typ
–
Max
45
Units Details/Conditions
µA All modes (TCPWM)
–
–
155
All modes (TCPWM)
–
–
650
All modes (TCPWM)
TCPWMFREQ
Description
Block current consumption at
3 MHz
Block current consumption at
12 MHz
Block current consumption at
48 MHz
Operating frequency
SID.TCPWM.2
ITCPWM2
SID.TCPWM.2A
ITCPWM3
SID.TCPWM.3
–
–
Fc
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
2/Fc
–
–
MHz Fc max = CLK_SYS
Maximum = 48 MHz
ns For all trigger
events[6]
SID.TCPWM.5
TPWMEXT
Output trigger pulse widths
2/Fc
–
–
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
SID.TCPWM.5A
TCRES
Resolution of counter
1/Fc
–
–
Minimum time
between successive
counts
SID.TCPWM.5B
PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width
of PWM Output
SID.TCPWM.5C
QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Document Number: 002-00123 Rev. *N
Page 23 of 42
PSoC 4: PSoC 4000S Datasheet
I2C
Table 15. Fixed I2C DC Specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
Units
µA
Details/Conditions
SID149
II2C1
Block current consumption at
100 kHz
–
–
50
–
SID150
II2C2
Block current consumption at
400 kHz
–
–
135
–
SID151
II2C3
Block current consumption at
1 Mbps
–
–
310
–
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
–
Min
Typ
Max
–
–
1
Min
Typ
Max
Units
µA
Table 16. Fixed I2C AC Specifications[7]
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Units
Details/Conditions
Msps –
SPI
Table 17. SPI DC Specifications[7]
Spec ID
Parameter
Description
Details/Conditions
SID163
ISPI1
Block current consumption at
1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at
4 Mbps
–
–
560
–
SID165
ISPI3
Block current consumption at
8 Mbps
–
–
600
–
–
Table 18. SPI AC Specifications[7]
Spec ID
SID166
Parameter
FSPI
Description
Min
Typ
Max
SPI operating frequency (Master;
6X Oversampling)
–
–
8
Units Details/Conditions
MHz –
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving
edge
–
–
15
ns
–
SID168
TDSI
MISO Valid before SClock
capturing edge
20
–
–
Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold time
0
–
–
Referred to Slave
capturing edge
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock
Capturing edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving
edge
–
–
42 + (3 × Tcpu)
SID171A
TDSO_EXT
MISO Valid after Sclock driving
edge in Ext. Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
SID172A
TSSELSSCK
SSEL Valid to first SCK Valid
edge
100
–
–
ns
–
TCPU = 1/FCPU
–
–
ns
–
Note
7. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 24 of 42
PSoC 4: PSoC 4000S Datasheet
UART
Table 19. UART DC Specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
–
Min
Typ
Max
Units
–
–
1
Table 20. UART AC Specifications[8]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Details/Conditions
Mbps –
LCD Direct Drive
Table 21. LCD Direct Drive DC Specifications[8]
Min
Typ
Max
Units
SID154
Spec ID
ILCDLOW
Parameter
Operating current in low power
mode
Description
–
5
–
µA
16 4 small segment
disp. at 50 Hz
Details/Conditions
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID156
LCDOFFSET Long-term segment offset
–
20
–
mV
–
SID157
ILCDOP1
LCD system operating current
Vbias = 5 V
–
2
–
mA
32 4 segments.
50 Hz. 25 °C
SID158
ILCDOP2
LCD system operating current
Vbias = 3.3 V
–
2
–
Min
Typ
Max
Units
10
50
150
Hz
32 4 segments.
50 Hz. 25 °C
Table 22. LCD Direct Drive AC Specifications[8]
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Details/Conditions
–
Note
8. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 25 of 42
PSoC 4: PSoC 4000S Datasheet
Memory
Flash
Table 23. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage
Min
Typ
Max
1.71
–
5.5
Units Details/Conditions
V
–
Table 24. Flash AC Specifications
Spec ID
Parameter
SID174
TROWWRITE[9]
SID175
TROWERASE[9]
Description
[9]
Min
Typ
Max
Units
Row (block) write time
(erase and program)
–
–
20
ms
Details/Conditions
Row erase time
–
–
16
–
Row (block) =
128 bytes
SID176
TROWPROGRAM
Row program time after erase
–
–
4
–
SID178
TBULKERASE[9]
Bulk erase time (32 KB)
–
–
35
–
SID180[10]
TDEVPROG[9]
Total device program time
Seconds –
SID181[10]
FEND
Flash endurance
SID182[10]
FRET
–
–
7
100 K
–
–
Cycles
–
Flash retention.
TA 55 °C, 100 K P/E cycles.
20
–
–
Years
–
SID182A[10] –
Flash retention.
TA 85 °C, 10 K P/E cycles.
10
–
–
–
SID182B[10] FRETQ
Flash retention.
TA ≤ 105 °C, 10 K P/E cycles,
≤ three years at TA ≥ 85 °C.
10
–
20
Guaranteed by
Characterization
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
System Resources
Power-on Reset (POR)
Table 25. Power On Reset (PRES)
Spec ID
Parameter
Description
Min
Typ
Max
1
–
67
SID.CLK#6
SR_POWER_UP Power supply slew rate
SID185[10]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
[10]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
SID186
Units Details/Conditions
V/ms At power-up and
power-down
V
–
–
Table 26. Brown-out Detect (BOD) for VCCD
Min
Typ
Max
SID190[10]
Spec ID
VFALLPPOR
Parameter
BOD trip voltage in active and
sleep modes
Description
1.48
–
1.62
SID192[10]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
Units Details/Conditions
V
–
–
Notes
9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
10. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 26 of 42
PSoC 4: PSoC 4000S Datasheet
SWD Interface
Table 27. SWD Interface Specifications
Min
Typ
Max
Units Details/Conditions
SID213
Spec ID
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[11]
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
SID216
T_SWDI_HOLD
0.25 × T
–
–
–
SID217[11]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5 × T
–
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
–
[11]
SID217A
[11]
Parameter
Description
T = 1/f SWDCLK
ns
–
Internal Main Oscillator (IMO)
Table 28. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Table 29. IMO AC Specifications
Spec ID
Min
Typ
Max
FIMOTOL1
Frequency variation at 24, 32,
and 48 MHz (trimmed)
–
–
±2
–
–
SID226
TSTARTIMO
IMO startup time
–
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
Min
Typ
Max
–
0.3
1.05
SID223
Parameter
SID223A
Description
Units Details/Conditions
%
–
±2.5
%
105 °C
7
µs
–
–
ps
–
Internal Low-Speed Oscillator (ILO)
Table 30. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231[11]
Parameter
IILO1
Description
ILO operating current
Units Details/Conditions
µA
–
Table 31. ILO AC Specifications
Min
Typ
Max
SID234[11]
Spec ID
TSTARTILO1
Parameter
ILO startup time
Description
–
–
2
SID236[11]
TILODUTY
ILO duty cycle
40
50
60
SID237
FILOTRIM1
ILO frequency range
20
40
80
Units Details/Conditions
ms
–
%
–
kHz –
Note
11. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 27 of 42
PSoC 4: PSoC 4000S Datasheet
Watch Crystal Oscillator (WCO)
Table 32. Watch Crystal Oscillator (WCO) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID398
FWCO
Crystal Frequency
–
32.768
–
SID399
FTOL
Frequency tolerance
–
50
250
kHz –
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive Level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
–
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating Current (high power
mode)
–
–
8
µA
–
SID406
IWCO2
Operating Current (low power
mode)
–
–
1
µA
–
Units
ppm With 20-ppm crystal
External Clock
Table 33. External Clock Specifications
Min
Typ
Max
SID305[12]
Spec ID
ExtClkFreq
Parameter
External clock input frequency
Description
0
–
48
SID306[12]
ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
Min
Typ
Max
3
–
4
Details/Conditions
MHz –
%
–
Clock
Table 34. Clock Specs
Spec ID
SID262[12]
Parameter
Description
TCLKSWITCH System clock source switching
time
Units
Details/Conditions
Periods –
Smart I/O Pass-through Time
Table 35. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
SID252
Parameter
Description
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
Min
Typ
Max
–
–
1.6
Units Details/Conditions
ns
–
Note
12. Guaranteed by characterization.
Document Number: 002-00123 Rev. *N
Page 28 of 42
PSoC 4: PSoC 4000S Datasheet
Ordering Information
The PSoC 4000S part numbers and features are listed in the following table.
Table 36. PSoC 4000S Ordering Information
4025
4045
TCPWM Blocks
SCB Blocks
Smart I/Os
GPIO
WLCSP (0.35-mm pitch)
0
1
0
2
5
2
8
21
✔
0
0
1
0
2
5
2
8
19
CY8C4024LQI-S402
24
16
2
0
0
1
0
2
5
2
16
27
CY8C4024AXI-S402
24
16
2
0
0
1
0
2
5
2
16
27
CY8C4024LQI-S403
24
16
2
0
0
1
0
2
5
2
16
34
CY8C4024AZI-S403
24
16
2
0
0
1
0
2
5
2
16
36
CY8C4024FNI-S412
24
16
2
0
1
1
0
2
5
2
8
21
CY8C4024LQI-S411
24
16
2
0
1
1
0
2
5
2
8
19
CY8C4024LQI-S412
24
16
2
0
1
1
0
2
5
2
16
27
CY8C4024AXI-S412
24
16
2
0
1
1
0
2
5
2
16
27
CY8C4024LQI-S413
24
16
2
0
1
1
0
2
5
2
16
34
CY8C4024AZI-S413
24
16
2
0
1
1
0
2
5
2
16
36
CY8C4024AZQ-S413
24
16
2
0
1
1
0
2
5
2
16
36
CY8C4025FNI-S402
24
32
4
0
0
1
0
2
5
2
8
21
CY8C4025LQI-S401
24
32
4
0
0
1
0
2
5
2
8
19
CY8C4025LQI-S402
24
32
4
0
0
1
0
2
5
2
16
27
CY8C4025AXI-S402
24
32
4
0
0
1
0
2
5
2
16
27
CY8C4025LQI-S403
24
32
4
0
0
1
0
2
5
2
16
34
✔
✔
✔
✔
✔
✔
–40 to 85 °C
✔
✔
✔
✔
✔
✔
–40 to 105 °C
✔
✔
✔
–40 to 85 °C
✔
✔
CY8C4025AZI-S403
24
32
4
0
0
1
0
2
5
2
16
36
✔
CY8C4025AZQ-S403
24
32
4
0
0
1
0
2
5
2
16
36
✔
CY8C4025FNI-S412
24
32
4
0
1
1
0
2
5
2
8
21
–40 to 105 °C
✔
✔
CY8C4025LQI-S411
24
32
4
0
1
1
0
2
5
2
8
19
CY8C4025LQI-S412
24
32
4
0
1
1
0
2
5
2
16
27
CY8C4025AXI-S412
24
32
4
0
1
1
0
2
5
2
16
27
CY8C4025LQI-S413
24
32
4
0
1
1
0
2
5
2
16
34
CY8C4025AZI-S413
24
32
4
0
1
1
0
2
5
2
16
36
CY8C4025AZQ-S413
24
32
4
0
1
1
0
2
5
2
16
36
CY8C4045FNI-S412
48
32
4
0
1
1
0
2
5
2
8
21
CY8C4045LQI-S411
48
32
4
0
1
1
0
2
5
2
8
19
CY8C4045LQI-S412
48
32
4
0
1
1
0
2
5
2
16
27
CY8C4045AXI-S412
48
32
4
0
1
1
0
2
5
2
16
27
CY8C4045LQI-S413
48
32
4
0
1
1
0
2
5
2
16
34
CY8C4045AZI-S413
48
32
4
0
1
1
0
2
5
2
16
36
✔
CY8C4045AZQ-S413
48
32
4
0
1
1
0
2
5
2
16
36
✔
Document Number: 002-00123 Rev. *N
Temperature Range
LP Comparators
0
2
48-pin TQFP
12-bit SAR ADC
2
16
40-pin QFN
10-bit CSD ADC
16
24
32-pin TQFP
CapSense
24
32-pin QFN
Opamp (CTBm)
CY8C4024FNI-S402
CY8C4024LQI-S401
MPN
24-pin QFN
SRAM (KB)
4024
Flash (KB)
Category
Package
Max CPU Speed (MHz)
Features
✔
–40 to 85 °C
✔
✔
✔
✔
–40 to 105 °C
✔
✔
✔
–40 to 85 °C
✔
✔
–40 to 105 °C
Page 29 of 42
PSoC 4: PSoC 4000S Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Table 37. Nomenclature
Field
Description
Values
Meaning
CY8C
Cypress Prefix
4
Architecture
4
PSoC 4
A
Family
0
4000 Family
B
CPU Speed
2
24 MHz
4
48 MHz
C
Flash Capacity
DE
Package Code
F
Temperature Range
S
Series Designator
XYZ
Attributes Code
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
I
Industrial
Q
Extended Industrial
S
PSoC 4 S-Series
M
PSoC 4 M-Series
L
PSoC 4 L-Series
BL
PSoC 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
Example
CY8C 4 A B C DE F – S XYZ
Cypress Prefix
Architecture
4: PSoC 4
1:
2:
4200
Family
0: 4100
4000 Family
Family within Architecture
CPU Speed
4: 48 MHz
5: 32 KB
Flash Capacity
AZ: TQFP
AX:
TQFP
Package Code
I: Industrial
Temperature Range
Silicon Family
Attributes Code
Document Number: 002-00123 Rev. *N
Page 30 of 42
PSoC 4: PSoC 4000S Datasheet
Packaging
The PSoC 4000S is offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 38. Package List
Spec ID#
Package
BID20
48-pin TQFP
7 × 7 × 1.4 mm height with 0.5-mm pitch
51-85135
BID27
40-pin QFN
6 × 6 × 0.6 mm height with 0.5-mm pitch
001-80659
BID34A
32-pin QFN
5 × 5 × 0.6 mm height with 0.5-mm pitch
001-42168
BID34
24-pin QFN
4 × 4 × 0.6 mm height with 0.5-mm pitch
001-13937
BID34G
32-pin TQFP
BID34F
25-ball WLCSP
Description
Package Dwg
7 × 7 × 1.4 mm height with 0.8-mm pitch
51-85088
2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch
002-09957
Table 39. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package θJA
48-pin TQFP
–
73.5
–
°C/W
TJC
Package θJC
48-pin TQFP
–
33.5
–
°C/W
TJA
Package θJA
40-pin QFN
–
17.8
–
°C/W
TJC
Package θJC
40-pin QFN
–
2.8
–
°C/W
TJA
Package θJA
32-pin QFN
–
20.8
–
°C/W
TJC
Package θJC
32-pin QFN
–
5.9
–
°C/W
TJA
Package θJA
24-pin QFN
–
21.7
–
°C/W
TJC
Package θJC
24-pin QFN
–
5.6
–
°C/W
TJA
Package θJA
32-pin TQFP
–
29.4
–
°C/W
TJC
Package θJC
32-pin TQFP
–
3.5
–
°C/W
TJA
Package θJA
25-ball WLCSP
–
40
–
°C/W
TJC
Package θJC
25-ball WLCSP
–
0.5
–
°C/W
Table 40. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
MSL 3
25-ball WLCSP
MSL 1
Document Number: 002-00123 Rev. *N
Page 31 of 42
PSoC 4: PSoC 4000S Datasheet
Package Diagrams
Figure 6. 48-pin TQFP (7 × 7 × 1.4 mm) Package Outline, 51-85135
51-85135 *C
Figure 7. 40-pin QFN (6 × 6 × 0.6 mm) Package Outline, 001-80659
001-80659 *A
Document Number: 002-00123 Rev. *N
Page 32 of 42
PSoC 4: PSoC 4000S Datasheet
Figure 8. 32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) Package Outline, 001-42168
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DIMENSIONS
A
A1
HATCH AREA IS SOLDERABLE EXPOSED PAD
MIN.
NOM.
MAX.
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
0.045
4. DIMENSIONS ARE IN MILLIMETERS
-
A2
0.020
2. BASED ON REF JEDEC # MO-248
0.15 BSC
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
NOTES:
1.
SYMBOL
0.50 TYP
001-42168 *F
Document Number: 002-00123 Rev. *N
Page 33 of 42
PSoC 4: PSoC 4000S Datasheet
Figure 9. 24-pin QFN ((4 × 4 × 0.60 mm) 2.65 × 2.65 E-Pad (Sawn)) Package Outline, 001-13937
001-13937 *H
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 10. 32-pin TQFP (7 × 7 × 1.4 mm) Package Outline, 51-85088
51-85088 *E
Document Number: 002-00123 Rev. *N
Page 34 of 42
PSoC 4: PSoC 4000S Datasheet
Figure 11. 25-ball WLCSP (2.02 × 1.93 × 0.48 mm) Package Outline, 002-09957
002-09957 **
Document Number: 002-00123 Rev. *N
Page 35 of 42
PSoC 4: PSoC 4000S Datasheet
Acronyms
Table 42. Acronyms Used in this Document (continued)
Acronym
Table 42. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
AMUXBUS analog multiplexer bus
IDAC
current DAC, see also DAC, VDAC
API
application programming interface
IDE
integrated development environment
APSR
application program status register
2C,
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
I
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
common-mode rejection ratio
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CPU
central processing unit
IPOR
initial power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 002-00123 Rev. *N
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
Page 36 of 42
PSoC 4: PSoC 4000S Datasheet
Table 42. Acronyms Used in this Document (continued)
Acronym
Description
Table 42. Acronyms Used in this Document (continued)
Acronym
Description
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration datasheet
UDB
universal digital block
POR
power-on reset
USB
Universal Serial Bus
PRES
precise power-on reset
USBIO
PRS
pseudo random sequence
USB input/output, PSoC pins used to connect to a
USB port
PS
port read data register
VDAC
voltage DAC, see also DAC, IDAC
PSoC®
Programmable System-on-Chip™
WDT
watchdog timer
PSRR
power supply rejection ratio
WOL
write once latch, see also NVL
PWM
pulse-width modulator
WRES
watchdog timer reset
RAM
random-access memory
XRES
external reset I/O pin
RISC
reduced-instruction-set computing
XTAL
crystal
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
Document Number: 002-00123 Rev. *N
Page 37 of 42
PSoC 4: PSoC 4000S Datasheet
Document Conventions
Units of Measure
Table 43. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-00123 Rev. *N
Page 38 of 42
PSoC 4: PSoC 4000S Datasheet
Document History Page
Description Title: PSoC 4: PSoC 4000S Datasheet, Programmable System-on-Chip (PSoC)
Document Number: 002-00123
Revision
ECN
Submission
Date
**
4883809
08/28/2015
New data sheet.
*A
4992376
10/30/2015
Removed 20-ball WLCSP package related information in all instances across the document.
Added 25-ball WLCSP package related information in all instances across the document.
Updated Pinouts:
Updated Table 1.
Updated Electrical Specifications:
Updated Analog Peripherals:
Updated Comparator:
Updated Table 10 (Updated details in “Details/Conditions” column corresponding to VICM3,
ICMP3 parameters (Added VDDD ≥ 2.2V at –40 °C)).
Updated Table 11 (Updated details in “Details/Conditions” column corresponding to
TRESP3 parameter (Added VDDD ≥ 2.2V at –40 °C)).
Updated CSD and IDAC:
Updated Table 13.
Updated Ordering Information:
Updated part numbers.
*B
5037826
12/08/2015
Changed status from Advance to Preliminary.
*C
5104369
01/27/2016
Updated Packaging:
Updated Table 39 (Replaced TBD with values for Theta JA and Theta JC parameters).
Updated Package Diagrams:
Replaced TBD with spec 002-09957 **.
Added Errata.
*D
5139206
02/16/2016
Updated to new template.
*E
5173961
03/15/2016
Updated Pinouts:
Updated Table 1.
Updated Electrical Specifications:
Updated Device Level Specifications:
Updated XRES:
Updated Table 8 (Updated all values corresponding to RPULLUP parameter).
Updated Table 9 (Updated all values corresponding to TRESETWAKE parameter).
Updated Analog Peripherals:
Updated CSD and IDAC:
Updated Table 12.
Updated 10-bit CapSense ADC:
Updated Table 13.
Updated Memory:
Updated Flash:
Updated Table 24 (Updated all values corresponding to TROWERASE, TROWPROGRAM
parameters).
*F
5268662
05/12/2016
Updated Pinouts:
Updated Alternate Pin Functions:
Updated Table 2.
Updated Electrical Specifications:
Updated Analog Peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated all values corresponding to IDAC1INL, IDAC2INL, SNR,
IDAC1CRT1, IDAC1CRT12, IDAC1CRT22, IDAC1CRT32, IDAC2CRT1, IDAC2CRT12,
IDAC2CRT22, IDAC2CRT32, IDACMISMATCH2, IDACMISMATCH3 parameters).
Updated 10-bit CapSense ADC:
Updated Table 13 (Updated all values corresponding to A_SND parameter).
Removed Errata.
Updated to new template.
Document Number: 002-00123 Rev. *N
Description of Change
Page 39 of 42
PSoC 4: PSoC 4000S Datasheet
Document History Page (continued)
Description Title: PSoC 4: PSoC 4000S Datasheet, Programmable System-on-Chip (PSoC)
Document Number: 002-00123
Revision
ECN
Submission
Date
*G
5330930
07/27/2016
Changed status from Preliminary to Final.
Updated Functional Definition:
Updated Special Function Peripherals:
Updated LCD Segment Drive:
Updated description.
Updated Electrical Specifications:
Updated Device Level Specifications:
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17, IDD20, IDD23,
IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated GPIO:
Updated Table 6 (Updated details in “Details/Conditions” column corresponding to VOH
parameter and spec ID SID60).
Updated Packaging:
Updated Table 38 (Updated details in “Description” column corresponding to 25-Ball
WLCSP package (Updated package dimensions)).
Updated Table 41 (Added 25-Ball WLCSP package and its corresponding details).
Completing Sunset Review.
*H
5415365
09/14/2016
Added 40-pin QFN package related information in all instances across the document.
Updated Electrical Specifications:
Updated Device Level Specifications:
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17, IDD20, IDD23,
IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated Packaging:
Updated Package Diagrams:
Added spec 001-80659 *A.
*I
5561833
01/09/2017
Updated Electrical Specifications:
Replaced PRGIO with Smart I/O in all instances.
*J
5704046
04/26/2017
Updated the Cypress Logo and Copyright.
*K
5969745
11/17/2017
Updated Document Title to read as “PSoC® 4: PSoC 4000S Datasheet Programmable
System-on-Chip (PSoC®)”.
Added 32-pin TQFP Package related information in all instance across the document.
Updated Ordering Information:
Updated part numbers.
Updated Packaging:
Updated Package Diagrams:
spec 001-42168 – Changed revision from *E to *F.
Added spec 51-85088 *E.
*L
6639191
07/31/2019
Updated Features:
Updated 32-bit MCU Subsystem:
Updated description.
Added Development Ecosystem.
Added PSoC Creator.
Updated Functional Definition:
Updated System Resources:
Updated Power System:
Updated description.
Updated Watch Crystal Oscillator (WCO):
Updated description.
Updated Fixed Function Digital:
Updated Serial Communication Block (SCB):
Updated description.
Updated Special Function Peripherals:
Updated LCD Segment Drive:
Updated description.
Document Number: 002-00123 Rev. *N
Description of Change
Page 40 of 42
PSoC 4: PSoC 4000S Datasheet
Document History Page (continued)
Description Title: PSoC 4: PSoC 4000S Datasheet, Programmable System-on-Chip (PSoC)
Document Number: 002-00123
Revision
ECN
Submission
Date
Description of Change
*L (cont.)
6639191
07/31/2019
Updated Pinouts:
Added Note below Table 1.
Updated Electrical Specifications:
Updated Analog Peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated details in “Details/Conditions” column corresponding to VREF,
VREF_EXT and VCOMPIDAC parameters).
Updated Digital Peripherals:
Updated SPI:
Updated Table 18 (Updated all values corresponding to TSSELSSCK parameter).
Updated Ordering Information:
Updated part numbers.
Updated Packaging:
Updated Package Diagrams:
spec 001-13937 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*M
7026754
11/20/2020
Added Clock Sources and ModusToolbox™ in Features.
Updated Development Ecosystem.
Updated temperature range in Electrical Specifications: Added Q-temp MPNs for the
48-TQFP package.
Updated Table 25: Updated SID.CLK#6 Description.
Updated Table 39: Updated Typ. value for TJA 25-ball WLCSP.
Updated Sales, Solutions, and Legal Information.
*N
7036861
12/23/2020
Updated Table 37: Updated Nomenclature to show “Extended Industrial”.
Document Number: 002-00123 Rev. *N
Page 41 of 42
PSoC 4: PSoC 4000S Datasheet
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Document Number: 002-00123 Rev. *N
Revised December 23, 2020
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