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Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Programmable System-on-Chip (PSoC®)
Automotive PSoC ® 4: PSoC 4100S Family Datasheet, Programmable System-on-Chip (PSoC ®)
Functional Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex®-M0+ CPU, while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination
of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with
best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and
programmable connectivity. PSoC 4100S products will be upward compatible with members of the PSoC 4 platform for new
applications and design needs.
Features
■
Automotive Electronics Council (AEC) AEC-Q100 Qualified
■
32-bit MCU subsystem
❐ 48-MHz Arm Cortex-M0+ CPU
❐ Up to 64 KB of flash with Read Accelerator
❐ Up to 8 KB of SRAM
■
Programmable analog
❐ Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and
ADC input buffering capability. Opamps can operate in Deep
Sleep low-power mode.
❐ 12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
❐ Single-slope 10-bit ADC function provided by a capacitance
sensing block
❐ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
❐ Two low-power comparators that operate in Deep Sleep
low-power mode
■
LCD drive capability
❐ LCD segment drive capability on GPIOs
■
Serial communication
❐ Three independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, UART
or LIN Slave functionality
■
Timing and pulse-width modulation
❐ Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
❐ Center-aligned, Edge, and Pseudo-random modes
❐ Comparator-based triggering of Kill signals for motor drive
and other high-reliability digital logic applications
■
Up to 34 programmable GPIO pins
❐ 28-pin SSOP, and 40-pin QFN packages
❐ Any GPIO pin can be CapSense, analog, or digital
❐ Drive modes, strengths, and slew rates are programmable
■
PSoC Creator Design Environment
❐ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
❐ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
■
Programmable digital
❐ Programmable logic blocks allowing Boolean operations to
be performed on port inputs and outputs
■
Low-power 1.71-V to 5.5-V operation
❐ Deep Sleep mode with operational analog and 2.5-A digital
system current
■
Industry-standard tool compatibility
❐ After schematic entry, development can be done with
Arm-based industry-standard development tools
■
Capacitive sensing
❐ Cypress
CapSense Sigma Delta (CSD) provides
best-in-class signal-to-noise ratio (SNR) (>5:1) and water
tolerance
❐ Cypress-supplied software component makes capacitive
sensing design easy
❐ Automatic hardware tuning (SmartSense™)
■
Temperature ranges
❐ A-Grade: –40 °C to +85 °C
❐ S-Grade: –40 °C to +105 °C
[1]
❐ E-Grade: –40 °C to +125 °C
Note
1. This device can also operate at temperatures exceeding 125 °C (the high temperature of the AEC-Q100 Grade 1 operating range) for a limited amount of time
depending on the mission profile of the application. Cypress provides a retention calculator to help estimate the retention lifetime based on the customers' individual
temperature profiles for operation throughout the –40 °C to +150 °C ambient temperature range. Contact techsupport@cypress.com.
Cypress Semiconductor Corporation
Document Number: 002-15106 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 29, 2020
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Contents
Logic Block Diagram ........................................................ 3
Functional Overview ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks .............................................................. 5
Fixed Function Digital .................................................. 6
LIN Slave Mode ........................................................... 6
GPIO ........................................................................... 6
Special Function Peripherals ....................................... 7
Pinouts .............................................................................. 8
Alternate Pin Functions ............................................. 10
Power ............................................................................... 12
Mode 1: 1.8 V to 5.5 V External Supply .................... 12
Mode 2: 1.8 V ±5% External Supply .......................... 12
Development Support .................................................... 13
Documentation .......................................................... 13
Online ........................................................................ 13
Tools .......................................................................... 13
Document Number: 002-15106 Rev. *H
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 14
Device-Level Specifications ...................................... 14
Analog Peripherals .................................................... 18
Digital Peripherals ..................................................... 27
Memory ..................................................................... 30
System Resources .................................................... 30
Ordering Information ...................................................... 33
Packaging Information ................................................... 36
Package Diagrams .................................................... 37
Acronyms ........................................................................ 39
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Document History Page ................................................. 42
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Page 2 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Logic Block Diagram
Figure 1. Logic Block Diagram
CPU Subsystem
SWD/TC
Cortex
M0+
32-bit
48 MHz
System Resources
Lite
SRAM Controller
ROM
8 KB
ROM Controller
Peripherals
SAR ADC
(12-bit)
SARMUX
WCO
Programmable
Analog
2x LP Comparator
Peripheral Interconnect (MMIO)
PCLK
3x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
Read Accelerator
CapSense
Reset
Reset Control
XRES
SRAM
4 KB
System Interconnect (Single Layer AHB)
IOSS GPIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
FLASH
64 KB
FAST MUL
NVIC, IRQMUX
AHB- Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
SPCIF
5x TCPWM
PSoC 4100S
Architecture
CTBm
2 x Opamp
High Speed I/O Matrix & 2 x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
Document Number: 002-15106 Rev. *H
34x GPIOs, LCD
I/O Subsystem
Page 3 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Functional Overview
PSoC 4100S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm SWD interface supports all programming and debug
features of the device.
Flash
The PSoC 4100S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
SRAM
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers.
An 8 KB supervisory ROM that contains boot and configuration
routines is provided.
It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4100S allows the
customer to make.
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4100S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a wakeup interrupt
controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
Eight KB of SRAM are provided with zero wait state access at
48 MHz.
SROM
System Resources
Power System
The power system is described in detail in the section Power on
page 12. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4100S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4100S provides
Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4100S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4100S consists of the internal
main oscillator (IMO), internal low-speed oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
The CPU also includes a debug interface, the SWD interface,
which is a two-wire form of JTAG. The debug configuration used
for PSoC 4100S has four breakpoint (address) comparators and
two watchpoint (data) comparators.
Document Number: 002-15106 Rev. *H
Page 4 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Figure 2. PSoC 4100S MCU Clocking Architecture
IMO
Divide By
2,4,8
HFCLK
LFCLK
Prescaler
Fractional
Dividers
SYSCLK
6X 16-bit
2X 16.5-bit
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4100S; two of those are
fractional dividers. The 16-bit capability allows flexible
generation of fine-grained frequency values and is fully
supported in PSoC Creator
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 3. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4100S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Document Number: 002-15106 Rev. *H
SARMUX
P7
Watchdog Timer
Port 2 (8 inputs)
The PSoC 4100S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
P0
Watch Crystal Oscillator (WCO)
vminus vplus
ILO
Integer
Dividers
12-bit Successive Approximation Register (SAR) ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
External Clock
HFCLK
Analog Blocks
Data and
Status Flags
POS
SARADC
NEG
External
Reference
and
Bypass
(optional )
Reference
Selection
VDD/2
VDDD
VREF
Inputs from other Ports
Two Opamps (Continuous-Time Block; CTB)
The PSoC 4100S has two opamps with Comparator modes
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, Voltage
Buffers, Filters, Trans-Impedance Amplifiers, and other functions
can be realized, in some cases with external passives. saving
power, cost, and space. The on-chip opamps are designed with
enough bandwidth to drive the Sample-and-Hold circuit of the
ADC without requiring external buffering.
Page 5 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Low-power Comparators (LPC)
The PSoC 4100S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
memory. In addition, the block supports an 8-deep FIFO for
receive and transmit which, by increasing the time given for the
CPU to read data, greatly reduces the need for clock stretching
caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4100S is not completely compliant with the I2C spec
in the following respect:
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
The PSoC 4100S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
■
Analog Multiplexed Buses
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
The PSoC 4100S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The Programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4100S.
Serial Communication Block (SCB)
The PSoC 4100S has three serial communication blocks, which
can be programmed to have SPI, I2C, UART or LIN Slave
functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4100S and effectively reduces I2C
communication to reading from and writing to an array in
Document Number: 002-15106 Rev. *H
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
LIN Slave Mode
The LIN Slave mode uses the SCB hardware block and
implements a full LIN slave interface. This LIN Slave is compliant
with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2
specification standards. It is certified by C&S GmbH based on
the standard protocol and data link layer conformance tests. LIN
slave can be operated at baud rates of up to ~20 Kbps with a
maximum of 40-meter cable length. PSoC Creator software
supports up to two LIN slave interfaces in the PSoC 4 device,
providing built-in application programming interfaces (APIs)
based on the LIN specification standard.
GPIO
The PSoC 4100S has up to 34 GPIOs.
The GPIO block implements the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
Page 6 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disabled state so as not to crowbar any inputs and/or
cause excess turn-on current. A multiplexing network known as
a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4100S).
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4100S through a CSD block
that can be connected to any pins through an analog multiplex
bus via analog switches. CapSense function can thus be
provided on any available pin or group of pins in a system under
software control. A PSoC Creator component is provided for the
CapSense block to make it easy for the user.
LCD Segment Drive
The PSoC 4100S has an LCD controller, which can drive up to
4 commons and up to 32 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; 1 32-bit register per port).
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
Document Number: 002-15106 Rev. *H
Page 7 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Pinouts
The following table provides the pin list for PSoC 4100S for the for the 40-pin QFN and 28-pin SSOP packages. All port pins support
GPIO.
Table 1. Pin List
40-pin QFN (AUTO)
28-pin SSOP (AUTO)
Pin
Name
Pin
Name
22
P0.0
19
P0.0
23
P0.1
20
P0.1
24
P0.2
21
P0.2
25
P0.3
22
P0.3
26
P0.4
27
P0.5
28
P0.6
23
P0.6
29
P0.7
24
P0.7
30
XRES
25
XRES
31
VCCD
26
VCCD
32
VSSD
27
VSS
33
VDD
28
VDD
34
VSSA
DN
VSS
35
P1.0
1
P1.0
36
P1.1
2
P1.1
37
P1.2
3
P1.2
38
P1.3
4
P1.3
39
P1.4
5
P1.4
40
P1.7/VREF
6
P1.7/VREF
1
P2.0
2
P2.1
3
P2.2
4
P2.3
5
P2.4
7
P2.4
6
P2.5
8
P2.5
7
P2.6
9
P2.6
8
P2.7
10
P2.7
9
VSSD
10
P3.0
11
P3.0
11
P3.1
12
P3.1
12
P3.2
13
P3.2
13
P3.3
14
P3.3
14
P3.4
15
P3.5
16
P3.6
Document Number: 002-15106 Rev. *H
Page 8 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 1. Pin List (continued)
40-pin QFN (AUTO)
28-pin SSOP (AUTO)
Pin
Name
Pin
Name
17
P3.7
18
19
P4.0
15
P4.0
P4.1
16
P4.1
20
P4.2
17
P4.2
21
P4.3
18
P4.3
The Power pins description is as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply
Document Number: 002-15106 Rev. *H
Page 9 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions. For example, it can be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin.
Table 2 provides the pin assignments.
Table 2. Pinouts
Port/Pin
Analog
P0.0
Smart I/O
Alternate Function 1
Alternate Function 2
Alternate Function 3
Deep Sleep 1
Deep Sleep 2
lpcomp.in_p[0]
tcpwm.tr_in[0]
scb[2].i2c_scl:0
scb[0].spi_select1:0
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
scb[2].i2c_sda:0
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
scb[0].spi_select3:0
P0.3
lpcomp.in_n[1]
scb[2].spi_select0
P0.4
wco.wco_in
P0.5
wco.wco_out
scb[1].uart_rx:0
scb[2].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
scb[1].i2c_sda:0
scb[1].spi_miso:1
scb[1].uart_tx:0
scb[2].uart_tx:0
P0.6
srss.ext_clk
scb[1].uart_cts:0
scb[2].uart_tx:1
P0.7
tcpwm.line[0]:2
scb[1].uart_rts:0
scb[1].spi_clk:1
scb[1].spi_select0:1
P1.0
ctb0_oa0+
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
ctb0_oa0-
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0_oa0_out
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:1
scb[0].spi_clk:1
P1.3
ctb0_oa1_out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:1
scb[0].spi_select0:1
P1.4
ctb0_oa1-
scb[0].spi_select1:1
P1.7
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
scb[2].spi_clk
P2.0
sarmux[0]
prgio[0].io[0]
tcpwm.line[4]:0
P2.1
sarmux[1]
prgio[0].io[1]
tcpwm.line_compl[4]:0
P2.2
sarmux[2]
prgio[0].io[2]
scb[1].spi_clk:2
P2.3
sarmux[3]
prgio[0].io[3]
scb[1].spi_select0:2
P2.4
sarmux[4]
prgio[0].io[4]
tcpwm.line[0]:1
scb[1].spi_select1:1
P2.5
sarmux[5]
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
Document Number: 002-15106 Rev. *H
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
Page 10 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 2. Pinouts (continued)
Port/Pin
Analog
Smart I/O
Alternate Function 1
P2.6
sarmux[6]
prgio[0].io[6]
tcpwm.line[1]:1
P2.7
sarmux[7]
prgio[0].io[7]
tcpwm.line_compl[1]:1
P3.0
prgio[1].io[0]
tcpwm.line[0]:0
P3.1
prgio[1].io[1]
P3.2
Alternate Function 2
Alternate Function 3
Deep Sleep 1
Deep Sleep 2
scb[1].spi_select3:1
lpcomp.comp[0]:1
scb[2].spi_mosi
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
prgio[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
P3.4
prgio[1].io[4]
tcpwm.line[2]:0
P3.5
prgio[1].io[5]
tcpwm.line_compl[2]:0
scb[1].spi_select2:0
P3.6
prgio[1].io[6]
tcpwm.line[3]:0
scb[1].spi_select3:0
P3.7
prgio[1].io[7]
tcpwm.line_compl[3]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
lpcomp.comp[1]:1
scb[2].spi_miso
P4.0
csd.vref_ext
scb[0].uart_rx:0
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-15106 Rev. *H
Page 11 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
Figure 4 illustrates the set of power supply pins as implemented
for the PSoC 4100S. The system has one regulator in Active
mode for the digital circuitry. There is no analog regulator; the
analog circuits run directly from the VDDA input.
Figure 4. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
VDDD
Analog
Domain
Mode 2: 1.8 V ±5% External Supply
Digital
Domain
In this mode, the PSoC 4100S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed.
VSSD
1.8 Volt
Regulator
In this mode, the PSoC 4100S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
VCCD
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead
inductance, and the bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
On some packages, VDDD and VDDA pins are shorted inside the
package and brought out as a generic VDD pin. In that case, only
0.1 µF and 1 µF decoupling capacitors are required on the VDD
pin. Figure 5 illustrates an example of a bypass scheme.
Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8 V to 5.5 V
1.8 V to 5.5 V
VDDA
VDD
F
0.1F
F
1 F
VCCD
PSoC 4100S
0.1F
VSS
Document Number: 002-15106 Rev. *H
Page 12 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Development Support
The PSoC 4100S family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4100S family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4100S family is part of a development tool
ecosystem. Visit us at www.cypress.com/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 002-15106 Rev. *H
Page 13 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings[2]
Spec ID
Parameter
Description
Min
Typ
Max
SID1
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
SID5
IGPIO_injection
GPIO injection current, Max for
VIH > VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
Details/
Conditions
Units
–
V
–
–
–
mA
Current injected
per pin
–
V
mA
–
–
Device-Level Specifications
All specifications are valid for –40 °C ≤ TA ≤ 85 °C for Grade-A devices, –40 °C ≤ TA ≤ 105 °C for Grade-S devices, and –40 °C ≤ TA
≤ 125 °C for Grade-E devices. Specifications are valid for 1.71 V to 5.5 V, except where noted.[3]
DC Specifications
Table 4. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID
Parameter
Description
Min
Typ
Max
Details/
Conditions
Units
Internally
regulated supply
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage
(VCCD = VDDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
–
X5R ceramic or
better
V
Internally
unregulated
supply
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
X5R ceramic or
better
Max is at 125 °C
and 5.5 V
µF
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.7
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.75
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
6.85
mA
Max is at 125 °C
and 5.5 V
Max is at 125 °C
and 5.5 V
Notes
2. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
3. This device is not AEC Q100 Grade 0 qualified, so Cypress does not guarantee performance at +150 °C. The specifications for 125 °C < TA 150 °C are best estimates
of the performance.
Document Number: 002-15106 Rev. *H
Page 14 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 4. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID
Typ
Max
Units
Details/
Conditions
1.7
2.2
mA
6 MHZ. Max is at
125 °C and 5.5 V.
2.2
2.5
0.7
0.9
mA
6 MHZ. Max is at
125 °C and 5.5 V.
1.0
1.2
mA
12 MHZ. Max is at
125 °C and 5.5 V.
2.5
60
µA
Max is at 3.6 V and
125 °C.
–
2.5
60
µA
Max is at 5.5 V and
125 °C.
I2C wakeup and WDT on
–
2.5
65
µA
Max is at 1.89 V
and 125 °C.
Supply current while XRES asserted
–
2
5
mA
–
Min
Typ
Max
Units
MHz
Parameter
Description
Min
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and Comparators on
–
SID25
IDD20
I2C wakeup, WDT, and Comparators on.
–
12 MHZ. Max is at
125 °C and 5.5 V.
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and Comparators on
–
SID28A
IDD23A
I2C wakeup, WDT, and Comparators on
–
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
I2C wakeup and WDT on
IDD26
–
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
I2C wakeup and WDT on
IDD29
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
XRES Current
SID307
IDD_XR
AC Specifications
Table 5. AC Specifications
Spec ID
Parameter
Description
SID48
FCPU
CPU frequency
DC
–
48
SID49[5]
TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[5]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
µs
Details/
Conditions
1.71 VDD 5.5
–
–
Notes
4. Guaranteed by characterization.
5. VIH must not exceed VDDD + 0.2 V.
Document Number: 002-15106 Rev. *H
Page 15 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
GPIO
Table 6. GPIO DC Specifications
Spec ID
Parameter
[6]
Description
Min
Typ
Max
Units
Details/Conditions
Input voltage high threshold
0.7 VDDD
–
–
CMOS Input
CMOS Input
SID57
VIH
SID58
VIL
Input voltage low threshold
–
–
0.3
VDDD
SID241
VIH[6]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[6]
LVTTL input, VDDD 2.7 V
2.0
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
–40 °C TA 125 °C
SID63A
RPULLUP
Pull-up resistor
3
–
–
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
–40 °C TA 125 °C
SID64A
RPULLDOWN
Pull-down resistor
3
–
–
125 °C TA 150 °C
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
25 °C, VDDD = 3.0 V
SID66
CIN
Input capacitance
–
–
7
pF
–
SID67[7]
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID67A[7] VHYSTTL
Input hysteresis LVTTL
7.5
–
–
SID68[7]
Input hysteresis CMOS
0.05 ×
VDDD
–
–
VDD < 4.5 V
200
–
–
VDD > 4.5 V
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Maximum total source or sink chip
current
–
–
200
mA
–
VHYSCMOS
SID68A[7] VHYSCMOS5V5 Input hysteresis CMOS
SID69[7]
IDIODE
SID69A[7] ITOT_GPIO
V
kΩ
–
–
125 °C TA 150 °C
VDDD 2.7 V, –40 °C TA
125 °C
mV
125 °C TA 150 °C
Notes
6. VIH must not exceed VDDD + 0.2 V.
7. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 16 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 7. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
3.3 V VDDD, Cload = 25 pF, –40 °C TA
125 °C
SID70A
TRISEF
Rise time in fast strong mode
–
–
25
3.3 V VDDD, Cload = 25 pF, 125 °C TA
150 °C
SID71
TFALLF
Fall time in fast strong mode
2
–
12
3.3 V VDDD, Cload = 25 pF, –40 °C TA
125 °C
SID71A
TFALLF
Fall time in fast strong mode
–
–
25
3.3 V VDDD, Cload = 25 pF, 125 °C TA
150 °C
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
3.3 V VDDD, Cload = 25 pF, –40 °C TA
125 °C
SID72A
TRISES
Rise time in slow strong mode
–
–
130
ns
3.3 V VDDD, Cload = 25 pF, 125 °C TA
150 °C
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
3.3 V VDDD, Cload = 25 pF, –40 °C TA
125 °C
SID73A
TFALLS
Fall time in slow strong mode
–
–
130
ns
3.3 V VDDD, Cload = 25 pF, 125 °C TA
150 °C
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
90/10%, 25-pF load, 60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25-pF load, 60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25-pF load, 60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
ns
MHz 90/10%, 25-pF load, 60/40 duty cycle
XRES
Table 8. XRES DC Specifications
Min
Typ
Max
SID77
Spec ID
VIH
Parameter
Input voltage high threshold
Description
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
SID80
CIN
Input capacitance
–
SID81[8]
VHYSXRES
Input voltage hysteresis
SID82
IDIODE
Current through protection diode to
VDD/VSS
Units
Details/Conditions
V
CMOS Input
–
kΩ
–
–
7
pF
–
–
100
–
mV
Typical hysteresis is 200 mV for
VDD > 4.5 V
–
–
100
µA
Min
Typ
Max
Units
1
–
–
µs
–
–
–
2.7
ms
–
–
Table 9. XRES AC Specifications
Spec ID
SID83[8]
Parameter
Description
TRESETWIDTH Reset pulse width
BID194[8] TRESETWAKE Wake-up time from reset release
Details/Conditions
Note
8. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 17 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Analog Peripherals
CTBm Opamp
Table 10. CTBm Opamp Specifications
Spec ID
Parameter
Description
IDD
Opamp block current, External
load
Min
Typ
Max
Units
Details/Conditions
SID269
IDD_HI
power = hi
–
1100
1850
–
SID270
IDD_MED
power = med
–
550
950
–40 °C TA 125 °C
SID270A
IDD_MED
power = med
–
–
1075
SID271
IDD_LOW
power = lo
–
150
350
–40 °C TA 125 °C
SID271A
IDD_LOW
power = lo
–
–
500
125 °C TA 150 °C
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power = hi
6
–
–
Input and output are
0.2 V to VDDA-0.2 V, –
40 °C TA 125 °C
SID272A
GBW_HI
power = hi
4.5
–
–
125 °C TA 150 °C
SID273
GBW_MED
power = med
3
–
–
SID273A
GBW_MED
power = med
–
3
–
125 °C TA 150 °C
SID274
GBW_LO
power = lo
–
1
–
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power = hi
10
–
–
Output is 0.5 V,
VDDA-0.5 V
SID276
IOUT_MAX_MID
power = mid
10
–
–
SID277
IOUT_MAX_LO
power = lo
–
5
–
Output is 0.5 V,
VDDA-0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power = hi
4
–
–
Output is 0.5 V,
VDDA-0.5 V
SID279
IOUT_MAX_MID
power = mid
4
–
–
SID280
IOUT_MAX_LO
power = lo
–
2
–
IDD_Int
Opamp block current Internal
Load
SID269_I
IDD_HI_Int
power = hi
–
1500
1700
SID270_I
IDD_MED_Int
power = med
–
700
900
SID271_I
IDD_LOW_Int
power = lo
–
–
–
GBW
VDDA = 2.7 V
GBW_HI_Int
power = hi
8
–
–
SID272_I
Document Number: 002-15106 Rev. *H
µA
MHz
mA
mA
125 °C TA 150 °C
Input and output are
0.2 V to VDDA-0.2 V, –
40 °C TA 125 °C
Output is 0.5 V,
VDDA-0.5 V
Output is 0.5 V,
VDDA-0.5 V
Output is 0.5 V,
VDDA-0.5 V
–
µA
–
–
MHz
Output is 0.25 V to
VDDA-0.25 V
Page 18 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 10. CTBm Opamp Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
SID282
VCM
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
VOUT
VDDA = 2.7 V
SID283
VOUT_1
power = hi, Iload = 10 mA
0.5
–
VDDA -0.5
SID284
VOUT_2
power = hi, Iload = 1 mA
0.2
–
VDDA -0.2
SID285
VOUT_3
power = med, Iload = 1 mA
0.2
–
VDDA -0.2
SID286
VOUT_4
power = lo, Iload = 0.1 mA
0.2
–
VDDA -0.2
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
SID288C
VOS_TR
–
V
–
–
–
V
–
–
High mode, input 0 V to
VDDA-0.2 V,
–40 °C TA 125 °C
Offset voltage, trimmed
–1.3
–
1.3
mV
High mode, input 0 V to
VDDA-0.2 V, 125 °C
TA 150 °C
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
Medium mode, input
0 V to VDDA-0.2 V
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
Low mode, input 0 V to
VDDA-0.2 V
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
SID290C
VOS_DR_TR
Offset voltage drift, trimmed
–15
–
15
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
High mode, –40 °C TA
125 °C
High mode, 125 °C TA
150 °C
µV/°C
Medium mode, –40 °C
TA 125 °C
Medium mode, 125 °C
TA 150 °C
SID290D
VOS_DR_TR
Offset voltage drift, trimmed
–
15
–
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
Low mode, –40 °C TA
SID290E
VOS_DR_TR
Offset voltage drift, trimmed
–
15
–
Low mode, 125 °C TA
SID291
CMRR
DC
70
80
–
125 °C
150 °C
dB
SID292
PSRR
At 1 kHz, 10-mV ripple
Document Number: 002-15106 Rev. *H
70
85
–
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
VDDD = 3.6 V,
high-power mode, input
is 0.2 V to VDDA-0.2 V
Page 19 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 10. CTBm Opamp Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Noise
SID294
VN2
Input-referred, 1 kHz,
power = Hi
–
72
–
Input and output are at
0.2 V to VDDA-0.2 V
SID295
VN3
Input-referred, 10 kHz,
power = Hi
–
28
–
Input and output are at
nV/rtHz 0.2 V to V
DDA-0.2 V
SID296
VN4
Input-referred, 100 kHz,
power = Hi
–
15
–
Input and output are at
0.2 V to VDDA-0.2 V
SID297
CLOAD
Stable up to max. load.
Performance specs at 50 pF.
–
–
125
pF
SID298
SLEW_RATE
Cload = 50 pF, Power = High,
VDDA = 2.7 V
6
–
–
V/µs
SID299
T_OP_WAKE
From disable to enable, no
external RC dominating
–
–
25
µs
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
COMP_MODE
Comparator mode; 50 mV drive,
Trise = Tfall (approx.)
SID300
TPD1
Response time; power = hi
–
150
–
SID301
TPD2
Response time; power = med
–
500
–
SID302
TPD3
Response time; power = lo
–
2500
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
SID304
WUP_CTB
Wake-up time from Enabled to
Usable
–
–
25
µs
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
25 °C
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
25 °C
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
200
–
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
25 °C
Document Number: 002-15106 Rev. *H
–
–
–
–
Input is 0.2 V to
VDDA-0.2 V
ns
Input is 0.2 V to
VDDA-0.2 V
Input is 0.2 V to
VDDA-0.2 V
µA
–
–
25 °C
25 °C
Page 20 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 10. CTBm Opamp Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
MHz
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
20-pF load,
no DC load 0.2 V to
VDDA-0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
With trim 25 °C,
0.2 V to VDDA-0.2 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
With trim 25 °C,
0.2 V to VDDA-0.2 V
SID_DS_15 VOS_LOW_M2
Mode 1, Low current
–
5
–
With trim 25 °C,
0.2 V to VDDA-0.2 V
mV
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
With trim 25 °C,
0.2V to VDDA-0.2 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
With trim 25 °C,
0.2 V to VDDA-0.2 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
With trim 25 °C,
0.2 V to VDDA-0.2 V
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
–
SID_DS_23 IOU_MED_M2
Mode 2, Medium current
–
1
–
–
SID_DS_24 IOU_LOW_M2
Mode 2, Low current
–
0.5
–
–
Document Number: 002-15106 Rev. *H
mA
Output is 0.5 V to
VDDA-0.5 V
Page 21 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Comparator
Table 11. Comparator DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Normal mode, –40 °C
TA 125 °C
SID84
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
SID84A
VOFFSET1
Input offset voltage, Factory trim
–
±15
–
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID85A
VOFFSET2
Input offset voltage, Custom trim
–
±4
–
125 °C TA 150 °C,
low power mode
125 °C TA 150 °C,
normal mode
mV
Low power mode, –
40 °C TA 125 °C
SID86
VHYST
Hysteresis when enabled
–
10
35
–40 °C TA 125 °C
SID86A
VHYST
Hysteresis when enabled
–
–
40
125 °C TA 150 °C
SID87
VICM1
Input common mode voltage in
normal mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in
ultra low power mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
VDDD ≥ 2.7 V, –40 °C
TA 125 °C
SID88B
CMRR
Common mode rejection ratio
–
50
–
VDDD ≥ 2.7 V; 125 °C
TA 150 °C
SID88A
CMRR
Common mode rejection ratio
42
–
–
VDDD ≤ 2.7 V, –40 °C
TA 125 °C
SID88C
CMRR
Common mode rejection ratio
–
42
–
VDDD ≤ 2.7 V; 125 °C
TA 150 °C
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power
mode
–
–
6
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
Min
Typ
Max
–
38
110
–
70
200
ns
–
2.3
15
µs
Modes 1 and 2
V
–
VDDD ≥ 2.2 V
at –40 °C
dB
–
µA
MΩ
–
VDDD ≥ 2.2 V
at –40 °C
–
Table 12. Comparator AC Specifications
Spec ID
Parameter
SID91
TRESP1
SID258
TRESP2
SID92
TRESP3
Description
Response time, normal mode, 50
mV overdrive
Response time, low power mode,
50 mV overdrive
Response time, ultra-low power
mode, 200 mV overdrive
Units
Details/Conditions
–
–
VDDD ≥ 2.2 V at –40 °C
Note
9. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 22 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Temperature Sensor
Table 13. Temperature Sensor Specifications
Spec ID
SID93
SID93A
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TSENSACC
Temperature sensor accuracy
–5
±1
5
°C
–40 to +85 °C
TSENSACC
Temperature sensor accuracy
–15
–
+15
°C
–85 to +150 °C
SAR ADC
Table 14. SAR ADC DC Specifications
Min
Typ
Max
Units
SID94
Spec ID
A_RES
Parameter
Resolution
Description
–
–
12
bits
Details/Conditions
SID95
A_CHNLS_S
Number of channels - single ended
–
–
8
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
SID97
A-MONO
Monotonicity
–
–
–
SID98
A_GAINERR
Gain error
–
–
±0.1
%
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
SID99A
A_OFFSET
Input offset voltage
–
–
2.7
mV
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
–
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
–
–
8 full speed.
Diff inputs use neighboring I/O
Yes.
With external reference.
Measured with 1-V
reference, –40 °C TA
125 °C
125 °C TA 150 °C
–
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
SID260
VREFSAR
Trimmed internal reference to SAR
–
–
TBD
V
–
Min
Typ
Max
Units
Details/Conditions
–
Measured at 1 V, –40 °C
TA 125 °C
125 °C TA 150 °C
Table 15. SAR ADC AC Specifications
Spec ID
Parameter
Description
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID107A
A_CMRR
Common mode rejection ratio
–
66
–
dB
SID108
A_SAMP
Sample rate
–
–
1
Msps
–40 °C TA 125 °C
SID108A
A_SAMP
–
–
0.375
Msps
SID109
A_SNR
65
–
–
dB
125 °C TA 150 °C
FIN = 10 kHz, –40 °C TA
125 °C
SID109A
A_SNR
–
65
–
dB
125 °C TA 150 °C
SID110
A_BW
–
–
A_samp/2
kHz
–
SID111
A_INL
–1.7
–
2
LSB
SID111A
A_INL
–1.5
–
1.7
LSB
SID111B
A_INL
–1.5
–
1.7
LSB
SID111C
A_INL
–4.5
–
3.3
LSB
SID111D
A_INL
Sample rate
Signal-to-noise and distortion ratio
(SINAD)
Signal-to-noise and distortion ratio
(SINAD)
Input bandwidth without aliasing
Integral non linearity.
VDD = 1.71 to 5.5, 1 Msps
Integral non linearity.
VDDD = 1.71 to 3.6, 1 Msps
Integral non linearity.
VDD = 1.71 to 5.5, 500 ksps
Integral non linearity. VDD = 4.5 to 5.5 V,
375 ksps
Integral non linearity.
VDD = 3 to 4.5 V, 300 ksps
–4.5
–
3.3
LSB
Document Number: 002-15106 Rev. *H
VREF = 1 to VDD, –40 °C
TA 125 °C
VREF = 1.71 to VDD, –40 °C
TA 125 °C
VREF = 1 to VDD, –40 °C
TA 125 °C
VREF = 1 to VDD, 125 °C
TA 150 °C
VREF = 1 to VDD, 125 °C
TA 150 °C
Page 23 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 15. SAR ADC AC Specifications (continued)
Spec ID
Parameter
SID111E
A_INL
SID112
A_DNL
SID112A
A_DNL
SID112B
A_DNL
SID112C
A_DNL
SID112D
A_DNL
SID112E
A_DNL
SID113
A_THD
Description
Integral non linearity.
VDD = 1.71 to 3 V, 150 ksps
Differential non linearity.
VDD = 1.71 to 5.5, 1 Msps
Differential non linearity.
VDD = 1.71 to 3.6, 1 Msps
Differential non linearity.
VDD = 1.71 to 5.5, 500 ksps
Differential non linearity. VDD = 4.5 to
5.5V, 375 ksps
Differential non linearity. VDD = 3 to
4.5 V, 300 ksps
Differential non linearity. VDD = 1.71 to
3 V, 150 ksps
Total harmonic distortion
Min
Typ
Max
Units
–4.5
–
3.4
LSB
–1
–
2.2
LSB
–1
–
2
LSB
–1
–
2.2
LSB
–1
–
3.2
LSB
–1
–
3.2
LSB
–1
–
3.3
LSB
–
–
–65
dB
SID113A
A_THD
Total harmonic distortion
–
–65
–
dB
SID261
FSARINTREF
SAR operating speed without external
reference bypass
–
–
100
ksps
Details/Conditions
VREF = 1 to VDD, 125 °C
TA 150 °C
VREF = 1 to VDD, –40 °C
TA 125 °C
VREF = 1.71 to VDD, –40 °C
TA 125 °C
VREF = 1 to VDD, –40 °C
TA 125 °C
VREF = 1 to VDD, 125 °C
TA 150 °C
VREF = 1 to VDD, 125 °C
TA 150 °C
VREF = 1 to VDD, 125 °C
TA 150 °C
Fin = 10 kHz
Fin = 10 kHz, 125 °C TA
150 °C
12-bit resolution
CSD and IDAC
Table 16. CSD and IDAC Specifications
Spec ID
Parameter
SYS.PER#3
VDD_RIPPLE
SYS.PER#16
VDD_RIPPLE_1.8
Description
Max allowed ripple on power
supply, DC to 10 MHz
Max allowed ripple on power
supply, DC to 10 MHz
Min
–
–
Typ
–
–
Max
±50
±25
Units
mV
mV
VDD > 1.75 V (with ripple),
25 °C TA, Parasitic
Capacitance (CP) <
20 pF,
Sensitivity ≥ 0.4 pF
µA
Maximum block current
for both IDACs in
dynamic (switching)
mode including comparators, buffer, and
reference generator.
SID.CSD.BLK ICSD
Maximum block current
–
–
4000
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
SID.CSD#15A VREF_EXT
External Voltage reference for
CSD and Comparator
0.6
SID.CSD#16
IDAC1IDD
IDAC1 (7 bits) block current
–
–
1750
SID.CSD#17
IDAC2IDD
IDAC2 (7 bits) block current
–
–
1750
SID308
VCSD
Voltage range of operation
1.71
–
5.5
SID308A
VCOMPIDAC
Voltage compliance range of
IDAC
0.6
–
VDDA –0.6
SID.CSD#15
VREF
Document Number: 002-15106 Rev. *H
Details/Conditions
VDD > 2 V (with ripple),
25 °C TA,
Sensitivity = 0.1 pF
V
VDDA - 0.6
µA
V
VDDA - 0.06 or 4.4,
whichever is lower
VDDA - 0.06 or 4.4,
whichever is lower
–
–
1.8 V ±5% or 1.8 V to
5.5 V
VDDA - 0.06 or 4.4,
whichever is lower
Page 24 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 16. CSD and IDAC Specifications (continued)
Min
Typ
Max
SID309
Spec ID
IDAC1DNL
Parameter
DNL
Description
–1
–
1
Units
Details/Conditions
SID310
IDAC1INL
INL
–3
–
3
DNL
–1
–
1
INL
–3
–
3
INL is ±5 LSB for
VDDA < 2 V, –40 °C TA
125 °C
125 °C TA 150 °C
INL is ±5 LSB for
VDDA < 2 V
SID311
IDAC2DNL
SID312
IDAC2INL
SID312A
IDAC2INL
INL
–
–
7
SID313
SNR
Ratio of counts of finger to
noise. Guaranteed by characterization
5
–
–
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits)
in low range
4.2
–
5.2
LSB = 37.5-nA typ
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits)
in medium range
34
–
41
LSB = 300-nA typ
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits)
in high range
275
–
330
LSB = 2.4-µA typ
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits)
in low range, 2X mode
8
–
10.5
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits)
in medium range, 2X mode
69
–
82
LSB = 300-nA typ. 2X
output stage
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits)
in high range, 2X mode
540
–
660
LSB = 2.4-µA typ.2X
output stage
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits)
in low range
4.2
–
5.2
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits)
in medium range
34
–
41
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits)
in high range
275
–
330
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits)
in low range, 2X mode
8
–
10.5
LSB = 37.5-nA typ. 2X
output stage
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits)
in medium range, 2X mode
69
–
82
LSB = 300-nA typ. 2X
output stage
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits)
in high range, 2X mode
540
–
660
LSB = 2.4-µA typ. 2X
output stage
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit
mode in low range
8
–
10.5
LSB = 37.5-nA typ
SID315G
IDAC3CRT23
Output current of IDAC in 8-bit
mode in medium range
69
–
82
LSB = 300-nA typ
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit
mode in high range
540
–
660
LSB = 2.4-µA typ
SID320
IDACOFFSET
All zeroes input
–
–
1
Polarity set by Source or
LSB Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
SID321A
IDACGAIN
Full-scale error less offset
–
–
±11
Document Number: 002-15106 Rev. *H
LSB
–
µA
µA
%
Capacitance range of 5 to
35 pF, 0.1-pF sensitivity.
All use cases. VDDA > 2 V
LSB = 37.5-nA typ. 2X
output stage
–40 °C TA 125 °C
125 °C TA 150 °C
Page 25 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 16. CSD and IDAC Specifications (continued)
Description
Min
Typ
Max
SID322
Spec ID
IDACMISMATCH1
Parameter
Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
4.6
Units
Details/Conditions
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
2.3
LSB = 2.4 µA typ, –40 °C
TA 125 °C
SID322C
IDACMISMATCH4
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.3
125 °C TA 150 °C
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit
IDAC
–
–
10
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit
IDAC
–
–
10
SID325
CMOD
External modulator capacitor
–
2.2
–
nF
µs
Full-scale transition.
No external load.
5-V rating, X7R or NP0
cap
10-bit CapSense ADC
Table 17. 10-bit CapSense ADC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
bits
Details/Conditions
Auto-zeroing is required
every millisecond
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±2
%
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
SIDA101
A_VINS
Input voltage range - single
ended
SIDA103
A_INRES
SIDA104
Defined by AMUX Bus.
–
–
–
VSSA
–
VDDA
V
Input resistance
–
2.2
–
KΩ
–
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
µs
Does not include
acquisition time.
Equivalent to 44.8 ksps
including acquisition time.
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
µs
Does not include
acquisition time.
Equivalent to 11.6 ksps
including acquisition time.
A_SND
Signal-to-noise and Distortion
ratio (SINAD)
dB
With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA108
SIDA108A
SIDA109
Document Number: 002-15106 Rev. *H
–
–
61
–
–
–
21.3
85.3
–
Page 26 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 17. 10-bit CapSense ADC Specifications (continued)
Spec ID
SIDA110
Parameter
A_BW
Description
Input bandwidth without aliasing
Min
–
Typ
–
Max
22.4
Units
Details/Conditions
kHz 8-bit resolution
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB VREF = 2.4 V or greater
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB –
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 18. TCPWM Specifications
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Units
Details/Conditions
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
All modes (TCPWM)
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
2/Fc
–
–
For all trigger events[10]
SID.TCPWM.5
TPWMEXT
Output trigger pulse widths
2/Fc
–
–
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
MHz
ns
Minimum time between
successive counts
I2C
Table 19. Fixed I2C DC Specifications[11]
Spec ID
Parameter
Units
Details/Conditions
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
–
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
–
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
–
Min
Typ
Max
–
–
1
µA
–
Table 20. Fixed I2C AC Specifications[11]
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Units
Details/Conditions
Msps –
Note
10. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Document Number: 002-15106 Rev. *H
Page 27 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
SPI
Table 21. SPI DC Specifications[11]
Spec ID
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
Units
Details/Conditions
–
µA
–
–
Table 22. SPI AC Specifications[11]
Spec ID
SID166
Parameter
FSPI
Description
Min
Typ
Max
Units
SPI Operating frequency (Master; 6X
Oversampling)
–
–
8
MHz
Details/Conditions
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
SID168
TDSI
MISO Valid before SClock capturing
edge
–
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
Referred to Slave capturing
edge
–
ns
Full clock, late MISO
sampling
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
SID172A
TSSELSSCK
SSEL Valid to first SCK valid edge
–
–
100
ns
TCPU = 1/FCPU
–
–
ns
–
Note
11. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 28 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
UART
Table 23. UART DC Specifications[12]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
–
Min
Typ
Max
Units
–
–
1
Min
Typ
Max
Table 24. UART AC Specifications[12]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Details/Conditions
Mbps –
LCD
Table 25. LCD Direct Drive DC Specifications[12]
Spec ID
Parameter
Description
Units
Details/Conditions
5
–
µA
16 4 small segment disp. at
50 Hz
500
5000
pF
–
20
–
mV
–
2
–
2
–
Min
Typ
Max
Units
10
50
150
Hz
SID154
ILCDLOW
Operating current in low power mode
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating current Vbias
=5V
–
SID158
ILCDOP2
LCD system operating current Vbias
= 3.3 V
–
–
mA
32 4 segments. 50 Hz.
25 °C
32 4 segments. 50 Hz.
25 °C
Table 26. LCD Direct Drive AC Specifications[12]
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Details/Conditions
–
Note
12. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 29 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Memory
Flash
Table 27. Flash DC Specifications
Spec ID
Parameter
SID173
VPE
Description
Erase and program voltage
Min
Typ
Max
Units
1.71
–
5.5
V
Min
Typ
Max
Details/Conditions
–
Table 28. Flash AC Specifications
Spec ID
Parameter
Description
Units
Details/Conditions
SID174
TROWWRITE[13]
Row (block) write time
(erase and program)
–
–
20
SID175
TROWERASE[13]
Row erase time
–
–
16
SID176
TROWPROGRAM[13] Row program time after erase
–
–
4
SID178
Bulk erase time (64 KB)
–
–
35
–
SID180[14]
TBULKERASE[13]
TDEVPROG[13]
Total device program time
–
–
7
Seconds –
SID181[14]
FEND
Flash endurance
100 K
–
–
Cycles –
FRET
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
SID182A[14, 15] FRET
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
–
CPU execution from
Flash
Min
Typ
Max
Units
1
–
67
V/ms
SID182[14, 15]
Row (block) =
128 bytes
ms
–
–
–
Years
–
System Resources
Power-on Reset (POR)
Table 29. Power On Reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER
Power supply slew rate
SID185[14]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
SID186[14]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
BOD trip voltage in active and
sleep modes
1.48
–
1.62
BOD trip voltage in Deep Sleep
1.11
V
Details/Conditions
On power-up &
power-down
–
–
Table 30. Brown-out Detect (BOD) for VCCD
Spec ID
SID190[14]
SID192[14]
Parameter
VFALLPPOR
VFALLDPSLP
Description
Units
Details/Conditions
–
V
–
1.5
–
Notes
13. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
14. Guaranteed by characterization.
15. Cypress provides a retention calculator to calculate the retention lifetime based on the customers' individual temperature profiles for operation over the –40 °C to
+150 °C ambient temperature range. Contact cytechsupport@cypress.com.
Document Number: 002-15106 Rev. *H
Page 30 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
SWD Interface
Table 31. SWD Interface Specifications
Spec ID
SID213
Parameter
F_SWDCLK1
Description
Min
Typ
Max
–
–
14
3.3 V VDD 5.5 V
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
MHz
SID214
F_SWDCLK2
SID215[16]
SID216[16]
SID217[16]
SID217A[16]
1.71 V VDD 3.3 V
SWDCLK ≤ 1/3 CPU
clock frequency
–
–
7
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
T_SWDI_HOLD
0.25*T
–
–
–
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
Min
Typ
Max
Units
T = 1/f SWDCLK
ns
–
–
Internal Main Oscillator
Table 32. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Description
Min
Typ
Max
Units
Details/Conditions
Table 33. IMO AC Specifications
Spec ID
Parameter
SID223
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2
%
–40 °C TA 125 °C
SID223A
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±4
%
125 °C TA 150 °C
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Units
–
0.3
1.05
µA
Min
Typ
Max
Units
–
–
2
ms
Internal Low-Speed Oscillator
Table 34. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
SID231[16] IILO1
Description
ILO operating current
Details/Conditions
–
Table 35. ILO AC Specifications
Spec ID
SID234[16]
Parameter
Description
Details/Conditions
TSTARTILO1
ILO startup time
SID236[16]
–
TILODUTY
ILO duty cycle
40
50
60
%
–
SID237
FILOTRIM1
ILO frequency range
20
40
80
kHz
–
Note
16. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 31 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Watch Crystal Oscillator
Table 36. Watch Crystal Oscillator Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID398
FWCO
Crystal frequency
–
32.768
–
kHz
–
SID399
FTOL
Frequency tolerance
–
50
250
ppm
With 20-ppm crystal
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive Level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal load capacitance
6
–
12.5
pF
–
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating current (high power mode)
–
–
8
µA
–
SID406
IWCO2
Operating current (low power mode)
–
–
1
µA
–
Min
Typ
Max
Units
External Clock
Table 37. External Clock Specifications
Spec ID
SID305[17]
Parameter
Description
Details/Conditions
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[17] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Units
3
–
4
Min
Typ
Max
Units
–
–
1.6
ns
Block
Table 38. Block Specs
Spec ID
SID262[17]
Parameter
TCLKSWITCH
Description
System clock source switching time
Details/Conditions
Periods –
PRGIO Pass-through Time
Table 39. PRGIO Pass-through Time (Delay in Bypass Mode)
Spec ID
SID252
Parameter
Description
Max. delay added by PRGIO in bypass
PRG_BYPASS
mode
Details/Conditions
–
Note
17. Guaranteed by characterization.
Document Number: 002-15106 Rev. *H
Page 32 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Ordering Information
Table 40 lists the marketing part numbers for the PSoC 4100S family.
Table 40. Ordering Information
4125
4146
4124
4125
28-SSOP
40-QFN
-40 to +85 °C
-40 to +105 °C
-40 to +125 °C
16
4
2
X
X
–
2
5
2
16
24
X
–
X
–
–
16
4
2
X
X
–
2
5
2
16
34
–
X
X
–
–
SCB Blocks
24
24
CSD
CY8C4124PVA-S412
CY8C4124LQA-S413
SRAM (KB)
GPIO
TCPWM Blocks
LP Comparators
12-bit SAR ADC
Direct LCD Drive
Opamp (CTBm)
Packages Operating Temp
Smart IOs
4124
MPN
Flash (KB)
Category
Max CPU Speed (MHz)
Features
CY8C4124PVA-S422
24
16
4
2
–
X
806 ksps
2
5
2
16
24
X
–
X
–
–
CY8C4124LQA-S423
24
16
4
2
–
X
806 ksps
2
5
2
16
34
–
X
X
–
–
CY8C4124PVA-S432
24
16
4
2
X
X
806 ksps
2
5
2
16
24
X
–
X
–
–
CY8C4124LQA-S433
24
16
4
2
X
X
806 ksps
2
5
2
16
34
–
X
X
–
–
CY8C4125PVA-S412
24
32
4
2
X
X
–
2
5
2
16
24
X
–
X
–
–
CY8C4125LQA-S413
24
32
4
2
X
X
–
2
5
2
16
34
–
X
X
–
–
CY8C4125PVA-S422
24
32
4
2
–
X
806 ksps
2
5
2
16
24
X
–
X
–
–
CY8C4125LQA-S423
24
32
4
2
–
X
806 ksps
2
5
2
16
34
–
X
X
–
–
CY8C4125PVA-S432
24
32
4
2
X
X
806 ksps
2
5
2
16
24
X
–
X
–
–
CY8C4125LQA-S433
24
32
4
2
X
X
806 ksps
2
5
2
16
34
–
X
X
–
–
CY8C4146PVA-S422
48
64
8
2
–
X
1000 ksps
2
5
2
16
24
X
–
X
–
–
CY8C4146LQA-S423
48
64
8
2
–
X
1000 ksps
2
5
3
16
34
–
X
X
–
–
CY8C4146PVA-S432
48
64
8
2
X
X
1000 ksps
2
5
3
16
24
X
–
X
–
–
CY8C4146LQA-S433
48
64
8
2
X
X
1000 ksps
2
5
3
16
34
–
X
X
–
–
CY8C4124PVS-S412
24
16
4
2
X
X
–
2
5
2
16
24
X
–
–
X
–
CY8C4124LQS-S413
24
16
4
2
X
X
–
2
5
2
16
34
–
X
–
X
–
CY8C4124PVS-S422
24
16
4
2
–
X
806 ksps
2
5
2
16
24
X
–
–
X
–
CY8C4124LQS-S423
24
16
4
2
–
X
806 ksps
2
5
2
16
34
–
X
–
X
–
CY8C4124PVS-S432
24
16
4
2
X
X
806 ksps
2
5
2
16
24
X
–
–
X
–
CY8C4124LQS-S433
24
16
4
2
X
X
806 ksps
2
5
2
16
34
–
X
–
X
–
CY8C4125PVS-S412
24
32
4
2
X
X
–
2
5
2
16
24
X
–
–
X
–
CY8C4125LQS-S413
24
32
4
2
X
X
–
2
5
2
16
34
–
X
–
X
–
CY8C4125PVS-S422
24
32
4
2
–
X
806 ksps
2
5
2
16
24
X
–
–
X
–
CY8C4125LQS-S423
24
32
4
2
–
X
806 ksps
2
5
2
16
34
–
X
–
X
–
CY8C4125PVS-S432
24
32
4
2
X
X
806 ksps
2
5
2
16
24
X
–
–
X
–
CY8C4125LQS-S433
24
32
4
2
X
X
806 ksps
2
5
2
16
34
–
X
–
X
–
Document Number: 002-15106 Rev. *H
Page 33 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 40. Ordering Information (continued)
4124
4125
4146
5
2
16
2
–
X
1000 ksps
2
5
3
16
2
X
X
1000 ksps
2
5
3
16
-40 to +125 °C
2
-40 to +105 °C
1000 ksps
-40 to +85 °C
8
X
40-QFN
8
64
–
28-SSOP
64
48
2
GPIO
48
CY8C4146PVS-S432
Smart IOs
CY8C4146LQS-S423
SCB Blocks
8
TCPWM Blocks
64
LP Comparators
48
12-bit SAR ADC
SRAM (KB)
CY8C4146PVS-S422
Direct LCD Drive
Flash (KB)
4146
CSD
MPN
Packages Operating Temp
Opamp (CTBm)
Category
Max CPU Speed (MHz)
Features
24
X
–
–
X
–
34
–
X
–
X
–
24
X
–
X
–
CY8C4146LQS-S433
48
64
8
2
X
X
1000 ksps
2
5
3
16
34
–
X
–
X
–
CY8C4124PVE-S412
24
16
4
2
X
X
–
2
5
2
16
24
X
–
–
–
X
CY8C4124LQE-S413
24
16
4
2
X
X
–
2
5
2
16
34
–
X
–
–
X
CY8C4124PVE-S422
24
16
4
2
–
X
806 ksps
2
5
2
16
24
X
–
–
–
X
CY8C4124LQE-S423
24
16
4
2
–
X
806 ksps
2
5
2
16
34
–
X
–
–
X
CY8C4124PVE-S432
24
16
4
2
X
X
806 ksps
2
5
2
16
24
X
–
–
–
X
CY8C4124LQE-S433
24
16
4
2
X
X
806 ksps
2
5
2
16
34
–
X
–
–
X
CY8C4125PVE-S412
24
32
4
2
X
X
–
2
5
2
16
24
X
–
–
–
X
CY8C4125LQE-S413
24
32
4
2
X
X
–
2
5
2
16
34
–
X
–
–
X
CY8C4125PVE-S422
24
32
4
2
–
X
806 ksps
2
5
2
16
24
X
–
–
–
X
CY8C4125LQE-S423
24
32
4
2
–
X
806 ksps
2
5
2
16
34
–
X
–
–
X
CY8C4125PVE-S432
24
32
4
2
X
X
806 ksps
2
5
2
16
24
X
–
–
–
X
CY8C4125LQE-S433
24
32
4
2
X
X
806 ksps
2
5
2
16
34
–
X
–
–
X
CY8C4146PVE-S422
48
64
8
2
–
X
1000 ksps
2
5
2
16
24
X
–
–
–
X
CY8C4146LQE-S423
48
64
8
2
–
X
1000 ksps
2
5
3
16
34
–
X
–
–
X
CY8C4146PVE-S432
48
64
8
2
X
X
1000 ksps
2
5
3
16
24
X
–
–
–
X
CY8C4146LQE-S433
48
64
8
2
X
X
1000 ksps
2
5
3
16
34
–
X
–
–
X
Document Number: 002-15106 Rev. *H
Page 34 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
Cypress Prefix
4
Architecture
4
PSoC 4
A
Family
0
4000 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
C
Values
Flash Capacity
DE
Package Code
F
Temperature Range
S
Silicon Family
XYZ
Attributes Code
Meaning
LQ
QFN
PV
SSOP
A
S
E
Automotive (AEC-Q100: –40 °C to +85 °C)
Automotive (AEC-Q100: –40 °C to +105 °C)
Automotive (AEC-Q100: –40 °C to +125 °C)
S
PSoC 4A-S1, PSoC 4A-S2
M
PSoC 4A-M
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C
4
A
B
C
DE
F
S
XYZ
T
T = Tape and Reel
Attributes Code
Silicon Family
Temperature Range
Package Code
Flash Capacity
CPU Speed
Family within Architecture
Architecture
Cypress Prefix
Example
4: PSoC 4
2: 4200 Family
4: 48 MHz
5: 32 KB
PV: SSOP
A, S, E: Automotive
Document Number: 002-15106 Rev. *H
Page 35 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Packaging Information
The PSoC 4100S will be offered in 28-pin SSOP and 40-pin QFN packages.
Table 41 provides the package dimensions and Cypress drawing numbers.
Table 41. Package List
Spec ID
Package
BID27
40-pin QFN
BID28
28-pin SSOP
Description
Package Drawing
6 × 6 × 0.6 mm height with 0.5-mm pitch
002-16818
28LD SSOP 210 MILS O28.21
51-85079
Table 42. Package Thermal Characteristics
Parameter
TA
Description
Package
Conditions
Min
Typ
Max
–
For A-grade devices
–40
25
85
–
For S-grade devices
–40
25
105
–
For E-grade devices
–40
25
125
Operating Ambient temperature
–
For A-grade devices
–40
–
100
–
For S-grade devices
–40
–
120
–
For E-grade devices
–40
–
140
40-pin QFN
–
–
17.8
–
Units
°C
TJ
Operating Junction temperature
TJA
Package θJA
TJC
Package θJC
40-pin QFN
–
–
2.8
–
°C/Watt
TJA
Package θJA
28-pin SSOP
–
–
66.58
–
°C/Watt
TJC
Package θJC
28-pin SSOP
–
–
46.28
–
°C/Watt
°C
°C/Watt
Table 43. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 44. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-15106 Rev. *H
Page 36 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Package Diagrams
Figure 6. 40-pin QFN (6.0 × 6.0 × 0.6 mm) LD40A 4.6 × 4.6 mm E-Pad (Sawn) Package Outline, 002-16818
002-16818 *B
Document Number: 002-15106 Rev. *H
Page 37 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Figure 7. 28-pin SSOP (210 Mils) Package Outline, 51-85079
51-85079 *G
Document Number: 002-15106 Rev. *H
Page 38 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Acronyms
Table 45. Acronyms Used in this Document
Acronym
Description
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
abus
analog local bus
GPIO
general-purpose input/output, applies to a PSoC
pin
ADC
analog-to-digital converter
HVI
high-voltage interrupt, see also LVI, LVD
AG
analog global
IC
integrated circuit
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an Arm data
transfer bus
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
ALU
arithmetic logic unit
I2C, or IIC
Inter-Integrated Circuit, a communications
protocol
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
AMUXBUS analog multiplexer bus
API
application programming interface
APSR
application program status register
Arm®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
DAC
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
digital-to-analog converter, see also IDAC, VDAC
LIN
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Local Interconnect Network, a communications
protocol.
LR
link register
DMIPS
Dhrystone million instructions per second
LUT
lookup table
DMA
direct memory access, see also TD
LVD
low-voltage detect, see also LVI
DNL
differential nonlinearity, see also INL
LVI
low-voltage interrupt, see also HVI
DNU
do not use
LVTTL
low-voltage transistor-transistor logic
DR
port write data registers
MAC
multiply-accumulate
DSI
digital system interconnect
MCU
microcontroller unit
DWT
data watchpoint and trace
MISO
master-in slave-out
ECC
error correcting code
NC
no connect
ECO
external crystal oscillator
NMI
nonmaskable interrupt
EEPROM
electrically erasable programmable read-only
memory
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
EMI
electromagnetic interference
NVL
nonvolatile latch, see also WOL
EMIF
external memory interface
opamp
operational amplifier
EOC
end of conversion
PC
program counter
EOF
end of frame
PCB
printed circuit board
EPSR
execution program status register
PGA
programmable gain amplifier
ESD
electrostatic discharge
PHUB
peripheral hub
ETM
embedded trace macrocell
PHY
physical layer
FPB
flash patch and breakpoint
PICU
port interrupt control unit
Document Number: 002-15106 Rev. *H
Page 39 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
PLL
phase-locked loop
UDB
universal digital block
PMDD
package material declaration data sheet
USB
Universal Serial Bus
POR
power-on reset
USBIO
USB input/output, PSoC pins used to connect to a
USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
Document Number: 002-15106 Rev. *H
Page 40 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Document Conventions
Units of Measure
Table 46. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-15106 Rev. *H
Page 41 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Document History Page
Description Title: Automotive PSoC® 4: PSoC 4100S Family Datasheet, Programmable System-on-Chip (PSoC®)
Document Number: 002-15106
Submission
Date
Revision
ECN
**
5351404
07/18/2016 New data sheet.
*A
5526020
Updated Logic Block Diagram.
Updated Figure 1.
Updated Packaging Information:
11/18/2016
Updated Package Diagrams:
Removed spec 001-80659 *A.
Added spec 002-16818 **.
*B
5621318
02/06/2017
5753750
Changed datasheet status to Final.
Added Note 1 for E-grade temperature range. Added new specs for the device usage at 150C
temperature range.
05/30/2017 Added SID67A, SID277A, SID107A, SID108A, SID111C, SID111D, SID111E,
SID112C, SID112D, SID112E, SID113A
Removed SID93A
Updated max value for SID321A
*D
6127588
Updated Note 1.
Updated DC Specifications - Updated typ and max values for SID10, SID16, SID19, SID22,
04/09/2018 SID25, SID28, SID28A, SID31, SID34, SID37, and SID307.
Added Note 3 under Device-Level Specifications.
Updated Ordering Information.
*E
6183759
05/23/2018
*F
6554816
04/24/2019 Removed Errata.
*G
6834892
05/04/2020
*H
6974789
Updated SID.CLK#6 parameter.
09/29/2020 Updated conditions for Device-Level Specifications.
Refer to Product Information Notice #6965423.
*C
Document Number: 002-15106 Rev. *H
Description of Change
Changed status from Advance to Preliminary.
Updated to new template.
Added Errata.
Updated SID64A, SID113, and SID113A specs.
Updated Ordering Information.
Updated Sales, Solutions, and Legal Information and Copyright year.
Page 42 of 43
Automotive PSoC® 4: PSoC 4100S
Family Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
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Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
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cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2016-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-15106 Rev. *H
Revised September 29, 2020
Page 43 of 43
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