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S6E1A Series
32-bit Arm® Cortex®-M0+
FM0+ Microcontroller
The S6E1A Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power
consumption and low cost.
This series has the Arm Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as
various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL
MANUAL".
Features
CSIO
32-bit Arm Cortex-M0+ Core
Full
duplex double buffer
dedicated baud rate generator
Overrun error detection function
Serial chip select function (ch.1 and ch.3 only)
Data length: 5 to 16 bits
Processor version: r0p1
Built-in
Maximum operating frequency: 40 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI
(non-maskable interrupt) and 32 peripheral interrupt with 4
selectable interrupt priority levels
LIN
LIN
protocol Rev.2.1 supported
duplex double buffer
Master/Slave mode supported
LIN break field generation function (The length is variable
between 13 bits and 16 bits.)
LIN break delimiter generation function (The length is
variable between 1 bit and 4 bits.)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
24-bit System timer (Sys Tick): System timer for OS task
Full
management
Bit Band operation
Compatible with Cortex-M3 bit band operation
On-Chip Memories
Flash memory
I2 C
Up
to 88 Kbyte
Read cycle:0 wait-cycle
Security function for code protection
Standard-mode
(Max: 100 kbps) supported / Fast-mode
(Max 400kbps) supported.
SRAM
The on-chip SRAM of this series has one independent SRAM.
SRAM: 6 Kbyte
Multi-function Serial Interface (Max 3channels)
128 bytes with FIFO in all channels (The number of FIFO
steps varies depending on the settings of the communication
mode or bit length.)
The operation mode of each channel can be selected from
one of the following.
UART
CSIO
LIN
I2 C
UART
Full
duplex double buffer
can be enabled or disabled.
Built-in dedicated baud rate generator
External clock available as a serial clock
Parity
Various error detection functions (parity errors, framing errors,
and overrun errors)
Cypress Semiconductor Corporation
Document Number: 002-05091 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 24, 2019
S6E1A Series
A/D Converter (Max: 8 channels)
12-bit A/D Converter
Successive
approximation type
Conversion time: 0.8 μs @ 5 V (S6E1A1xC0A) / 2.0 μs
(S6E1A1xB0A)
Priority conversion available (2 levels of priority)
Scan conversion mode
Built-in FIFO for conversion data storage (for scan
conversion: 16 steps, for priority conversion: 4 steps)
Base Timer (Max: 4 channels)
The operation mode of each channel can be selected from one
of the following.
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. In addition, it
can be used as an up/down counter.
The detection edge for the three external event input pins
AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Multi-function Timer
16-bit PWM timer
The Multi-function Timer consists of the following blocks.
16-bit PPG timer
16-bit free-run timer × 3 channels
16/32-bit reload timer
Input capture × 4 channels
16/32-bit PWC timer
Output compare × 6 channels
General-purpose I/O Port
ADC start compare × 6 channel
This series can use its pin as a general-purpose I/O port when
it is not used for an external bus or a peripheral function. All
ports can be set to fast general-purpose I/O ports or slow
general-purpose I/O ports. In addition, this series has a port
relocate function that can set to which I/O port a peripheral
function can be allocated.
Waveform generator × 3 channels
All ports are Fast GPIO which can be accessed by 1cycle
PWM signal output function
Capable of controlling the pull-up of each pin
DC chopper waveform output function
Capable of reading pin level directly
Dead time function
Port relocate function
Input capture function
Up to 37 fast general-purpose I/O ports @48pin package
ADC start function
Certain ports are 5 V tolerant.
DTIF (motor emergency stop) interrupt function
See "3. Pin Assignment" and "5. I/O Circuit Type" for details
of such pins.
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down
counters. The operation mode of each timer channel can be
selected from one of the following.
Free-running mode
Periodic mode (= Reload mode)
One-shot mode
16-bit PPG timer × 3 channels
IGBT mode is contained.
The following function can be used to achieve the motor
control.
Real-time Clock (RTC)
The Real-time Clock counts
year/month/day/hour/minute/second/day of the week from year
00 to year 99.
The RTC can generate an interrupt at a specific time
(year/month/day/hour/minute) and can also generate an
interrupt in a specific year, in a specific month, on a specific
day, at a specific hour or at a specific minute.
It has a timer interrupt function generating an interrupt upon
a specific time or at specific intervals.
It can keep counting while rewriting the time.
It can count leap years automatically.
Document Number: 002-05091 Rev. *D
Page 2 of 97
S6E1A Series
Watch Counter
The Watch Counter wakes up the microcontroller from the low
power consumption mode. The clock source can be selected
from the main clock, the sub clock, the built-in high-speed CR
clock or the built-in low-speed CR clock.
Low-voltage Detector (LVD)
Interval timer: up to 64 s (sub clock: 32.768 kHz)
LVD1: error reporting via an interrupt
This series monitors the voltage on the VCC pin with a 2-stage
mechanism. When the voltage falls below a designated voltage,
the Low-voltage Detector generates an interrupt or a reset.
External Interrupt Controller Unit
LVD2: auto-reset operation
Up to 8 external interrupt input pins
Low Power Consumption Mode
Non-maskable interrupt (NMI) input pin: 1
This series has four low power consumption modes.
SLEEP
Watchdog Timer (2 channels)
The watchdog timer generates an interrupt or a reset when the
counter reaches a time-out value.
TIMER
RTC
This series consists of two different watchdogs, "hardware"
watchdog and "software" watchdog.
STOP
The "hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "hardware" watchdog
is active in any low-power consumption modes except RTC
mode and STOP mode.
Peripheral Clock Gating
Clock and Reset
Debug
Clocks
Serial Wire Debug Port (SW-DP)
A clock can be selected from five clock sources (two external
oscillators, two built-in CR oscillator, and main PLL).
Main clock
: 4 MHz to 40MHz
Sub clock
: 32.768 kHz
Built-in high-speed CR clock
: 4 MHz
Built-in low-speed CR clock
: 100 kHz
Main PLL clock
Micro Trace Buffer (MTB)
Resets
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
Unique ID
A 41-bit unique value of the device has been set.
Power Supply
Wide voltage range: VCC = 2.7 V to 5.5 V
Reset
request from the INITX pin
on reset
Software reset
Watchdog timer reset
Low-voltage detection reset
Clock supervisor reset
Power
Clock Supervisor (CSV)
The Clock Supervisor monitors the failure of external clocks
with a clock generated by a built-in CR oscillator.
If an external clock failure (clock stop) is detected, a reset is
asserted.
If an external frequency anomaly is detected, an interrupt or
a reset is asserted.
Document Number: 002-05091 Rev. *D
Page 3 of 97
S6E1A Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. Pin Descriptions .............................................................................................................................................................. 13
5. I/O Circuit Type ............................................................................................................................................................... 24
6. Handling Precautions ..................................................................................................................................................... 30
6.1
Precautions for Product Design ................................................................................................................................... 30
6.2
Precautions for Package Mounting .............................................................................................................................. 31
6.3
Precautions for Use Environment ................................................................................................................................ 33
7. Handling Devices ............................................................................................................................................................ 34
8. Block Diagram ................................................................................................................................................................. 37
9. Memory Size .................................................................................................................................................................... 38
10. Memory Map .................................................................................................................................................................... 38
11. Pin Status in Each CPU State ........................................................................................................................................ 41
12. Electrical Characteristics ............................................................................................................................................... 45
12.1 Absolute Maximum Ratings ......................................................................................................................................... 45
12.2 Recommended Operating Conditions ......................................................................................................................... 46
12.3 DC Characteristics ...................................................................................................................................................... 47
12.3.1 Current Rating .............................................................................................................................................................. 47
12.3.2 Pin Characteristics ....................................................................................................................................................... 50
12.4 AC Characteristics ....................................................................................................................................................... 51
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 51
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 52
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 53
12.4.4 Operating Conditions of Main PLL (In the case of using the main clock as the input clock of the PLL) ....................... 54
12.4.5 Operating Conditions of Main PLL
(In the case of using the built-in high-speed CR clock as the input clock of the main PLL) .......................................... 54
12.4.6 Reset Input Characteristics .......................................................................................................................................... 55
12.4.7 Power-on Reset Timing ................................................................................................................................................ 55
12.4.8 Base Timer Input Timing .............................................................................................................................................. 56
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 57
12.4.10 External Input Timing ................................................................................................................................................ 73
12.4.11 QPRC Timing ........................................................................................................................................................... 74
12.4.12 I2C Timing ................................................................................................................................................................. 76
12.4.13 SW-DP Timing .......................................................................................................................................................... 77
12.5 12-bit A/D Converter .................................................................................................................................................... 78
12.6 Low-voltage Detection Characteristics ........................................................................................................................ 81
12.6.1 Low-voltage Detection Reset ....................................................................................................................................... 81
12.6.2 Low-voltage Detection Interrupt ................................................................................................................................... 82
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 83
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 84
12.8.1 Return Factor: Interrupt ................................................................................................................................................ 84
12.8.2 Return Factor: Reset .................................................................................................................................................... 86
13. Ordering Information ...................................................................................................................................................... 88
14. Package Dimensions ...................................................................................................................................................... 89
15. Major Changes ................................................................................................................................................................ 94
Document Number: 002-05091 Rev. *D
Page 4 of 97
S6E1A Series
Document History ................................................................................................................................................................. 96
Sales, Solutions, and Legal Information ............................................................................................................................. 97
Document Number: 002-05091 Rev. *D
Page 5 of 97
S6E1A Series
1. Product Lineup
Memory Size
S6E1A11B0A
S6E1A11C0A
56 Kbyte
6 Kbyte
Product name
On-chip Flash memory
On-chip SRAM
S6E1A12B0A
S6E1A12C0A
88 Kbyte
6 Kbyte
Function
S6E1A11B0A
S6E1A12B0A
32
Product name
Pin count
Cortex-M0+
40 MHz
2.7 V to 5.5 V
3 ch. (Max)
ch.0/ch.1/ch.3: FIFO
CPU
Frequency
Power supply voltage range
Multi-function Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
Multi-function
Timer
4 ch. (Max)
A/D start compare
6 ch.
Input capture
Free-run timer
Output compare
Waveform
generator
PPG
4 ch.
3 ch.
6 ch.
QPRC
Dual Timer
Real-time Clock
Watch Counter
Watchdog timer
External Interrupt
I/O port
12-bit A/D converter
CSV (Clock Supervisor)
LVD (Low-voltage Detection)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
S6E1A11C0A
S6E1A12C0A
48/52
1 unit
3 ch.
3 ch.
1 ch.
1 unit
1 unit
1 unit
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) + NMI × 1
23 pins (Max)
5 ch. (1 unit)
37 pins (Max)
8 ch. (1 unit)
Yes
2 ch.
4 MHz
100 kHz
SW-DP
Yes
Note:
• All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See "14. ELECTRICAL CHARACTERISTICS 14.4 AC Characteristics 14.4.3 Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
Document Number: 002-05091 Rev. *D
Page 6 of 97
S6E1A Series
2. Packages
Product name
Package
LQFP: LQB032 (0.80 mm pitch)
QFN: WNU032 (0.50 mm pitch)
LQFP: LQA048 (0.50 mm pitch)
QFN: WNY048 (0.50 mm pitch)
LQFP: LQC052 (0.65 mm pitch)
: Supported
S6E1A11B0A
S6E1A12B0A
-
S6E1A11C0A
S6E1A12C0A
Note:
• See "14. Package Dimensions" for detailed information on each package.
Document Number: 002-05091 Rev. *D
Page 7 of 97
S6E1A Series
3. Pin Assignment
LQB032
25 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
26 P01/SWCLK
27 P03/SWDIO
28 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
29 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
30 P61/SOT3_0/TIOB2_2/DTTI0X_2
31 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0
32 VSS
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 1
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 2
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 3
22 AVSS
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 4
21 AVCC
LQFP - 32
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 5
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 6
19 P12/AN02/SOT1_1/IC00_2/INT01_1
VSS 7
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
PE3/X1 16
PE2/X0 15
MD0 14
PE0/ADTG_1/DTTI0X_1/INT02_2 13
INITX 12
P47/X1A 11
VCC 9
17 VSS
P46/X0A 10
C 8
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 8 of 97
S6E1A Series
WNU032
25 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
26 P01/SWCLK
27 P03/SWDIO
28 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
29 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
30 P61/SOT3_0/TIOB2_2/DTTI0X_2
31 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0
32 VSS
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 1
24 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 2
23 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 3
22 AVSS
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 4
21 AVCC
QFN - 32
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 5
20 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 6
19 P12/AN02/SOT1_1/IC00_2/INT01_1
VSS 7
18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
PE3/X1 16
PE2/X0 15
MD0 14
PE0/ADTG_1/DTTI0X_1/INT02_2 13
INITX 12
P47/X1A 11
VCC 9
17 VSS
P46/X0A 10
C 8
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 9 of 97
S6E1A Series
LQA048
38 P01/SWCLK
37 P00
40 P03/SWDIO
39 P02
42 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
41 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
44 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
43 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
46 P81/SOT1_2
45 P80/SCK1_2/FRCK0_1
48 VSS
47 P82/SIN1_2
(TOP VIEW)
VCC 1
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
33 AVSS
P39/DTTI0X_0/ADTG_2 5
32 AVRH
LQFP - 48
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 6
31 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 7
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 8
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 9
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
27 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
VSS 12
VSS 24
PE3/X1 23
MD0 21
PE2/X0 22
P4A/TIOB1_0 19
PE0/ADTG_1/DTTI0X_1/INT02_2 20
INITX 17
P49/TIOB0_0 18
P46/X0A 15
P47/X1A 16
C 13
VCC 14
25 P10/AN00
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 10 of 97
S6E1A Series
WNY048
38 P01/SWCLK
37 P00
40 P03/SWDIO
39 P02
42 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
41 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
44 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
43 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
46 P81/SOT1_2
45 P80/SCK1_2/FRCK0_1
48 VSS
47 P82/SIN1_2
(TOP VIEW)
VCC 1
36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
35 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
34 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
33 AVSS
P39/DTTI0X_0/ADTG_2 5
32 AVRH
QFN- 48
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 6
31 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 7
30 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 8
29 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 9
28 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 10
27 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 11
26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
VSS 12
VSS 24
PE3/X1 23
MD0 21
PE2/X0 22
P4A/TIOB1_0 19
PE0/ADTG_1/DTTI0X_1/INT02_2 20
INITX 17
P49/TIOB0_0 18
P46/X0A 15
P47/X1A 16
C 13
VCC 14
25 P10/AN00
Note:
• The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05091 Rev. *D
Page 11 of 97
S6E1A Series
LQC052
40 NC
42 P01/SWCLK
41 P00
44 P03/SWDIO
43 P02
46 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
45 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1
48 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2
47 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2
50 P81/SOT1_2
49 P80/SCK1_2/FRCK0_1
52 VSS
51 P82/SIN1_2
(TOP VIEW)
VCC 1
39 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
38 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
P51/INT01_0/BIN0_2/SOT3_1 3
37 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
P52/INT02_0/ZIN0_2/SCK3_1 4
36 NC
NC 5
35 AVSS
P39/DTTI0X_0/ADTG_2 6
34 AVRH
LQFP - 52
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 7
33 AVCC
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 8
32 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 9
31 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 10
30 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 11
29 P12/AN02/SOT1_1/IC00_2/INT01_1
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 12
28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
VSS 13
VSS 26
PE2/X0 24
PE3/X1 25
MD0 23
PE0/ADTG_1/DTTI0X_1/INT02_2 22
NC 21
P4A/TIOB1_0 20
INITX 18
P49/TIOB0_0 19
P46/X0A 16
P47/X1A 17
C 14
VCC 15
27 P10/AN00
Note:
• The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-05091 Rev. *D
Page 12 of 97
S6E1A Series
4. Pin Descriptions
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin no.
LQFP-48
QFN-48
LQFP-52
1
1
Pin name
LQFP-32
QFN-32
-
VCC
I/O circuit type
Pin state type
-
P50
INT00_0
2
2
-
AIN0_2
I*
J
I*
J
I*
J
E
I
F
J
F
J
SIN3_1
IC01_0
P51
3
3
-
INT01_0
BIN0_2
SOT3_1
P52
4
4
-
INT02_0
ZIN0_2
SCK3_1
P39
6
5
-
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA0_1
7
6
1
AIN0_3
SUBOUT_2
RTCCO_2
INT03_0
SCK0_2
P3B
RTO01_0
TIOA1_1
8
7
2
BIN0_3
SOT0_2
INT04_0
SCS31_2
Document Number: 002-05091 Rev. *D
Page 13 of 97
S6E1A Series
Pin no.
LQFP-48
QFN-48
LQFP-52
Pin name
LQFP-32
QFN-32
I/O circuit type
Pin state type
P3C
RTO02_0
TIOA2_1
9
8
3
ZIN0_3
F
J
F
J
F
J
F
I
SIN0_2
INT05_0
SCS30_2
P3D
RTO03_0
10
9
4
TIOA3_1
INT06_0
AIN0_0
SCK3_2
P3E
RTO04_0
11
10
5
TIOA0_0
BIN0_0
SOT3_2
INT15_0
P3F
RTO05_0
12
11
6
TIOA1_0
ZIN0_0
SIN3_2
13
12
7
VSS
-
14
13
8
C
-
15
14
9
VCC
-
16
15
10
17
16
11
18
17
12
19
18
-
20
19
-
Document Number: 002-05091 Rev. *D
P46
X0A
P47
X1A
INITX
P49
TIOB0_0
P4A
TIOB1_0
D
E
D
F
B
C
E
I
E
I
Page 14 of 97
S6E1A Series
Pin no.
LQFP-48
QFN-48
LQFP-52
Pin name
LQFP-32
QFN-32
I/O circuit type
Pin state type
PE0
22
20
13
ADTG_1
C
J
J
D
A
A
A
B
DTTI0X_1
INT02_2
23
21
14
24
22
15
25
23
16
26
24
17
27
25
-
MD0
PE2
X0
PE3
X1
VSS
P10
AN00
G
K
H*
L
H*
L
H*
L
H*
L
P11
AN01
28
26
18
SIN1_1
INT02_1
FRCK0_2
IC02_0
P12
AN02
29
27
19
SOT1_1
IC00_2
INT01_1
P13
AN03
SCK1_1
30
28
20
SUBOUT_1
IC01_2
RTCCO_1
INT00_1
P14
AN04
31
29
-
SIN0_1
SCS10_1
INT03_1
IC02_2
Document Number: 002-05091 Rev. *D
Page 15 of 97
S6E1A Series
Pin no.
LQFP-48
QFN-48
LQFP-52
Pin name
LQFP-32
QFN-32
I/O circuit type
Pin state type
P15
AN05
32
30
-
SOT0_1
H*
L
SCS11_1
IC03_2
33
31
21
INT15_2
AVCC
34
32
-
AVRH
-
35
33
22
AVSS
-
-
P23
AN06
SCK0_0
37
34
23
TIOA2_0
G
L
G
L
E
J
E
I
E
H
E
I
E
H
IC02_1
AIN0_1
INT04_1
P22
AN07
SOT0_0
38
35
24
TIOB2_0
IC03_1
ZIN0_1
INT05_1
P21
SIN0_0
INT06_1
39
36
25
TIOB1_1
IC01_1
BIN0_1
FRCK0_0
41
37
-
42
38
26
43
39
-
44
40
27
Document Number: 002-05091 Rev. *D
P00
P01
SWCLK
P02
P03
SWDIO
Page 16 of 97
S6E1A Series
Pin no.
LQFP-48
QFN-48
LQFP-52
Pin name
LQFP-32
QFN-32
I/O circuit type
Pin state type
P04
SCK3_0
45
41
28
INT03_2
I*
J
E
G
I*
I
I*
J
K
I
K
I
K
I
TIOB0_1
IGTRG0_1
P0F
NMIX
46
42
29
SUBOUT_0
CROUT_1
RTCCO_0
P61
47
43
30
SOT3_0
TIOB2_2
DTTI0X_2
-
SCS11_2
P60
SIN3_0
48
44
31
TIOA2_2
INT15_1
IC00_0
IGTRG0_0
-
SCS10_2
P80
49
45
-
SCK1_2
FRCK0_1
P81
50
46
-
51
47
-
52
48
32
VSS
-
5,21,36,40
-
-
NC
-
SOT1_2
P82
SIN1_2
*:5V tolerant I/O
Document Number: 002-05091 Rev. *D
Page 17 of 97
S6E1A Series
List of pin functions
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel
on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select
the pin to be used.
Pin
function
Pin no.
Pin name
ADTG_1
20
13
5
-
AN00
27
25
-
AN01
28
26
18
AN02
29
27
19
30
28
20
31
29
-
AN05
32
30
-
AN06
37
34
23
AN07
38
35
24
11
10
5
7
6
1
19
18
-
45
41
28
12
11
6
8
7
2
20
19
-
39
36
25
37
34
23
9
8
3
48
44
31
38
35
24
47
43
30
AN03
TIOA0_0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_0
Base Timer
1
TIOA1_1
TIOB1_0
TIOB1_1
A/D converter external trigger
input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
TIOA2_0
TIOA2_1
Base Timer
2
TIOB2_2
Debugger
Base timer ch.2 TIOA pin
TIOA2_2
TIOB2_0
Base Timer
3
LQFP-32
QFN-32
6
AN04
Base Timer
0
LQFP-48
QFN-48
LQFP-52
22
ADTG_2
ADC
Function description
Base timer ch.2 TIOB pin
TIOA3_1
Base timer ch.3 TIOA pin
10
9
4
SWCLK
Serial wire debug interface clock input pin
Serial wire debug interface data
input / output pin
42
38
26
44
40
27
SWDIO
Document Number: 002-05091 Rev. *D
Page 18 of 97
S6E1A Series
Pin
function
Pin no.
Pin name
INT00_0
Function description
LQFP-32
QFN-32
2
2
-
30
28
20
3
3
-
29
27
19
4
4
-
28
26
18
INT02_2
22
20
13
INT03_0
7
6
1
31
29
-
45
41
28
8
7
2
37
34
23
9
8
3
38
35
24
10
9
4
39
36
25
11
10
5
48
44
31
32
30
-
46
42
29
INT00_1
INT01_0
INT01_1
External interrupt request 00 input pin
External interrupt request 01 input pin
INT02_0
INT02_1
INT03_1
External
Interrupt
LQFP-48
QFN-48
LQFP-52
External interrupt request 02 input pin
External interrupt request 03 input pin
INT03_2
INT04_0
INT04_1
INT05_0
INT05_1
INT06_0
INT06_1
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
INT15_0
INT15_1
External interrupt request 15 input pin
INT15_2
NMIX
Document Number: 002-05091 Rev. *D
Non-Maskable Interrupt input pin
Page 19 of 97
S6E1A Series
Pin
function
Pin no.
Pin name
LQFP-32
QFN-32
41
37
-
P01
42
38
26
43
39
-
44
40
27
P04
45
41
28
P0F
46
42
29
P10
27
25
-
P11
28
26
18
29
27
19
30
28
20
P14
31
29
-
P15
32
30
-
P21
39
36
25
38
35
24
P23
37
34
23
P39
6
5
-
P3A
7
6
1
P3B
8
7
2
9
8
3
P3D
10
9
4
P3E
11
10
5
P3F
12
11
6
P46
16
15
10
17
16
11
P03
P12
P13
P22
P3C
P47
P49
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
General-purpose I/O port 3
General-purpose I/O port 4
19
18
-
P4A
20
19
-
P50
2
2
-
3
3
-
4
4
-
48
44
31
47
43
30
49
45
-
P51
General-purpose I/O port 5
P52
GPIO
LQFP-48
QFN-48
LQFP-52
P00
P02
GPIO
Function description
P60
P61
General-purpose I/O port 6
P80
P81
50
46
-
P82
51
47
-
PE0*
22
20
13
24
22
15
25
23
16
PE2
PE3
Document Number: 002-05091 Rev. *D
General-purpose I/O port 8
General-purpose I/O port E
Page 20 of 97
S6E1A Series
Pin
function
Pin no.
Pin name
Function description
SIN0_0
SIN0_1
Multi-functio
n Serial 0
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SOT0_2
(SDA0_2)
SCK0_0
(SCL0_0)
SCK0_2
(SCL0_2)
SIN1_1
SIN1_2
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
Multi-functio
n Serial 1
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
SCS10_1
SCS10_2
SCS11_1
SCS11_2
Multifunction
Serial
3
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
SCS30_2
SCS31_2
Document Number: 002-05091 Rev. *D
LQFP-32
QFN-32
39
36
25
31
29
-
9
8
3
38
35
24
32
30
-
8
7
2
37
34
23
7
6
1
28
26
18
51
47
-
29
27
19
50
46
-
30
28
20
49
45
-
Multi-function serial interface ch.1 serial
chip select 0 output/input pin.
31
29
-
48
44
-
Multi-function serial interface ch.1 serial
chip select 1 output pin.
32
30
-
47
43
-
48
44
31
2
2
-
12
11
6
47
43
30
3
3
-
11
10
5
45
41
28
4
4
-
10
9
4
9
8
3
8
7
2
Multi-function serial interface ch.0 input
pin
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA0 when used as an I2C
pin (operation mode 4).
Multi-function serial interface ch.0 clock
I/O pin.
This pin operates as SCK0 when used as
a CSIO pin (operation mode 2) and as
SCL0 when used as an I2C pin (operation
mode 4).
Multi-function serial interface ch.1 input
pin
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA1 when used as an I2C
pin (operation mode 4).
Multi-function serial interface ch.1 clock
I/O pin.
This pin operates as SCK1 when used as
a CSIO pin (operation mode 2) and as
SCL1 when used as an I2C pin (operation
mode 4).
SIN3_0
SIN3_1
LQFP-48
QFN-48
LQFP-52
Multi-function serial interface ch.3 input
pin
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when used as
a UART/CSIO/LIN pin (operation mode 0
to 3) and as SDA3 when used as an I2C
pin (operation mode 4).
Multi-function serial interface ch.3 clock
I/O pin.
This pin operates as SCK3 when used as
a CSIO (operation mode 2) and as SCL3
when used as an I2C pin (operation mode
4).
Multi-function serial interface ch.3 serial
chip select 0 input/output pin.
Multi-function serial interface ch.3 serial
chip select 1 output pin.
Page 21 of 97
S6E1A Series
Pin
function
Pin no.
Pin name
DTTI0X_0
Function description
LQFP-32
QFN-32
6
5
-
22
20
13
47
43
30
39
36
25
49
45
-
FRCK0_2
28
26
18
IC00_0
48
44
31
IC00_2
29
27
19
IC01_0
2
2
-
IC01_1
39
36
25
30
28
20
28
26
18
IC02_1
37
34
23
IC02_2
31
29
-
IC03_1
38
35
24
32
30
-
7
6
1
8
7
2
9
8
3
10
9
4
11
10
5
12
11
6
48
44
31
45
41
28
DTTI0X_1
DTTI0X_2
Input signal of waveform generator
controlling RTO00 to RTO05 outputs of
Multi-function Timer 0.
FRCK0_0
FRCK0_1
IC01_2
IC02_0
16-bit free-run timer ch.0 external clock
input pin.
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes channel number.
IC03_2
Multi-functio
n Timer 0
LQFP-48
QFN-48
LQFP-52
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
IGTRG0_0
IGTRG0_1
Document Number: 002-05091 Rev. *D
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
PPG IGBT mode external trigger input pin
Page 22 of 97
S6E1A Series
Pin no.
Pin
function
Pin name
10
9
4
37
34
23
2
2
-
AIN0_3
7
6
1
BIN0_0
11
10
5
39
36
25
3
3
-
BIN0_3
8
7
2
ZIN0_0
12
11
6
ZIN0_1
38
35
24
4
4
-
9
8
3
46
42
29
30
28
20
RTCCO_2
7
6
1
SUBOUT_0
46
42
29
30
28
20
7
6
1
18
17
12
23
21
14
1
1
-
BIN0_1
BIN0_2
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
ZIN0_3
RTCCO_0
RTCCO_1
SUBOUT_1
0.5-seconds pulse output pin of Real-time
clock
Sub clock output pin
SUBOUT_2
VCC
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, input MD0="L".
During serial programming to Flash
memory, input MD0="H".
Power supply pin
VCC
Power supply pin
15
14
9
VSS
GND pin
13
12
7
VSS
GND pin
26
24
17
VSS
GND pin
52
48
32
X0
Main clock (oscillation) input pin
24
22
15
X0A
Sub clock (oscillation) input pin
16
15
10
X1
Main clock (oscillation) I/O pin
25
23
16
17
16
11
46
42
29
33
31
21
34
32
-
35
33
22
14
13
8
RESET
INITX
Mode
MD0
POWER
GND
CLOCK
LQFP-32
QFN-32
AIN0_1
ZIN0_2
Real-time
clock
LQFP-48
QFN-48
LQFP-52
AIN0_0
AIN0_2
Quadrature
Position/
Revolution
Counter
Function description
X1A
Sub clock (oscillation) I/O pin
Built-in high-speed CR oscillation clock
CROUT_1
output port
AVCC
A/D converter analog power supply pin
Analog
A/D converter analog reference voltage
POWER
AVRH
input pin
Analog
A/D converter analog reference voltage
AVSS
GND
input pin
Power supply stabilization capacitance
C pin
C
pin
*: PE0 is an open drain pin, cannot output high.
Document Number: 002-05091 Rev. *D
Page 23 of 97
S6E1A Series
5. I/O Circuit Type
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
• Oscillation feedback resistor
: Approximately 1MΩ
• With standby mode control
Feedback
A
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
Document Number: 002-05091 Rev. *D
Page 24 of 97
S6E1A Series
Type
Circuit
Remarks
Pull-up resistor
B
Digital input
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50kΩ
Digital input
C
N-ch
Document Number: 002-05091 Rev. *D
Digital output
• Open drain output
• CMOS level hysteresis input
Page 25 of 97
S6E1A Series
Type
Circuit
Remarks
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5MΩ
• With standby mode control
Feedback
D
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05091 Rev. *D
Page 26 of 97
S6E1A Series
Type
Circuit
P-ch
E
P-ch
N-ch
Remarks
Digital output
Digital output
R
Pull-up resistor control
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Digital input
Standby mode control
P-ch
P-ch
Digital output
F
N-ch
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
• IOH= -12mA, IOL= 12mA
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05091 Rev. *D
Page 27 of 97
S6E1A Series
Type
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
G
Pull-up resistor control
R
Digital input
Standby mode control
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Analog input
Input control
P-ch
P-ch
N-ch
Digital output
Digital output
H
R
Pull-up resistor control
Digital input
Standby mode control
•
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
• Available to control of PZR
registers.
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Analog input
Input control
Document Number: 002-05091 Rev. *D
Page 28 of 97
S6E1A Series
Type
Circuit
P-ch
P-ch
Remarks
Digital output
I
N-ch
Digital output
R
Pull-up resistor control
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
5V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
• IOH= -4mA, IOL= 4mA
• Available to control PZR registers
• When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Digital input
Standby mode control
Mode input
J
P-ch
Digital output
K
N-ch
CMOS level hysteresis input
Digital output
R
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH= -4mA, IOL= 4mA
When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Digital input
Standby mode control
Document Number: 002-05091 Rev. *D
Page 29 of 97
S6E1A Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Code: DS00-00004-2Ea
Document Number: 002-05091 Rev. *D
Page 30 of 97
S6E1A Series
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Document Number: 002-05091 Rev. *D
Page 31 of 97
S6E1A Series
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-05091 Rev. *D
Page 32 of 97
S6E1A Series
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05091 Rev. *D
Page 33 of 97
S6E1A Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size:
Load capacitance:
More than 3.2 mm × 1.5 mm
Approximately 6 pF to 7 pF
Lead type
Load capacitance:
Approximately 6 pF to 7 pF
Document Number: 002-05091 Rev. *D
Page 34 of 97
S6E1A Series
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as External clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Document Number: 002-05091 Rev. *D
Page 35 of 97
S6E1A Series
Notes on Power-on
Turn power on/off in the following order or at the same time.
Turning on : VCC → AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.
Handling when using debug pins
When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input.
Document Number: 002-05091 Rev. *D
Page 36 of 97
S6E1A Series
8. Block Diagram
S6E1A11/S6E1A12
SWCLK,
SWDIO
To PIN-Function-Ctrl
SW-DP
Fast
GPIO
Cortex-M0+ Core
@40MHz(Max)
MTB
AHB-APB Bridge:
APB0(Max 40MHz)
System ROM
table
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
WatchDog Timer
(Hardware)
Multi-layer AHB (Max 40MHz)
Bit Band
Wrapper
NVIC
INITX
On-Chip SRAM
6 Kbyte
Flash I/F
Security
On-Chip Flash
56 Kbyte/
88 Kbyte
CSV
CLK
X0A
X1A
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
CR
100kHz
CROUT
AVCC,
AVSS
AVRH
(only S6E1A1xC0A)
12-bit A/D Converter
Power-On
Reset
Unit 0
ANxx
TIOAx
TIOBx
AINx
BINx
ZINx
Base Timer
16-bit 4ch./
32-bit 2ch.
QPRC
1ch.
A/D Activation
Compare 6ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
AHB-APB Bridge : APB1 (Max 40MHz)
ADTG
LVD Ctrl
LVD
IRQ-Monitor
Regulator
Watch Counter
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
8pin + NMI
INTx
MODE-Ctrl
MD0
NMIX
Low-speed CR
Prescaler
Peripheral Clock Gating
To Fast GPIO
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
Waveform Generator
3ch.
C
GPIO
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
Pxx
SCKx
IGTRGx
16-bit PPG
3ch.
Multi-function Timer
Document Number: 002-05091 Rev. *D
Multi-function Serial I/F
3ch.
(with FIFO)
SINx
SOTx
SCSx
Page 37 of 97
S6E1A Series
9. Memory Size
See Memory size in 1. Product Lineup to confirm the memory size.
10. Memory Map
Memory Map (1)
0x41FF_FFFF
Peripheral area
0xFFFF_FFFF
Reserved
0xF802_0000
0xF800_0000
Fast GPIO
(Single-cycle I/O port)
Reserved
Reserved
0xF000_3000
ROM table
0xF000_2000
0xF000_1000
0xF000_0000
MTB_DWT
MTB registers(SFR)
Cortex-M0+ Private
Peripherals
0xE000_0000
0x4003_C800
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
32 Mbytes Bit Band alias
0x4200_0000
Peripherals
0x4000_0000
0x4003_5100
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
32 Mbytes Bit Band alias
0x2200_0000
Reserved
LVD
Reserved
GPIO
Reserved
INT-Req READ
EXTI
Reserved
CR Trim
Reserved
Reserved
0x2400_0000
RTC
Watch Counter
Reserved
MFS
Reserved
Reserved
0x4400_0000
Peripheral Clock Gating
Low Speed CR Prescaler
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
A/DC
QPRC
Base Timer
PPG
0x2008_0000
SRAM
Reserved
0x2000_0000
0x4002_1000
0x4002_0000
Reserved
Reserved
See
map(2)"
See "Memory
“Memory map
(2)” forfor
the memory
memory size
the
sizedetails.
details.
0x4001_6000
0x4001_5000
Dual Timer
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
CR Trim
Security
Flash
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
0x0000_0000
0x4000_1000
0x4000_0000
Document Number: 002-05091 Rev. *D
MFT unit 0
Flash I/F
Page 38 of 97
S6E1A Series
Memory Map (2)
S6E1A12B0A
S6E1A12C0A
0x2008_0000
S6E1A11B0A
S6E1A11C0A
0x2008_0000
Reserved
0x2000_1800
Reserved
0x2000_1800
SRAM
6K bytes
0x2000_0000
SRAM
6K bytes
0x2000_0000
Reserved
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
Reserved
0x0001_6000
0x0000_E000
Flash 88K bytes *
Flash 56Kbytes *
0x0000_0000
0x0000_0000
*: See "S6E1A1 Series Flash Programming Manual" to check details of the flash memory.
Document Number: 002-05091 Rev. *D
Page 39 of 97
S6E1A Series
Peripheral Address Map
Start address
End address
Bus
Peripheral
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog Timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function Timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low-Voltage Detection
0x4003_5800
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function Serial Interface
0x4003_9000
0x4003_9FFF
Reserved
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C7FF
Peripheral Clock Gating
0x4003_C800
0x4003_FFFF
Reserved
0x4004_0000
0x41FF_FFFF
Document Number: 002-05091 Rev. *D
AHB
APB0
APB1
AHB
Flash memory I/F register
Reserved
Software Watchdog Timer
Reserved
Reserved
Reserved
Page 40 of 97
S6E1A Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Document Number: 002-05091 Rev. *D
Page 41 of 97
S6E1A Series
Pin status type
List of Pin Status
Function group
State upon
power-on
reset or
low-voltage
detection
Power
supply
unstable
-
State at
INITX
input
State upon
device
internal reset
Power supply stable
INITX = 0
-
INITX = 1
-
State in Run
mode or
SLEEP mode
State in TIMER mode,
RTC mode, or
STOP mode
Power supply
stable
Power supply stable
INITX = 1
-
INITX = 1
SPL = 0
SPL = 1
Hi-Z / Internal
Maintain
input fixed at
previous state
"0"
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Main crystal
A oscillator input
pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
Hi-Z / Internal
input fixed at
"0"
Hi-Z / Internal
input fixed at
"0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
Input enabled
Hi-Z /
Internal input
fixed at "0"/
Input
enabled
Hi-Z /
Internal input
fixed at "0"
Hi-Z / Internal
input fixed at
"0"
Maintain
previous
state/When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at "0"
C INITX input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
D Mode input pin
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
Sub crystal
E oscillator input pin
/
External sub
clock input
selected
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
Input enabled
B
Main crystal
oscillator output
pin
Document Number: 002-05091 Rev. *D
Page 42 of 97
Pin status type
S6E1A Series
Function group
State upon
power-on
reset or
low-voltage
detection
Power
supply
unstable
-
State at
INITX
input
State upon
device
internal reset
Power supply stable
INITX = 0
-
INITX = 1
-
State in Run
mode or
SLEEP mode
State in TIMER mode,
RTC mode, or
STOP mode
Power supply
stable
Power supply stable
INITX = 1
-
INITX = 1
SPL = 0
SPL = 1
Hi-Z / Internal
Maintain
input fixed at
previous state
"0"
Hi-Z / Internal
Maintain
input fixed at
previous state
"0"
Maintain
Maintain
previous
previous
state/When
state/When
oscillation
oscillation
stops*2,
stops*2,
Hi-Z / Internal
Hi-Z / Internal
input fixed at
input fixed at
"0"
"0"
Maintain
previous state
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Sub crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at "0"/
Input
enabled
Hi-Z /
Internal input
fixed at "0"
Hi-Z / Internal
input fixed at
"0"
Maintain
previous state
NMIX selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input enabled
Serial wire debug
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up / Input
enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input enabled
Hi-Z
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Setting
disabled
Setting
disabled
F
Resource other
G than the above
selected
GPIO selected
H
I
Resource
selected
GPIO selected
External interrupt
enabled selected
J
Resource other
than the above
selected
GPIO selected
Analog input
selected
K
Resource other
than the above
selected
GPIO selected
Document Number: 002-05091 Rev. *D
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
Hi-Z / Internal
input fixed at
"0"
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
Hi-Z / Internal
input fixed at
"0"
Page 43 of 97
Pin status type
S6E1A Series
Function group
Analog input
selected
State upon
power-on
reset or
low-voltage
detection
Power
supply
unstable
-
Hi-Z
State at
INITX
input
State upon
device
internal reset
Power supply stable
INITX = 0
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
INITX = 1
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
State in Run
mode or
SLEEP mode
State in TIMER mode,
RTC mode, or
STOP mode
Power supply
stable
Power supply stable
INITX = 1
-
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
L External interrupt
enabled selected
Resource other
than the above
selected
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
Maintain
previous state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
GPIO selected
Maintain
previous state
Hi-Z / Internal
input fixed at
"0"
*1:Oscillation stops in Sub timer mode, Low-speed CR timer mode, STOP mode, RTC mode.
*2:Oscillation stops in STOP mode.
Document Number: 002-05091 Rev. *D
Page 44 of 97
S6E1A Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Power supply voltage*1, *2
Analog power supply voltage*1, *3
VCC
AVCC
Min
VSS - 0.5
VSS - 0.5
Analog reference voltage*1, *3
AVRH
VSS - 0.5
Input voltage*1
VI
VSS - 0.5
VSS - 0.5
Analog pin input voltage*1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
"L" level maximum output current*4
IOL
-
"L" level average output current*5
IOLAV
-
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
"H" level maximum output current*4
IOH
-
"H" level average output current*5
IOHAV
-
"H" level total maximum output current
"H" level total average output current*6
Power consumption
Storage temperature
∑IOH
∑IOHAV
PD
TSTG
- 55
Unit
Max
VSS + 6.5
VSS + 6.5
V
V
VSS + 6.5
V
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
10
20
4
12
100
50
- 10
- 20
-4
- 12
- 100
- 50
200
+ 150
Remarks
Only
S6E1A1xC0A
V
V
5V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
4 mA type
12 mA type
4 mA type
12 mA type
4 mA type
12 mA type
4 mA type
12 mA type
*1:These parameters are based on the condition that VSS = AVss = 0 V.
*2:Vcc must not drop below VSS - 0.5 V.
*3:Ensure that the voltage does not to exceed VCC + 0.5 V at power-on.
*4:The maximum output current is the peak value for a single pin.
*5:The average output is the average current for a single pin over a period of 100 ms.
*6:The total average output current is the average current for all pins over a period of 100 ms.
Warning
• Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings
Document Number: 002-05091 Rev. *D
Page 45 of 97
S6E1A Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
Power supply voltage
Analog power supply voltage
VCC
AVCC
Analog reference voltage
Smoothing capacitor
Operating temperature
Value
Unit
-
Min
2.7*2
2.7
Max
5.5
5.5
AVRH
-
2.7
AVCC
V
CS
Ta
-
1
- 40
10
+ 105
μF
°C
V
V
Remarks
AVCC = VCC
Only
S6E1A1xC0A
For regulator*1
“1: See "C Pin" in "6. Handling Precautions" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
Warning
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
4. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-05091 Rev. *D
Page 46 of 97
S6E1A Series
12.3 DC Characteristics
12.3.1 Current Rating
Symbol
(Pin
name)
Run mode,
code executed
from Flash
Icc
(VCC)
Run mode,
code executed
from RAM
Run mode,
code executed
from Flash
Run mode,
code executed
from Flash
Iccs
(VCC)
SLEEP operation
Document Number: 002-05091 Rev. *D
Conditions
4MHz external clock input, PLL
ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
4MHz external clock input, PLL
ON*8
Benchmark code executed
Built-in high speed CR stopped
PCLK1 stopped
4MHz crystal oscillation, PLL ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
4MHz external clock input, PLL
ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by
CKENx
4MHz external clock input, PLL
ON
NOP code executed
Built-in high speed CR stopped
PCLK1 stopped
Built-in high speed CR*5
NOP code executed
All peripheral clock stopped by
CKENx
32kHz crystal oscillation
NOP code executed
All peripheral clock stopped by
CKENx
Built-in low speed CR
NOP code executed
All peripheral clock stopped by
CKENx
4MHz external clock input, PLL
ON*8
All peripheral clock stopped by
CKENx
Built-in high speed CR*5
All peripheral clock stopped by
CKENx
32kHz crystal oscillation
All peripheral clock stopped by
CKENx
Built-in low speed CR
All peripheral clock stopped by
CKENx
HCLK
Frequency
*4
4MHz
8MHz
20MHz
Value
0.7
1.3
2.8
1.5
2.3
4.0
40MHz
5.7
7.3
4MHz
8MHz
20MHz
0.6
1.2
2.6
1.4
2.1
3.7
40MHz
4.8
6.3
4MHz
8MHz
20MHz
1.0
1.7
3.4
2.9
3.6
5.6
40MHz
5.7
8.2
4MHz
8MHz
20MHz
0.5
0.9
2.0
1.2
1.8
2.9
40MHz
3.7
4.8
40MHz
2.8
4MHz
Unit
Remarks
mA
*3
mA
*3
mA
*3
mA
*3
3.7
mA
*3,*6,*7
0.8
1.5
mA
*3
32kHz
65
900
μA
*3
100kHz
73
920
μA
*3
4MHz
8MHz
20MHz
40MHz
0.4
0.7
1.5
2.7
1.2
1.6
2.4
3.7
mA
*3
4MHz
0.5
1.2
mA
*3
32kHz
63
880
μA
*3
100kHz
66
890
μA
*3
Typ*1
Max*2
Page 47 of 97
S6E1A Series
*1 : Ta=+25℃,VCC=3.0V
*2 : Ta=+105℃,VCC=5.5V
*3 : All ports are fixed
*4 : PCLK0=HCLK/8
*5 : The frequency is set to 4MHz by trimming
*6 : Flash sync down is set to FRWTR.RWT = 11 and FSYNDN.SD = 1111
*7 : VCC=2.7V
*8 : When HCLK=4MHz, PLL OFF
Symbol
(Pin
name)
ICCH
(VCC)
ICCT
(VCC)
ICCR
(VCC)
Value
Conditions
STOP mode
Sub timer mode
RTC mode
Ta=25℃
Vcc=3.0V
LVD off
Ta=25℃
Vcc=5.0V
LVD off
Ta=105℃
Vcc=5.5V
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=3.0V
32kHz crystal oscillation
LVD off
Ta=25℃
Vcc=5.0V
32kHz crystal oscillation
LVD off
Ta=105℃
Vcc=5.5V
32kHz crystal oscillation
LVD off
Typ
Max
Uni
t
Remarks
5.6
28
μA
*1
6.7
30
μA
*1
-
540
μA
*1
12
42
μA
*1
13
44
μA
*1
-
730
μA
*1
9
36
μA
*1
10
38
μA
*1
-
570
μA
*1
*1:All ports are fixed.
Document Number: 002-05091 Rev. *D
Page 48 of 97
S6E1A Series
LVD current
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Low-Voltage
detection circuit
(LVD) power
supply current
Pin
name
Symbol
ICCLVD
VCC
Value
Conditions
Typ
Max
Unit
Remarks
0.13
0.3
μA
For occurrence of reset
0.13
0.3
μA
For occurrence of
interrupt
At operation
Flash memory current
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
current
Pin
name
Symbol
ICCFLASH
VCC
Value
Conditions
At Write/Erase
Typ
9.5
Max
11.2
Unit
Remarks
mA
A/D convertor current (S6E1A1xC0A)
Parameter
Power supply
current
Reference
power supply
current
(AVRH)
Pin
name
Symbol
ICCAD
AVCC
ICCAVRH
AVRH
At operation
At stop
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Unit
Remarks
Typ
Max
0.7
0.9
mA
0.13
13
μA
At operation
1.1
1.97
mA
At stop
0.1
1.7
μA
Conditions
AVRH=5.5V
A/D convertor current (S6E1A1xB0A)
Parameter
Symbol
Pin
name
Power supply
current
ICCAD
AVCC
Conditions
At operation
At stop
(VCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = - 40°C to + 105°C)
Value
Unit
Remarks
Typ
Max
1.8
0.23
2.87
14.7
mA
μA
Peripheral current dissipation
Clock
system
HCLK
PCLK1
Peripheral
Conditions
Frequency (MHz)
8
20
40
0.22
0.55
1.10
0.05
0.15
0.30
0.28
0.68
1.38
GPIO
Base timer
Multi-functional timer/PPG
At all ports operation
At 4ch operation
At 1unit/4ch operation
4
0.11
0.03
0.14
Quadrature
position/Revolution counter
At 1unit operation
0.02
0.04
0.11
0.22
ADC
Multi-function serial
At 1unit operation
At 1ch operation
0.07
0.15
0.14
0.31
0.37
0.77
0.73
1.54
Document Number: 002-05091 Rev. *D
Unit
Remarks
mA
mA
Page 49 of 97
S6E1A Series
12.3.2
Pin Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
"H" level input
voltage
(hysteresis
input)
VIHS
"L" level input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis
input pin,
MD0, PE0
5V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, PE0
5V tolerant
input pin
4 mA type
"H" level
output voltage
VOH
12 mA type
4 mA type
"L" level
output voltage
VOL
12 mA type
Input leak
current
Pull-up
resistance
value
Input
capacitance
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC, VSS,
AVCC,
AVSS, AVRH
Document Number: 002-05091 Rev. *D
Conditions
Min
Value
Typ
Max
Unit
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
Remarks
kΩ
pF
Page 50 of 97
S6E1A Series
12.4 AC Characteristics
12.4.1
Main Clock Input Characteristics
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling time
Internal operating
clock*1 frequency
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Conditions
Unit
Remarks
Min
Max
Pin
name
Symbol
FCH
X0,
X1
VCC ≥ 4.5V
VCC < 4.5V
4
4
40
20
MHz
When the crystal
oscillator is connected
-
4
40
MHz
When the external
clock is used
-
25
250
ns
PWH/tCYLH,
PWL/tCYLH
45
55
%
-
-
5
ns
tCF,
tCR
FCM
-
-
-
41.2
MHz
When the external
clock is used
When the external
clock is used
When the external
clock is used
Master clock
FCC
FCP0
FCP1
-
-
-
41.2
41.2
41.2
MHz
MHz
MHz
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYLH
-
tCYCC
tCYCP0
tCYCP1
24.27
ns
Base clock (HCLK/FCLK)
24.27
ns
APB0 bus clock*2
24.27
ns
APB1 bus clock*2
*1: For details of each internal operating clock, refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
Internal operating
clock*1 cycle time
*2: For details of the APB bus to which a peripheral is connected, see "8. Block Diagram".
X0
Document Number: 002-05091 Rev. *D
Page 51 of 97
S6E1A Series
12.4.2
Sub Clock Input Characteristics
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Typ
Max
When the crystal
32.768
kHz
oscillator is
connected
Input frequency
1/tCYLL
When the external
32
100
kHz
X0A,
clock is used
X1A
When the external
Input clock cycle
tCYLL
10
31.25
μs
clock is used
Input clock pulse
PWH/tCYLL,
When the external
45
55
%
width
PWL/tCYLL
clock is used
*: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used.
X0A
Document Number: 002-05091 Rev. *D
Page 52 of 97
S6E1A Series
12.4.3
Built-in CR Oscillation Characteristics
Built-in high-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Ta = + 25°C,
3.6V < VCC ≤ 5.5V
Clock frequency
FCRH
Ta =0°C to + 85°C,
3.6V < VCC ≤ 5.5V
Ta = - 40°C to + 105°C,
3.6V < VCC ≤ 5.5V
Ta = + 25°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 85°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 20°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Ta = - 40°C to + 105°C,
2.7V ≤ VCC ≤ 3.6V
Typ
Max
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
2.8
4
5.2
Unit
Remarks
During trimming*1
MHz
Ta = - 40°C to + 105°C
Not during trimming
Frequency
tCRWT
30
μs
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency
trimming/temperature trimming.
*2
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source
clock.
Built-in low-speed CR
(VCC = AVCC = 2.7 V to 5.5 V, VSS =AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRL
Document Number: 002-05091 Rev. *D
Conditions
-
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 53 of 97
S6E1A Series
12.4.4
Operating Conditions of Main PLL
(In the case of using the main clock as the input clock of the PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
PLL oscillation stabilization wait time*1
tLOCK
100
(LOCK UP time)
PLL input clock frequency
FPLLI
4
PLL multiple rate
5
PLL macro oscillation clock frequency
FPLLO
75
Main PLL clock frequency*2
FCLKPLL
*1: The wait time is the time it takes for PLL oscillation to stabilize.
Typ
Max
Unit
-
-
μs
-
16
37
150
40
MHz
multiple
MHz
MHz
Remarks
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
12.4.5
Operating Conditions of Main PLL
(In the case of using the built-in high-speed CR clock as the input clock of the main PLL)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
PLL oscillation stabilization wait time*1
tLOCK
100
(LOCK UP time)
PLL input clock frequency
FPLLI
3.88
PLL multiple rate
19
PLL macro oscillation clock frequency
FPLLO
72
Main PLL clock frequency*2
FCLKPLL
*1: The wait time is the time it takes for PLL oscillation to stabilize.
Typ
Max
Unit
-
-
μs
4
-
4.12
35
150
41.2
MHz
multiple
MHz
MHz
Remarks
*2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL".
Note:
For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency has been trimmed.
Document Number: 002-05091 Rev. *D
Page 54 of 97
S6E1A Series
12.4.6
Reset Input Characteristics
(VCC =AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Reset input time
12.4.7
Symbol
tINITX
Pin
name
Value
Conditions
INITX
Min
-
Unit
Max
500
-
Remarks
ns
Power-on Reset Timing
(VSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Power supply shout down time
Power ramp rate
Time until releasing Power-on reset
Symbol
Pin
name
Value
Conditions
VCC
Max
1
-
-
ms
*1
1.0
-
1000
mV/µs
*2
0.43
-
3.4
ms
VCC: 0.2V to 2.70V
tPRT
*1: VCC must be held below 0.2V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.6.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See "12.6. Low-Voltage Detection Characteristics".
Document Number: 002-05091 Rev. *D
Remark
Typ
tOFF
dV/dt
Unit
Min
Page 55 of 97
S6E1A Series
12.4.8
Base Timer Input Timing
Timer input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH, tTIWL
Conditions
-
Value
Min
2 tCYCP
tTIWH
Max
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
tTRGH, tTRGL
TIOAn/TIOBn
(when using as
TGIN)
Conditions
-
tTRGH
TGIN
VIHS
Value
Min
2 tCYCP
Max
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
• tCYCP indicates the APB bus clock cycle time.
For the number of the APB bus to which the Base Timer has been connected, see "8. Block Diagram".
Document Number: 002-05091 Rev. *D
Page 56 of 97
S6E1A Series
12.4.9
CSIO/UART Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
Conditions
VCC ≥ 4.5 V
Min
Max
8
4 tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Unit
Baud rate
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
2 tCYCP 10
-
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
SCK ↓ → SOT delay time
tSLOVE
-
50
-
30
ns
SIN → SCK ↑ setup time
tIVSHE
10
-
10
-
ns
SCK ↑ → SIN hold time
tSHIXE
20
-
20
-
ns
SCK falling time
SCK rising time
tF
tR
-
5
5
-
5
5
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
-
VCC < 4.5 V
Min
Max
8
4 tCYCP
-
Internal shift
clock
operation
External shift
clock
operation
2 tCYCP 10
tCYCP +
10
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
SOT
VOH
VOL
tIVSHI
SIN
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
Document Number: 002-05091 Rev. *D
Page 57 of 97
S6E1A Series
tSLSH
VIH
SCK
tF
tSHSL
VIL
VIH
VIL
tR
tSLOVE
SOT
VIH
VOH
VOL
tIVSHE
VIH
VIL
SIN
tSHIXE
VIH
VIL
MS bit = 1
Synchronous serial (SPI = 0, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
Baud rate
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Conditions
-
Internal shift
clock
operation
VCC < 4.5V
Min
Max
8
4 tCYCP
-
VCC ≥ 4.5V
Min
Max
8
4 tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2 tCYCP 10
tCYCP + 10
External shift
clock
operation
Unit
-
2 tCYCP 10
tCYCP + 10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 58 of 97
S6E1A Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 59 of 97
S6E1A Series
Synchronous serial (SPI = 1, SCINV = 0)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Baud rate
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Conditions
-
Internal shift
clock
operation
VCC < 4.5 V
Min
Max
8
4 tCYCP
-
VCC ≥ 4.5 V
Min
Max
8
4 tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
External shift
clock
operation
Unit
-
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 60 of 97
S6E1A Series
tSCYC
VOH
VOL
SCK
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
MS bit = 0
tSLSH
VIH
SCK
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
VIL
tF
*
SOT
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: This changes as data is written to the TDR register.
Document Number: 002-05091 Rev. *D
Page 61 of 97
S6E1A Series
Synchronous serial (SPI = 1, SCINV = 1)
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
SCKx
Baud rate
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Conditions
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Internal shift
clock
operation
VCC < 4.5 V
Min
Max
8
4 tCYCP
-
VCC ≥ 4.5 V
Min
Max
8
4 tCYCP
-
Mbps
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
External shift
clock
operation
Unit
-
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
• The above AC characteristics are for CLK synchronous mode.
• tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
• External load capacitance CL = 30 pF
Document Number: 002-05091 Rev. *D
Page 62 of 97
S6E1A Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
MS bit = 0
tSHSL
tR
VIL
SCK
tSLSH
VIH
VIH
VIL
tF
VIL
VIH
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 63 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 0, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↓ setup time
tCSSE
SCK↑→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SUT delay time
tDSE
SCS↑→SUT delay time
tDEE
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Min
Max
Min
Unit
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
ns
ns
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 64 of 97
S6E1A Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSSE
tCSHE
SCK input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 65 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 1, CSLVL=1)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↓→SCK↑ setup time
tCSSI
SCK↓→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
SCS↓→SCK↑ setup time
tCSSE
SCK↓→SCS↑ hold time
tCSHE
SCS deselect time
tCSDE
SCS↓→SOT delay time
tDSE
SCS↑→SOT delay time
tDEE
Internal shift
clock
operation
External shift
clock
operation
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Min
Max
Min
Unit
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
ns
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
ns
ns
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 66 of 97
S6E1A Series
SCS output
tCSDI
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS input
tCSDE
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 67 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 0, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↓ setup time
tCSSI
SCK↑→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↓ setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Min
Max
Min
Unit
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+50
(*3)+50
+5tCYCP
-
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
ns
tCSSE
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
Internal shift
clock
operation
External shift
clock
operation
ns
ns
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 68 of 97
S6E1A Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 69 of 97
S6E1A Series
When using synchronous serial chip select (SCINV = 1, CSLVL=0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
SCS↑→SCK↑ setup time
tCSSI
SCK↓→SCS↓ hold time
tCSHI
SCS deselect time
tCSDI
SCS↑→SCK↑ setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSDE
SCS↑→SOT delay time
tDSE
SCS↓→SOT delay time
tDEE
VCC ≥ 4.5V
VCC < 4.5V
Conditions
Min
Max
Min
Unit
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+50
(*3)+50
+5tCYCP
-
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
(*2)+50
(*3)+50
+5tCYCP
-
ns
tCSSE
(*2)+0
(*3)-50
+5tCYCP
3tCYCP+30
tCSHE
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
-
40
-
40
ns
0
-
0
-
ns
Internal shift
clock
operation
External shift
clock
operation
ns
ns
(*1): CSSU bit value × serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value × serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value × serial chip select timing operating clock cycle [ns]
Notes:
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ".
• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL".
• The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SCSx0_1.
• When the external load capacitance CL = 30pF.
Document Number: 002-05091 Rev. *D
Page 70 of 97
S6E1A Series
tCSDI
SCS output
tCSHI
tCSSI
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
tCSDE
SCS input
tCSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-05091 Rev. *D
Page 71 of 97
S6E1A Series
External clock (EXT = 1): asynchronous only
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
SCK rising time
Symbol
tSLSH
tSHSL
tF
tR
Conditions
CL = 30 pF
tR
SCK
VIL
Document Number: 002-05091 Rev. *D
Value
Min
tCYCP + 10
tCYCP + 10
-
tSHSL
VIH
5
5
VIL
Remarks
ns
ns
ns
ns
tF
tSLSH
VIH
Unit
Max
VIL
VIH
Page 72 of 97
S6E1A Series
12.4.10 External Input Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
A/D converter
trigger input
ADTGx
FRCKx
Input pulse width
tINH, tINL
Remarks
-
2 tCYCP*1
-
ns
Free-run timer
input clock
ICxx
Input capture
Wave form
DTTIxX
2 tCYCP
ns
generator
2 tCYCP + 100*1
ns
External
INTxx, NMIX
interrupt, NMI
500*2
ns
*1: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the
number of the APB bus to which the Multi-function Timer is connected and that of the APB bus to which the External Interrupt
Controller is connected, see "8. Block Diagram".
*1
*2: In STOP mode and TIMER mode
Document Number: 002-05091 Rev. *D
Page 73 of 97
S6E1A Series
12.4.11 QPRC Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
Time from AIN pin "H" level to BIN
tAUBU
PC_Mode2 or PC_Mode3
rise
Time from BIN pin "H" level to AIN
tBUAD
PC_Mode2 or PC_Mode3
fall
Time from AIN pin "L" level to BIN
tADBD
PC_Mode2 or PC_Mode3
fall
Time from BIN pin "L" level to AIN
tBDAU
PC_Mode2 or PC_Mode3
rise
Time from BIN pin "H" level to AIN
2 tCYCP*
ns
tBUAU
PC_Mode2 or PC_Mode3
rise
Time from AIN pin "H" level to BIN
tAUBD
PC_Mode2 or PC_Mode3
fall
Time from BIN pin "L" level to AIN
tBDAD
PC_Mode2 or PC_Mode3
fall
Time from AIN pin "L" level to BIN
tADBU
PC_Mode2 or PC_Mode3
rise
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
Time from determined ZIN level to
tZABE
QCR:CGSC="1"
AIN/BIN rise and fall
Time from AIN/BIN rise and fall time
tABEZ
QCR:CGSC="1"
to determined ZIN level
*: tCYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the
number of the APB bus to which the QPRC is connected, see "8. Block Diagram".
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05091 Rev. *D
tBLL
Page 74 of 97
S6E1A Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05091 Rev. *D
Page 75 of 97
S6E1A Series
12.4.12 I2C Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Standard-mode
Min
Max
0
100
Fast-mode
Min
Max
0
400
Unit
Remarks
SCL clock frequency
FSCL
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
0.6
μs
SDA ↓ → SCL ↓
SCL clock "L" width
tLOW
4.7
1.3
μs
SCL clock "H" width
tHIGH
4.0
0.6
μs
(Repeated) START setup
time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 30 pF,
R = (Vp/IOL)*1
Data hold time
tHDDAT
0
3.45*2
0
0.9*3
μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
tBUF
4.7
1.3
μs
"START condition"
Noise filter
tSP
2 tCYCP*4 2 tCYCP*4 ns
*1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. Vp
represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current.
*2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at "L"
(tLOW) does not extend.
*3: A Fast-mode I2C bus device can be used in a Standard-mode I2C bus system, provided that the condition of "tSUDAT ≥ 250 ns" is
fulfilled.
*4: tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which the I2C is connected, see "8. Block Diagram".
To use Standard-mode, set the APB bus clock at 2MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05091 Rev. *D
Page 76 of 97
S6E1A Series
12.4.13 SW-DP Timing
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Value
Conditions
Min
Max
Unit
SWDIO setup time
tSWS
SWCLK,
SWDIO
-
15
-
ns
SWDIO hold time
tSWH
SWCLK,
SWDIO
-
15
-
ns
SWDIO delay time
tSWD
SWCLK,
SWDIO
-
-
45
ns
Remarks
Note:
• External load capacitance CL = 30 pF
SWCLK
SWDIO
(When input)
SWD
SWDIO
(When output)
Document Number: 002-05091 Rev. *D
Page 77 of 97
S6E1A Series
12.5 12-bit A/D Converter
Electrical characteristics of A/D Converter
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
VZT
ANxx
Full-scale transition voltage
VFST
ANxx
Conversion time
-
-
Min
- 4.5
- 2.5
- 20
AVRH - 20
AVCC-20
0.8*1
2.0*1
Value
Typ
-
12
4.5
+ 2.5
+ 20
AVRH+ 20
AVCC+20
bit
LSB
LSB
mV
mV
-
-
μs
10
μs
1000
ns
Max
Unit
0.24
Sampling
time*2
Ts
-
0.3
0.6
40
Compare clock
cycle*3
Tcck
-
50
100
State transition time to
operation permission
Analog input capacity
Tstt
-
-
-
1.0
μs
CAIN
-
-
-
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
Analog port input current
-
ANxx
Analog input voltage
-
ANxx
Reference voltage
-
AVRH
AVSS
AVSS
2.7
-
9.7
1.6
2.3
4
5
AVRH
AVCC
AVCC
kΩ
LSB
μA
V
V
Remarks
S6E1A1xC0A
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xC0A
AVCC < 4.5V
S6E1A1xB0A
S6E1A1xC0A
AVCC ≥ 4.5V
S6E1A1xC0A
AVCC < 4.5V
S6E1A1xB0A
AVCC ≥ 4.5V
AVCC < 4.5V
S6E1A1xC0A
S6E1A1xB0A
Only S6E1A1xB0A
*1: The conversion time is the value of "sampling time (Ts) + compare time (Tc)".
The minimum conversion time is computed according to the following conditions: sampling time = 240 ns, compare time = 560
ns (AVcc ≥ 4.5 V). Must be set 25MHz to the Base clock (HCLK).
Ensure that the conversion time satisfies the specifications of the sampling time (Ts) and compare clock cycle (Tcck).
For details of the settings of the sampling time and compare clock cycle, refer to "CHAPTER: A/D Converter" in "FM0+ Family
PERIPHERAL MANUAL Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (Tc) is the result of (Equation 2).
Document Number: 002-05091 Rev. *D
Page 78 of 97
S6E1A Series
ANxx,
Analog input pins
Rext
Comparator
RAIN
Analog signal
source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN:
Input resistance of A/D Converter = 1.6 kΩ with 4.5 < AVCC < 5.5 ch.1 to ch.5
Input resistance of A/D Converter = 1.4 kΩ with 4.5 < AVCC < 5.5 ch.0, ch.6, ch.7
Input resistance of A/D Converter = 2.3 kΩ with 2.7 < AVCC < 4.5 ch.1 to ch.5
Input resistance of A/D Converter = 2.0 kΩ with 2.7 < AVCC < 4.5 ch.0, ch.6, ch.7
CAIN:
Input capacitance of A/D Converter = 9.7 pF with 2.7 < AVCC < 5.5
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-05091 Rev. *D
Page 79 of 97
S6E1A Series
Definitions of 12-bit A/D Converter terms
Resolution
: Analog variation that is recognized by an A/D converter.
Integral Nonlinearity
: Deviation of the line between the zero-transition point (0b000000000000 ←→
0b000000000001) and the full-scale transition point (0b111111111110 ←→
0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity
: Deviation from the ideal value of the input voltage that is required to change the output
code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Actual conversion
characteristics
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
Actual conversion characteristics
AVRH*1
AVSS
AVRH*1
AVSS
Analog input
Analog input
*1: At the 32pin product, it is AVCC
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
:
:
:
:
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05091 Rev. *D
Page 80 of 97
S6E1A Series
12.6 Low-voltage Detection Characteristics
12.6.1
Low-voltage Detection Reset
(Ta = - 40°C to + 105°C)
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
SVHR*1 =
00000
SVHR*1 =
00001
SVHR*1 =
00010
SVHR*1 =
00011
SVHR*1 =
00100
SVHR*1 =
00101
SVHR*1 =
00110
SVHR*1 =
00111
SVHR*1 =
01000
SVHR*1 =
01001
SVHR*1 =
01010
Value
Min
Typ
Max
2.25
2.45
2.65
2.30
2.50
2.70
2.39
2.60
2.81
Same as SVHR = 00000 value
2.48
2.70
2.92
Same as SVHR = 00000 value
2.58
2.80
3.02
Same as SVHR = 00000 value
2.76
3.00
3.24
Same as SVHR = 00000 value
2.94
3.20
3.46
Same as SVHR = 00000 value
3.31
3.60
3.89
Same as SVHR = 00000 value
3.40
3.70
4.00
Same as SVHR = 00000 value
3.68
4.00
4.32
Same as SVHR = 00000 value
3.77
4.10
4.43
Same as SVHR = 00000 value
3.86
4.20
4.54
Same as SVHR = 00000 value
LVD stabilization wait
time
TLVDW
-
-
-
8160×
tCYCP*2
μs
LVD detection delay
time
TLVDDL
-
-
-
200
μs
Parameter
Symbol
Conditions
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection
reset.
*2: tCYCP indicates the APB1 bus clock cycle time.
Document Number: 002-05091 Rev. *D
Page 81 of 97
S6E1A Series
12.6.2
Low-voltage Detection Interrupt
(Ta = - 40°C to + 105°C)
Parameter
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization wait
time
LVD detection delay
time
Symbol
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
Conditions
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
Value
Typ
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
TLVDW
-
-
-
TLVDDL
-
-
-
Max
3.02
3.13
3.24
3.35
3.46
3.56
3.89
4.00
4.00
4.10
4.32
4.43
4.43
4.54
4.54
4.64
8160 ×
tCYCP*
200
Uni
t
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
μs
*:tCYCP represents the APB1 bus clock cycle time.
Document Number: 002-05091 Rev. *D
Page 82 of 97
S6E1A Series
12.7 Flash Memory Write/Erase Characteristics
(VCC = 2.7 V to 5.5 V, Ta = - 40°C to + 105°C)
Parameter
Sector erase time
Min
Large
sector
Small
sector
-
Value
Typ
0.7
Unit
Max
2.2
s
0.3
0.9
Halfword (16-bit) write time
-
30
528
μs
Chip erase time
-
2.6
8
s
Remarks
The sector erase time includes the time of
writing prior to internal erase.
The halfword (16-bit) write time excludes the
system-level overhead.
The chip erase time includes the time of
writing prior to internal erase.
Write/erase cycle and data hold time
Write/erase cycle
1,000
Data hold time (year)
Remarks
20*
10,000
10*
*: This value was converted from the result of a technology reliability assessment. (This value was converted from the result of a
high temperature accelerated test using the Arrhenius equation with the average temperature value being + 85°C).
Document Number: 002-05091 Rev. *D
Page 83 of 97
S6E1A Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Value*
Typ
Max
Sub TIMER mode
Remarks
μs
tCYCC
Ticnt
Unit
40 + 17×tCYCC
80 + 17×tCYCC
μs
360
720
μs
191
381
μs
RTC mode,
819
1090
STOP mode
*: The value depends on the accuracy of built-in CR.
The stabilization time of Main clock/Sub clock/Main PLL clock is not included.
μs
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05091 Rev. *D
Page 84 of 97
S6E1A Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL".
Document Number: 002-05091 Rev. *D
Page 85 of 97
S6E1A Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 105°C)
Parameter
Value
Symbol
Typ
Max*
Unit
208
378
μs
208
378
μs
398
758
μs
Sub TIMER mode
490
849
μs
RTC/STOP mode
288
538
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-05091 Rev. *D
Start
Page 86 of 97
S6E1A Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL".
• The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7 Power-on Reset Timing " for the detail
on the time during the power-on reset/low -voltage detection reset.
• When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
• The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05091 Rev. *D
Page 87 of 97
S6E1A Series
13. Ordering Information
Part number
S6E1A11B0AGP20000
S6E1A12B0AGP20000
S6E1A11B0AGN20000
S6E1A12B0AGN20000
S6E1A11B0AGN2B000
S6E1A12B0AGN2B000
S6E1A11C0AGV20000
S6E1A12C0AGV20000
S6E1A11C0AGN20000
S6E1A12C0AGN20000
S6E1A11C0AGN2B000
S6E1A12C0AGN2B000
S6E1A11C0AGF20000
S6E1A12C0AGF20000
On-chip
Flash
memory
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
56Kbyte
88Kbyte
Document Number: 002-05091 Rev. *D
On-chip
SRAM
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
6Kbyte
Package
Packing
Plastic LQFP (0.80mm pitch), 32pins
(LQB032)
Tray
Plastic QFN (0.50mm pitch), 32pins
(WNU032)
Plastic LQFP (0.50mm pitch), 48pins
(LQA048)
Plastic QFN (0.50mm pitch), 48pins
(WNY048)
Plastic LQFP (0.65mm pitch), 52pins
(LQC052)
Tray
Taping
Tray
Tray
Taping
Tray
Page 88 of 97
S6E1A Series
14. Package Dimensions
Package Type
LQFP 32
Package Code
LQB032
4
D
D1
24
5 7
17
17
25
16
E1
6
32
8
e
b
0.20
C A-B
TOP VIEW
9
32
8
2 5 7
1
BOTTOM VIEW
0.10 C A-B D
3
0.20 C A-B D
25
4
9
1
16
E
5
7
3
24
D
8
2
9
θ
A
A'
0.10 C
SEATING
PLANE
c
b
SECTION A-A'
0.25
10
SIDE VIEW
SYM BOL
DIM ENSIONS
M IN .
NOM . M AX.
1.60
A
A1
0.05
b
0.32
c
0.13
0.15
0.35
0.43
0.18
D
9.00 BSC
D1
7.00 BSC
e
0.80 BSC
E
9.00 BSC
E1
7.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
0°
8°
002-13879 **
PACKAGE OUTLINE, 32 LEAD LQFP
7.0X7.0X1.6 M M LQB032 REV*.*
Document Number: 002-05091 Rev. *D
Page 89 of 97
S6E1A Series
Package Type
QFN 32
Package Code
WNU032
0.10
D
C A B
D2
A
17
24
0.10 C
2X
16
(ND-1)× e
E
0.10
25
C A B
E2
5
9
9
IND EX M A RK
8
32
8
b
e
B
0.10 C
TOP VIEW
BOTTOM VIEW
2X
c
1
L
0.10
C A B
0.05
C
4
0.10 C
A
0.08 C
A1
C
SEATING PLAN E
9
SID E VIEW
DIM ENSIONS
SYM BOL
M IN.
NOM .
A
A1
0.80
0.00
0.05
D
5.00 BSC
E
5.00 BSC
b
0.20
0.25
D2
3.20 BSC
E2
3.20 BSC
e
0.50 BSC
c
0.25 REF
L
M AX.
0.35
0.40
NOTE
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
2. DIM ENSIONING AND TOLERANCIN
3. N IS THE TOTAL NU
M BER OF TERM INALS.
4. DIM ENSION "b "APPLIES TO M ETA
LLIZED TERM INAL AND IS M EASURED
BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP.IF THE TERM INAL HAS
THE OPTION AL RADIUS ON THE OTHER END OF THE TERM INAL. THE
DIM ENSION "b "SHOULD NOT BE M EASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUM BER OF
0.30
C CONFORM S TO ASM E Y14.5-1994.
TERM INALS ON D OR E SIDE.
6. M AX. PACKAGE W ARPAGE IS 0.05m m .
7. M AXIM UM ALLOW ABL E BURRS IS 0.076m m IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP W ILL BE LOCATED W ITHIN INDICATED ZONE.
9. BILATERAL COPLAN ARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS W ELL AS THE TERM INALS.
0.45
10. JEDEC SPEC
IFICATION NO. REF : N/A
002-15907 **
PACKAGE OUTLINE, 32 LEAD QFN
5.00X5.00X0.80 M M WNU032 3.20X3.20 M M EPAD (SAWN) REV**
Document Number: 002-05091 Rev. *D
Page 90 of 97
S6E1A Series
Package Type
LQFP 48
Package Code
LQA048
4
D
5 7
D1
36
25
37
24
E1
24
37
13
48
E
5
7
3
36
25
4
6
48
13
1
12
e
1
12
2 5 7
0.10 C A-B D
3
0.20 C A-B D
b
0.80
C A-B
D
8
2
A
θ
A
A'
0.80 C
SYM BOL
L1
0.25
L
A1
c
b
10
SECTION A-A'
D IM EN SIONS
M IN .
N OM . M AX.
0.00
0.20
1.70
A
A1
9
SEATING
PLANE
b
0.15
0.27
c
0.09
0.20
D
9.00 BSC
D1
7.00 BSC
e
0.50 BSC
E
9.00 BSC
E1
7.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
0°
8°
002-13731 **
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 M M LQA048 REV**
Document Number: 002-05091 Rev. *D
Page 91 of 97
S6E1A Series
Package Type
QFN 48
Package Code
WNY048
0.15
D
A
D2
25
C A B
36
0.10 C
24
2X
37
0.15
(ND-1)× e
E
C A B
E2
5
13
9
INDEX M ARK
8
48
12
B
L
b
0.10 C
TOP VIEW
0.10
0.05
C A B
C
4
BOTTOM VIEW
2X
A
0.05 C
A1
c
1
e
SEATING PLANE
9
C
SIDE VIEW
NOTE
DIMENSIONS
SYMBOL
M IN.
NOM.
MAX.
1. ALL DIMENSIONS ARE IN M ILLIMETERS.
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTALNUM BER OF TERMINALS.
A
A1
0.80
0.00
D
7.00 BSC
E
b
0.05
7.00 BSC
0.18
0.25
D2
4.65 BSC
E2
4.65 BSC
e
0.50 BSC
c
0.30 REF
L
0.45
0.50
4. DIMENSION "b"APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETW EEN 0.15 AND 0.30m m FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUMBER OF TERMINALSON D OR E SIDE.
0.30
6. MAX. PACKAGE W ARPAGE IS 0.05m m.
7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP W ILLBE LOCATED W ITHIN INDICATED ZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS W ELL AS THE TERMINALS.
0.55
10. JEDEC SPECIFICATION NO. REF : N/A
002-16422 **
PACKAGE OUTLINE, 48 LEAD QFN
7.00X7.00X0.80 M M WNY048 4.65X4.65 M M EPAD (SAWN) REV**
Document Number: 002-05091 Rev. *D
Page 92 of 97
S6E1A Series
Package Type
LQFP 52
Package Code
LQC052
4
D
5 7
D1
39
27
26
40
39
27
26
40
14
52
E1 E
4
5
7
3
6
14
52
1
2 5 7
13
e
b
0.20 C A-B D
0.13
C A-B
1
13
0.10 C A-B D
3
BOTTOM VIEW
D
8
TOP VIEW
2
A
θ
0.25
A
A'
0.10 C
SEATIN G
PLA N E
L1
L
A1
10
9
c
b
SECTIO N A-A'
SIDE VIEW
SYM BOL
DIM ENSION
M IN.
NOM . M AX.
1.70
A
A1
0.00
0.20
b
0.265
c
0.09
0.30
0.365
0.20
D
12.00 BSC
D1
10.00 BSC
e
0.65 BSC
E
12.00 BSC
E1
10.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
0°
8°
002-13880 **
PACKAGE OUTLINE, 52 LEAD LQFP
10.0X10.0X1.7 M M LQC052 REV**
Document Number: 002-05091 Rev. *D
Page 93 of 97
S6E1A Series
15. Major Changes
Spansion Publication Number: S6E1A1_DS710-00001
Page
Section
Revision 0.1
Revision 1.0 [July 16,2014]
3
1. Description
5
2. Features
6
2. Features
9
3. Product Lineup
21,22,23
6. List of Pin Functions
,
List of pin functions
24,25
6. List of Pin Functions
23
List of pin functions
12. Memory Map
40
Memory map (1)
12. Memory Map
41
Memory map (2)
14. Electrical Characteristics
46
14.1 Absolute Maximum Ratings
14. Electrical Characteristics
47
14.2 Recommended Operating Conditions
14. Electrical Characteristics
48,49,50 14.3 DC Characteristics
14.3.1 Current Rating
14. Electrical Characteristics
52
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
14. Electrical Characteristics
14.4 AC Characteristics
54
14.4.3 Built-in CR Oscillation
Characteristics
14. Electrical Characteristics
14.4 AC Characteristics
14.4.5 Operating Conditions of Main
55
PLL(In the case of using the built-in
high-speed CR clock as the input clock of
the main PLL)
14. Electrical Characteristics
56
14.4 AC Characteristics
14.4.7 Power-on Reset Timing
14. Electrical Characteristics
78
14.4 AC Characteristics
14.4.12 I2C Timing
80
83,84
85
14. Electrical Characteristics
14.5 12-bit A/D Converter
14. Electrical Characteristics
14.6 Low-voltage Detection
Characteristics
14. Electrical Characteristics
14.7 Flash Memory Write/Erase
Characteristics
Document Number: 002-05091 Rev. *D
Change Results
Initial release
Revised from "Preliminary" to "Full Production"
Revised from "TYPE1" product to "TYPE1-M0+" product
Revised "Processor version"
Revised "Conversion time" of 12-bit A/D converter
Added "Note" for accuracy of built-in CR
Revised Pin number 30 and 31 of LQFP-32 and QFN-32
Revised Function description of SOT1_x(SDA1_x)
Revised from "MTB resister" to "MTB resister(SFR)"
Revised product name and RAM address
Revised Analog pin input voltage
Added note "*2"
• Revised and added "Conditions"
• Revised the value of "TBD"
Revised the value of "Internal operating clock frequency" and
"Internal operating clock cycle time"
Revised the value of "TBD"
• Revised the value of "TBD"
• Revised the maximum value of "Main PLL clock frequency"
• Revised the value of "TBD"
• Revised from "LVDL_minimum" to "VDH_minimum"
• Revised the condition of "Noise filter"
• Revised the note for noise filter
• Revised the value of "Conversion time", "Sampling time" and
"Compare clock cycle"
• Revised the value of "State transition time to operation
permission"
• Revised the note
Revised the value of SVHR and SVHI
• Revised the value of "TBD"
• Revised the value of typical
Page 94 of 97
S6E1A Series
Page
86,88
90
Section
14. Electrical Characteristics
14.8 Return Time from Low-Power
Consumption Mode
15. Ordering Information
Change Results
Revised the value of "TBD"
Revised from "LCC-52P-M02" to "FPT-52P-M02"
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05091 Rev. *D
Page 95 of 97
S6E1A Series
Document History
Document Title: S6E1A Series, 32-bit Arm® Cortex®-M0+ FM0+ Microcontroller
Document Number: 002-05091
Revision
ECN
Orig. of
Change
Submission
Date
**
-
AKIH
07/16/2014
Description of Change
Migrated to Cypress and assigned document number 002-05091.
No change to document contents or format.
*A
5131394
AKIH
02/10/2016
Updated to Cypress template.
*B
5626717
HTER
04/13/2017
・Modified RTC description in “Features, Real-Time Clock(RTC)”.
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function (Page 2)
・Updated Package code and dimensions as follows (Page 7-12, 87-92)
- FPT-32P-M30 -> LQB032
- FPT-48P-M49 -> LQA048
- FPT-52P-M02 -> LQC052
- LCC-32P-M73 -> WNU032
- LCC-48P-M74 -> WNY048
・Updated “12.4.7 Power-on Reset Timing”.
Changed parameter from “Power Supply rise time (Tr) [ms]” to “Power
ramp rate (dV/dt) [mV/us]” and add some comments (Page 54)
・Modified the Chapter name “12.4.9 CSIO Timing” to “12.4.9 CSIO/UART
Timing”. (Page 56)
・Added the Baud rate spec in “12.4.9 CSIO Timing”. (Page 56-61)
・Modified “12.4.9 CSIO Timing”. Deleted “SPI=1, MS=0” in the titles and
added MS=0,1 in the schematic (Page 63-70)
・Deleted the DMAC description. (Page 1, 6, 36-39, 48)
Modified according to the Datasheet Errata (002-05092 Rev. **) as below.
・Deleted the Pin name of no available. (Page 8-9, 17, 21)
・Fixed typo from SCLKx_0 to SCKx_0. (Page 56-61)
・Added the note. (Page 63-69)
・Corrected the Ordering Information table. (Page 87)
*C
6062224
HUAL
02/07/2018
・Updated Figure of I/O Circuit type A and type D
・Modified the A/D Converter value in the table 12.5
the changed sampling time is for min value when AVcc < 4.5V for
S6E1AxC0A part and this value is changed from 0.5 to 0.3.
*D
6602393
XITO
Document Number: 002-05091 Rev. *D
06/24/2019
Updated to new template.
Page 96 of 97
S6E1A Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2014-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED
USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION
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product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations,
surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly,
the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other
liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates,
distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property
damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk
Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has
given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05091 Rev. *D
June 24, 2019
Page 97 of 97
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