73S8024RN-IMR/F

19-5404; Rev 2; 6/12 73S8024RN Low-Cost Smart Card Interface DATA SHEET DESCRIPTION ADVANTAGES • The 73S8024RN is a single smart card (ICC) interface IC that can be controlled by a dedicated control bus. The 73S8024RN has been designed to provide full electrical compliance with ISO 7816-3, EMV 4.0 (EMV2000) and NDS specifications. Interfacing with the system controller is done through a control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. The card clock can be generated by an on-chip oscillator using an external crystal or by connection to a clock signal. The 73S8024RN incorporates an ISO 7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3V or 5V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input VPC. Digital circuitry is separately powered by a digital power supply VDD. • • • • FEATURES • Card Interface:  Complies with ISO 7816-3, EMV 4.0, and NDS  An LDO voltage regulator provides 3V / 5V to the card from an external power supply input  Provides at least 90mA to the card  ISO 7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry  Protection includes 3 voltage supervisors that detect voltage drops on VCC (card), VDD (digital)**, and VPC (regulator) power supplies  The VDD voltage supervisor threshold value can be externally adjusted**  Over-current detection 150mA max  Card clock stop high or low*  2 card detection inputs, 1 for each possible user polarity  Auxiliary I/O lines, for C4 / C8 contact signals*  Card CLK clock frequency up to 20MHz • System Controller Interface:  3 Digital inputs control the card activation / deactivation, card reset and card voltage  4 Digital inputs control the card clock (division rate and card clock stop modes)  1 Digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults.  Crystal oscillator or host clock, up to 27MHz • Regulator Power Supply:  4.75V to 5.5V (EMV 4.0)  4.85V to 5.5V (NDS) With its embedded LDO regulator, the 73S8024RN is a cost effective solution for any application where a 5V (typically -5% +10%) power supply is available. Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided*. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power supply)**, a VPC (regulator power supply), a VCC (card power supply) or an over-heating fault. The card over-current circuitry is a true current detection function, as opposed to VCC voltage drop detection, as usually implemented in ICC interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. It allows automated card deactivation at a customized VDD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range. APPLICATIONS • • • Set-Top-Box Conditional Access and Pay-perView Point of Sales and Transaction Terminals Control Access and Identification * Pins/functions not available on 20-pin QFN package. ** User VDD_FLT threshold configuration not available on 20-pin QFN package. Rev. 2 Traditional step-up converter is replaced by a LDO regulator:  Greatly reduced power dissipation  Fewer external components are required  Better noise performance  High current capability (90mA supplied to the card) SO28 package is pin-to-pin compatible with industry-standard TDA8004 and TDA8024 Card clock STOP (high and low) mode Small format (4x4x0.85mm) 20QFN package option True card over-current detection • Digital Interfacing: 2.7V to 5.5V • • ±6kV ESD Protection on the card interface Package: SO28, 20QFN or 32QFN 1 73S8024RN Data Sheet DS_8024RN_020 FUNCTIONAL DIAGRAM NC VDDF_ADJ VDD 21 [20] {12} VPC 5 [2,9,16,25,32] 18 [17] 6 6 [3] {2} VPC FAULT DIGITAL POWER SUPPLY VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE {13} [21] 22 GND VDD FAULT VCC FAULT ICC FAULT {10} [18] 19 Int_Clk CMDVCC {11} [19] 20 RSTIN {20} [31] 3 5V/3V {14} [22] 23 OFF DIGITAL CIRCUITRY & FAULT LOGIC {18} [29] 1 CLKDIV1 {19} [30] 2 CLKDIV2 {15} [23] 24 XTALIN {16} [24] 25 XTALOUT [4] 7 CLKSTOP [5] 8 CLKLEV {17} [26] 26 I/OUC [27] AUX1UC 27 [28] AUX2UC 28 R-C OSC. ISO-7816 SEQUENCER XTAL OSC LDO REGULATOR & VOLTAGE SUPERVISORS 4 [1] {1} GND 14 [12] {6} GND 17 [15] {9} VCC ICC RESET BUFFER 16 [14] {8} RST ICC CLOCK BUFFER 15 [13] {7} CLK 10 [7] {4} PRES CLOCK GENERATION 9 [6] {3} PRES OVER TEMP TEMP FAULT 11 [8] {5} I/O ICC I/O BUFFERS 13 [11] AUX1 12 [10] AUX2 Pin numbers reference the 28SO package. [Pin numbers] reference the 32QFN package. {Pin numbers} reference the 20QFN package. Figure 1: 73S8024RN Block Diagram 2 Rev. 2 DS_8024RN_020 73S8024RN Data Sheet Table of Contents 1 Pin Description ...............................................................................................................................5 2 System Controller Interface ...........................................................................................................7 3 Power Supply and Voltage Supervision ........................................................................................8 4 Card Power Supply ........................................................................................................................9 5 Over-Temperature Monitor.............................................................................................................9 6 On-Chip Oscillator and Card Clock ...............................................................................................9 7 Activation Sequence ....................................................................................................................10 8 Deactivation Sequence ................................................................................................................12 9 OFF and Fault Detection ..............................................................................................................13 10 I/O Circuitry and Timing ...............................................................................................................13 11 Typical Application Schematic ....................................................................................................15 12 Electrical Specification ................................................................................................................16 12.1 Absolute Maximum Ratings ....................................................................................................16 12.2 Recommended Operating Conditions .....................................................................................16 12.3 Package Thermal Parameters ................................................................................................16 12.4 Smart Card Interface Requirements........................................................................................17 12.5 Characteristics: Digital Signals................................................................................................19 12.6 DC Characteristics..................................................................................................................20 12.7 Voltage / Temperature Fault Detection Circuits .......................................................................20 13 Mechanical Drawing (20QFN) ......................................................................................................21 14 Package Pin Designation (20QFN)...............................................................................................22 15 Mechanical Drawing (32QFN) ......................................................................................................23 16 Package Pin Designation (32QFN)...............................................................................................24 17 Mechanical Drawing (SO).............................................................................................................25 18 Package Pin Designation (SO).....................................................................................................25 19 Ordering Information....................................................................................................................26 20 Related Documentation................................................................................................................26 21 Contact Information .....................................................................................................................26 Revision History ...................................................................................................................................27 Rev. 2 3 73S8024RN Data Sheet DS_8024RN_020 Figures Figure 1: 73S8024RN Block Diagram ...................................................................................................... 2 Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low .............................................. 10 Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low ........................................... 11 Figure 4: Deactivation Sequence ........................................................................................................... 12 Figure 5: Timing Diagram – Management of the Interrupt Line OFF ....................................................... 13 Figure 6: I/O and I/OUC State Diagram ................................................................................................. 14 Figure 7: I/O – I/OUC Delays Timing Diagram ....................................................................................... 14 Figure 8: 73S8024RN – Typical Application Schematic.......................................................................... 15 Figure 9: 20QFN Mechanical Drawing ................................................................................................... 21 Figure 10: 20QFN Pin Out ..................................................................................................................... 22 Figure 11: 32QFN Mechanical Drawing ................................................................................................. 23 Figure 12: 32QFN Pin Out ..................................................................................................................... 24 Tables Table 1: Choice of VCC Pin Capacitor....................................................................................................... 9 Table 2: Card Clock Frequency ............................................................................................................... 9 4 Rev. 2 DS_8024RN_020 1 73S8024RN Data Sheet Pin Description CARD INTERFACE Name Pin 28SO 11 Pin 20QFN 5 AUX1 13 – AUX2 12 – RST CLK 16 15 8 7 PRES 10 4 PRES 9 3 VCC 17 9 GND 14 6 I/O Pin Description 32QFN 8 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. 14 Card reset: provides reset (RST) signal to card. 13 Card clock: provides clock signal (CLK) to card. The rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on XTALIN and CLKDIV selections. 7 Card Presence switch: active high indicates card is present. Should be tied to GND when not used, but it Includes a high-impedance pull-down current source. 6 Card Presence switch: active low indicates card is present. Should be tied to VDD when not used, but it Includes a high-impedance pull-up current source. 15 Card power supply – logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. 12 Card ground. MISCELLANEOUS INPUTS AND OUTPUTS Name Pin 28SO 24 Pin 20QFN 15 Pin 32QFN 23 XTALOUT 25 16 24 VDDF_ADJ 18 – 17 NC 5 – 2, 9, 16, 25, 32 XTALIN Description Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. VDD fault threshold adjustment input: this pin can be used to adjust the VDDF values (that controls deactivation of the card). Must be left open if unused. Non-connected pin. POWER SUPPLY AND GROUND Name VDD Pin 28SO 21 Pin 20QFN 12 Pin 32QFN 20 VPC GND GND 6 4 22 2 1 13 3 1 21 Rev. 2 Description System interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. LDO Regulator ground. Digital ground. 5 73S8024RN Data Sheet DS_8024RN_020 MICROCONTROLLER INTERFACE Name Pin 28SO 19 Pin 20QFN 10 5V/#V 3 20 CLKSTOP 7 – CLKLVL 8 – CLKDIV1 CLKDIV2 1 2 18 19 CMDVCC Pin Description 32QFN 18 Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, if a card is present. 31 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default this pin high (selection of 5V card) when not connected. 4 Stops the card clock signal during a card session when set high (card clock STOP mode). Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used. 5 Sets the logic level of the card clock STOP mode when the clock is de-activated by setting pin 7 high. Logic low selects card STOP low. Logic high selects card STOP high. Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used. 29 Sets the divide ratio from the XTAL oscillator (or external 30 clock input) to the card clock. These pins include pull-down resistors. OFF 23 14 22 RSTIN 20 11 19 I/OUC 26 17 26 AUX1UC 27 – 27 AUX2UC 28 – 28 6 CLKDIV1 CLKDIV2 CLOCK RATE 0 0 XTALIN/8 0 1 XTALIN/4 1 1 XTALIN/2 1 0 XTALIN Interrupt signal to the processor. Active Low - Multifunction indicating fault conditions and card presence. Open drain output configuration. It includes an internal 21kΩ pull-up to VDD. Reset Input: This signal is the reset command to the card. System controller data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. Rev. 2 DS_8024RN_020 73S8024RN Data Sheet 2 System Controller Interface Three separated digital inputs allow direct control of the card interface from the host as follows: • Pin CMDVCC: When low, starts an activation sequence. • Pin RSTIN: controls the card Reset signal (when enabled by the sequencer). • Pin 5V/#V: Defines the card voltage. Card clock is controlled by four digital inputs: • CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal or external clock). • • CLKSTOP (active high) allows card power down mode by stopping the card clock. CLKLEV defines the card clock level of the card power down mode. Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (Low = No card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence. Rev. 2 7 73S8024RN Data Sheet DS_8024RN_020 3 Power Supply and Voltage Supervision The 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for VPC and VCC are linked so that a fault is generated to activate a deactivation sequence when the voltage VPC becomes lower than VCC. It allows the 73S8024RN to operate at lower VPC voltage when using 3V cards only. The voltage regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 and NDS specifications. The VPC voltage supervisor threshold values are defined from applicable standards (EMV and NDS). A third voltage supervisor monitors the VDD voltage. It is used to initialize the ISO 7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the 32QFN package, not supported in the 20QFN package) is used to connect an external resistor REXT to ground to raise the VDD fault voltage to another value VDDF. The resistor value is defined as follows: REXT= 56kΩ /(VDDF - 2.33) An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas. R3 = 24000 / Kx R1 = R3*(Kx / (1 – Kx)) Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:  Kx = (2.789 / 2.7) - 0.6125 = 0.42046. Solving for R3 gives:  R3 = 24000 / 0.42046 = 57080. Solving for R1 gives:  R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412. Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ. These values give an equivalent resistance of Kx = 0.4228, a 0.6% error. If the 2.3V default threshold is used, this pin must be left unconnected. The 20QFN package has the VDD fault threshold fixed at this default value. 8 Rev. 2 DS_8024RN_020 73S8024RN Data Sheet 4 Card Power Supply The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO 7816-3 sequencer. Card voltage selection is carried out by the digital input 5V/#V. Choice of the VCC Capacitor: Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card are different. An external capacitor must be connected between the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the transient requirements. The type and value of this capacitor can be optimized to meet the desired specification. Table 1 shows the recommended capacitors for each VPC power supply configuration and applicable specification. Table 1: Choice of VCC Pin Capacitor Specification Requirements System Requirements Min VCC Voltage Allowed During Transient Current Max Transient Current Charge Min VPC Power Supply Required EMV 4.0 4.6V 30nA.s 4.75V ISO 7816-3 4.5V 20nA.s 4.75V NDS 4.6V 40nA.s 4.85V Specification Capacitor Type X5R/X7R w/ ESR < 100mΩ Capacitor Value 3.3 µF 1 µF 1 µF Note: Capacitor value for NDS implementation is also defined by the deactivation time requirement. 5 Over-Temperature Monitor A built-in detector monitors die temperature. Upon an over-temperature condition, a card deactivation sequence is initiated, and an error or fault condition is reported to the system controller. 6 On-Chip Oscillator and Card Clock The 73S8024RN device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. The card clock frequency may be chosen between four different division rates, defined by digital inputs CLKDIV 1 and CLKDIV 2, as per Table 2. Table 2: Card Clock Frequency CLKDIV1 0 0 1 1 CLKDIV2 0 1 0 1 CLK ⅛ XTALIN ¼ XTALIN XTALIN ½ XTALIN Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs CLKSTOP and CLKLEV (not supported in the 20QFN package). Rev. 2 9 73S8024RN Data Sheet DS_8024RN_020 7 Activation Sequence The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no over-temperature fault or no VDD fault. The following steps show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: • CMDVCC is set low. • Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low to report a fault to the system controller, and the power VCC to the card is shut off. • • • Turn I/O (AUX1, AUX2) to reception mode at the end of (t2). CLK is applied to the card at the end of (t3). RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not set RST high until 42000 clock cycles after the start of CLK. CMDVCC VCC I/O CLK RSTIN RST t1 t2 t3 t4 t1 = 0.510 ms (timing by 1.5MHz internal Oscillator) t2 = 1.5µs, I/O goes to reception state t3 = >0.5µs, CLK starts t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low 10 Rev. 2 DS_8024RN_020 73S8024RN Data Sheet The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: • • • • • CMDVCC is set low. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the system controller, and the power VCC to the card is shut down. Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode. CLK is applied to the card at the end of (t3), after I/O is in reception mode. RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not set RST high until 42000 clock cycles after the start of CLK. CMDVCC VCC I/O CLK RSTIN RST t1 t2 t3 t4 t1 = 0.510 ms (timing by 1.5MHz internal Oscillator) t2 = 1.5µs, I/O goes to reception state t3 = > 0.5µs, CLK active t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low Rev. 2 11 73S8024RN Data Sheet DS_8024RN_020 8 Deactivation Sequence Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated when VPC goes lower than VCC. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: • • • • RST goes low at the end of t1. CLK is set low at the end of t2. I/O goes low at the end of t3. Out of reception mode. VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low. CMDVCC -- OR -- OFF RST CLK I/O VCC t1 t1 = t2 = t3 = t4 = t5 = t2 t3 t4 t5 > 0.5µs, timing by 1.5MHz internal Oscillator > 7.5µs > 0.5µs > 0.5µs depends on VCC filter capacitor. For NDS application, CF=1µF makes t1 + t2 + t3 + t4 + t5 < 100µs Figure 4: Deactivation Sequence 12 Rev. 2 DS_8024RN_020 73S8024RN Data Sheet 9 OFF and Fault Detection There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process. The Figure 5 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside the card session: OFF is low by card extracted OFF is low by any fault PRES OFF CMDVCC VCC outside card session within card session within card session Figure 5: Timing Diagram – Management of the Interrupt Line OFF 10 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. Within a card session and when the I/O reception state is turn on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. Figure 6 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 7. Rev. 2 13 73S8024RN Data Sheet DS_8024RN_020 Neutral State No I/O reception Yes I/O & not I/OUC No Yes No I/OUC & not I/O Yes I/OUC in I/OICC in No No I/OUC I/O yes yes Figure 6: I/O and I/OUC State Diagram I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 25ns tI/OUC_LH = 25ns Figure 7: I/O – I/OUC Delays Timing Diagram 14 Rev. 2 DS_8024RN_020 73S8024RN Data Sheet 11 Typical Application Schematic AUX2UC_to/from_uC AUX1UC_to.from_uC See NOTE 5 I/OUC_to/from_uC VDD See NOTE 6 CLKDIV1_from_uC See NOTE 3 CLKDIV2_from_uC 5V/3V_select_from_uC External_clock_from uC VDD VPC See NOTE 2 C4 100nF C5 10uF CLKSTOP_from_uC CLKLVL_from_uC See NOTE 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLKDIV1 CLKDIV2 5V3V_ GND NC VPC CLKSTOP CLKLVL PRESB PRES I/O AUX2 AUX1 GND 73S8024RN AUX2UC AUX1UC I/OUC XTALOUT XTALIN OFF_ GND VDD RSTIN CMDVCC_ VDDF_ADJ VCC RST CLK SO28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 - OR - R3 Rext2 C2 VDD See NOTE 1 C6 R1 Rext1 100nF Y1 22pF C3 CRYSTAL 22pF See NOTE 4 See note 7 OFF_interrupt_to_uC RSTIN_from_uC CMDVCC_from_uC 8 7 6 5 4 3 2 1 NDS & ISO7816=1uF, EMV=3.3uF Low ESR (