MAX24001TL+T

MAX24001 2.5Gbps Tx Burst-Mode Laser Transceiver General Description The MAX24001 is a complete burst-mode laser driver transmitter and limiting amplifier receiver for use within fiber optic modules for FTTx applications. A fully compliant GPON/GEPON module with digital diagnostics can be realized when used with a 2KB EEPROM and suitable optics. Alternatively, a microcontroller can be used in conjunction with the MAX24001; however, this is not a necessity in order to achieve SFF-8472 compliance. Functional Diagram 2.5Gbps Limiting Receiver RX_IN+ RX_OUT+ RX_OUTRX_INLOS/SD TX_FAULT / DAC APD_CTRL ADC RSSI SCL_SLAVE SDA_SLAVE SCL_MASTER SDA_MASTER TSENSE TSENSE_RET MPD SLEEP The 2.5Gbps limiting receive path features programmable output swing control, rate selection, and OMA-based loss-of-signal detection. Functions are also provided which facilitate the implementation of APD biasing without the need for an external DCDC converter. The burst-mode laser driver has temperature compensated modulation control using a lookup table. Closed-loop control of laser power incorporates tracking error compensation and has multiple options for rapidly settling the laser power thus enabling fast registration and shutdown on the network. Diagnostics are enhanced with the inclusion of programmable transmit signal detection during bursts, and rogue ONU detection between bursts. This is linked to a laser safety system which allows the modulation and bias currents to be shut off in response to a range of different fault conditions detected on-chip. The transmit and receive systems are independently powered and can respond separately to the SLEEP pin. The MAX24001 is highly configurable from either EEPROM or low-cost MCU using a two-wire interface. Applications TX_DISABLE TX_SD / TX_FAULT BEN+ BEN- BIAS TX_IN+ TX_IN- TX_OUT+ TX_OUT- 2.5Gbps Burst mode laser driver ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ Features 2.5Gbps Limiting Receiver Integrated APD Bias Loop With Overvoltage And Overcurrent Protection OMA-Based LOS Detection 1.25Gbps to 2.5Gbps Laser Driver CML, LVPECL, HSTL, SSTL-Compatible Inputs Open and Closed-Loop Bias Control Temperature-Compensated IMOD Control Highly Configurable Laser Safety System Transmit TX_SD and Rogue ONU Detection SFP MSA and SFF-8472 Digital Diagnostics Integrated Temperature Sensor Power-Saving SLEEP Modes External DAC, ADC, and PWM Interfaces Ordering Information GPON, GEPON, Gigabit Ethernet PART TEMP RANGE PIN-PACKAGE MAX24001TL+ -40°C to +95°C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 19-6460; Rev 2; 2/14 Maxim Integrated 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. ABSOLUTE MAXIMUM RATINGS Voltage Range on VDD_TX, VDD_TXO, VDD_RX, VDD_RXO ........................................................................... -0.3V to +3.65V Voltage Range on Any Pin Not Otherwise Specified (with respect to VSS_* ) ........................... -0.5V to (VDD_* + 0.5V) Continuous Power Dissipation (TA = +70°C) TQFN (derate 35.7mW/°C above +70°C) ................................................................................................. 2857.1mW Operating Temperature Range ............................................................................................................ -40°C to +95°C Junction Temperature ...................................................................................................................................... +150°C Storage Temperature ......................................................................................................................... -70°C to +150°C Lead Temperature (soldering, 10s) ................................................................................................................. +300°C Soldering Temperature (reflow) ....................................................................................................................... +260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Operating Supply Voltage SYMBOL CONDITIONS VDD MIN TYP MAX UNITS 3.0 3.3 3.6 V VDD 0.75 V ROSA sourcing to RSSI pin RSSI Pin Compliance ROSA sinking from RSSI pin 0.75 V BIAS Pin Compliance 0.8 V TX_OUT Pin Compliance 0.8 V MPD Input Current For correct APC loop operation 40 2000 µA MPD Input Capacitance For correct APC loop operation 4 20 pF Junction Temperature -40 +120 °C Case Temperature -40 +95 °C Device not guaranteed to meet parametric specifications when operated beyond these conditions. Permanent damage may be incurred by operating beyond these limits. ELECTRICAL CHARACTERISTICS (VCC = 2.97V to 3.63V, TA = -40°C to +95°C.) (Note 1) Note 1: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25°C, 3.3V. CONTINUOUS RATINGS PARAMETER Supply Current Maxim Integrated SYMBOL CONDITIONS IDD Excluding laser bias and modulation currents, 20mA bias and modulation current, Rx CML output 400mVP-P MIN TYP 136 MAX UNITS mA 2 RECEIVER CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Differential Input Impedance MIN TYP MAX UNITS 80 100 120 Ω Maximum Input Data Rate 2.5 Gbps Minimum Input Data Rate 1.25 Gbps Differential, BER = 1E-10, 2.5Gbps, Input Sensitivity 6.5 PRBS 223-1 pattern 13 mVP-P Deterministic Jitter 2.5Gbps, VOUT = 800mVP-P, VIN between 25mVP-P differential and 1000mVP-P 40 psP-P Random Jitter 2.5Gbps, VOUT = 800mVP-P, VIN between 25mVP-P differential and 1000mVP-P 2.7 psRMS Output Rise/Fall Times 2.5Gbps, VOUT = 800mVP-P, VIN = 25mVP-P differential and 1000mVP-P 60 ps 30 kHz Low-Frequency Cutoff Output Impedance 1MHz differential Minimum Output Swing Differential, 4-bit programmable (Note 2) Maximum Output Swing Differential, 4-bit programmable (Note 2) 80 100 120 Ω 200 240 mVP-P 800 880 MIN TYP mVP-P Note 2: Measured with 1111111100000000 pattern. LOSS OF SIGNAL AND RSSI CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MAX UNITS Maximum OMA LOS Assert Time 11 μs Maximum OMA LOS Deassert Time 11 μs Maximum LOS Threshold Setting 400 mVP-P LOS DAC = 50 (Note 3) 67 mVP-P LOS DAC = 105 (Note 3) 143 mVP-P Sourced or sunk from RSSI pin 1200 μA LOS Assert/Deassert Level Maximum RSSI Current Level Note 3: LOS assert and deassert levels can be set independently to define hysteresis. Maxim Integrated 3 TRANSMITTER CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum Input Data Rate PRBS23 2.488 Gbps Minimum Input Data Rate PRBS23 1.25 Gbps Maximum Modulation Current 80 Minimum Modulation Current Measured using 15Ω effective termination, Maximum Electrical Rise/Fall Time (20% to 80%) IMOD = 8mAP-P to 80mAP-P mAP-P 8 mAP-P 96 ps Total Jitter PRBS15, 2.488Gbps, IMOD = 8mAP-P to 80mAP-P, differential electrical measurement 65 Deterministic Jitter PRBS15, 2.488Gbps, IMOD = 8mAP-P to 80mAP-P, differential electrical measurement 45 mUIP-P Random Jitter PRBS15, 2.488Gbps, IMOD = 8mAP-P to 80mAP-P, differential electrical measurement 1.11 mUIRMS 90 mA Maximum Bias Current 175 mUIP-P BURST TIMINGS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 7 12 ns Disable: Bias current reduced to 20% of its maximum value. Burst Enable/Disable Time (Electrical) Enable: Bias current increased to 90% of desired bias plus modulation current Target bias current > 3mA Minimum Burst Length to Update APC Loop During closed-loop operation 90 ns Minimum Burst Gap During closed-loop operation 75 ns 1.2 ms From power-on, negation of TX_DISABLE, or negation of SLEEP to 90% of desired optical power. Maximum Initial Mean Power Control Settling Time (APC Loop) Fast settling algorithm enabled, no fast start LUT. Bias current overshoot < 10% Bias current > 4mA Maxim Integrated 4 TRANSMITTER INPUT CHARACTERISTICS TX_IN (differential AC or DC coupled) BEN (differential DC coupled) VIH Input Voltage Range TX_IN (differential AC or DC coupled) BEN (differential DC coupled) VDD + 0.1 0.2V VPP (diff) TX_IN (differential AC or DC coupled) BEN (differential DC coupled) VDD - 0.88 V IH(min) VDD - 1.16 VIL(max) VDD - 1.48 VIL(max) 0.8V V IL(min) VDD - 1.81 V IL(min) -0.3 VIH(max) VDD - 2.0 CML 3V3 2V V IH(min) 1.6V V IL VDD VIH(max) LVCMOS/LVTTL 3V3 LVPECL 3V3 Typical I/O ranges for TX_IN and BEN are shown. TX_IN and BEN inputs are also compatible with HSTL and SSTL for low-voltage operation. DIGITAL I/O CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Time To Initialise From power-up or hot plug 71 ms TX_DISABLE Assert TX_DISABLE assert to optical disable 0.3 μs TX_DISABLE Negate TX_DISABLE negate to optical enable 0.5 ms TX_DISABLE to Reset Time TX_DISABLE must be held high to reset TX_FAULT 0.155 μs Maximum Delay BEN Change to TX_SD Response Rising or falling edge 100 ns Light During Gap to Laser Shutdown Rogue ONU 100 μs SLEEP, TX_DISABLE inputs LOS, TX_SD outputs VDD VIH(max) 2V V IH(min) VDD VIH(max) VDD - 0.5V V IH(min) VIL(max) 0.8V VIL(max) V IL(min) Vss V IL(min) 0.4V Low Speed LVTTL 3V3 Vss Low Speed LVTTL 3V3 Typical I/O Ranges for SLEEP, TX_DISABLE, LOS and TX_SD Maxim Integrated 5 PERIPHERAL FUNCTIONS PARAMETER SYMBOL CONDITIONS MIN TYP Module 3V3 supply voltage above which reset will not be asserted MAX UNITS 2.5 V Power-On-Reset (POR) Voltage Module 3V3 supply voltage below which reset is guaranteed 2.2 V APD Control PARAMETER SYMBOL CONDITIONS MIN TYP ADC Pin Minimum Voltage ADC Pin Maximum Voltage MAX UNITS 1.30 V 2.25 V DAC Pin Minimum Current 0 mA DAC Pin Maximum Current 0.45 mA DAC Pin Compliance 1.5 V Minimum PWM frequency 250 kHz Maximum PWM frequency 2 MHz Load current change from 20μA to 1mA 2 ms PWM Frequency Step Response Settling Time SLEEP PARAMETER Sleep Assert/Deassert Maxim Integrated SYMBOL CONDITIONS Time to allow first operation or enter sleep from deassertion of sleep pin MIN TYP MAX UNITS 100 ns 6 TWO-WIRE INTERFACE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN Maximum SCL Clock Frequency TYP MAX UNITS 400 kHz Minimum SCL Clock LOW Period tLOW 1200 ns Minimum SCL Clock HIGH Period tHIGH 600 ns Minimum Setup Time For A Repeated START Condition tSU:STA 600 ns Minimum Hold Time (Repeated) START Condition tHD:STA 600 ns Minimum Data Hold Time tHD:DAT 0 ns Minimum Data Setup Time tSU:DAT 100 ns Minimum Setup Time for STOP Condition tSU:STO 600 ns Minimum Bus Free Time Between a STOP and START Condition tBUF 1200 ns Maximum Rise and Fall Times of Both SDA and SCL Signals tR, tF 300 ns Minimum Rise and Fall Times of Both SDA and SCL Signals tR, tF Cx ns 10 pF Cb = capacitance of a single bus line Cx = 20 + 0.1 x Cb Maximum Capacitance for Each I/O Pin t SU:STA tSU:DAT tHD:DAT t SU:STO t BUF SDA SCL t HD:STA Maxim Integrated tHIGH t LOW tR tF 7 DIGITAL DIAGNOSTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TEMPERATURE Reporting Resolution -40°C to +95°C range 0.85 °C/LSB Maximum Inaccuracy Single-point calibration, external mode ±2 °C Reporting Resolution 3.0V to 3.6V range 10 mV/LSB Maximum Inaccuracy Calibrated, within the supply reporting range ±3 % 0.392 mA/LSB POWER SUPPLY TX BIAS Reporting Resolution 5mA to 90mA range Maximum Inaccuracy Calibrated, within the Tx bias reporting range ±10 % mpd_range = 00, 40μA to 200μA 0.78 μA/LSB mpd_range = 01, 100μA to 800μA 3.125 μA/LSB mpd_range = 10, 400μA to 2000μA 12.5 μA/LSB Calibrated, within the MPD operating range ±20 % 0 to 16μA (Note 4) 0.5 μA/LSB 16μA to 206μA (Note 4) 2.0 μA/LSB 206μA to 1000μA (Note 4) 8.0 μA/LSB 3μA to 25μA, calibrated (Note 4) ±25 % 25μA to 1000μA, calibrated (Note 4) ±10 % TX POWER MPD Current Reporting Resolution Maximum Inaccuracy RX POWER RSSI Current Reporting Resolution Maximum Inaccuracy Note 4: rx_rssi_scale = 00 (x1 gain) range and resolution settings can be changed to improve accuracy. Maxim Integrated 8 36 35 34 33 32 VSS_DIG VDD_RX 37 RSSI VSS_RX 38 RX_IN- 39 RX_IN+ 40 VSS_RX ADC 1 DAC/TX_FAULT TOP VIEW APD_CTRL Pin Configuration 31 SCL_MASTER 1 30 VDD_DIG SDA_MASTER 2 29 SLEEP VDD_RXO 3 28 VDD_TXO VSS_RXO 4 27 VSS_TXO RX_OUT- 5 26 TX_OUT- RX_OUT+ 6 25 TX_OUT+ VSS_RXO 7 24 VSS_TXO LOS/SD 8 23 BIAS SCL_SLAVE 9 22 MPD SDA_SLAVE 10 21 TX_SD/TX_FAULT MAX24001 18 19 20 RREF 17 BEN- 16 BEN+ TSENSE_RET 15 VSS_TX TSENSE 14 TX_IN+ 13 TX_IN- 12 VDD_TX 11 TX_DISABLE EP TQFN (5mm x 5mm) Maxim Integrated 9 Pin Description PIN NAME DIR TYPE FUNCTION 1 SCL_MASTER O/P LVTTL Two-Wire Interface Clock Connection To EEPROM, with Internal 10kΩ Pullup Resistor 2 SDA_MASTER I/O LVTTL Two-Wire Interface Data Connection To EEPROM, with Internal 10kΩ Pullup Resistor 3 VDD_RXO Analog +3.3V Receiver Output Power Supply 4 VSS_RXO Analog GND Receiver Output Ground Connection 5 RX_OUT- O/P High Speed Limiting Receiver Inverted Output. 100Ω differential to RX_OUT+. 6 RX_OUT+ O/P High Speed Limiting Receiver Noninverted Output. 100Ω differential to RX_OUT-. 7 VSS_RXO Analog GND 8 LOS/SD O/P LVTTL Loss-Of-Signal Indication. Open drain with external 4.7kΩ to 10kΩ resistor. 9 SCL_SLAVE I/P LVTTL Two-Wire Interface Clock Connection To Host. with external 10kΩ pullup resistor 10 SDA_SLAVE I/O LVTTL Two-Wire Interface Data Connection To Host. with external 10kΩ pullup resistor 11 TX_DISABLE I/P LVTTL Internally pulled high to VDD_DIG with a 7.5kΩ resistor 12 TSENSE Analog Analog Temperature Sensor Current Force 13 TSENSE_RET Analog Analog Temperature Sensor Current Return 14 VDD_TX Analog +3.3V 15 TX_IN- I/P High Speed Transmitter Input Signal Inverted 16 TX_IN+ I/P High Speed Transmitter Input Signal Noninverted 17 VSS_TX Analog GND 18 BEN+ I/P High Speed Receiver Output Ground Connection Transmitter Power Supply Transmitter Ground Connection Burst-Enable Noninverted 19 BEN- I/P High Speed 20 RREF Analog Analog Connects to External Precision Resistor Burst-Enable Inverted 21 TX_SD/ TX_FAULT O/P LVTTL Push-Pull Signal Detect Indication. Can be configured as open-drain TX_FAULT output, pulled high externally using a 4.7kΩ to 10kΩ resistor. 22 MPD I/P Analog Monitor Photodiode Input 23 BIAS Analog Analog Bias Current Sink 24 VSS_TXO Analog GND 25 TX_OUT+ O/P High Speed Laser Data Differential Drive Output 26 TX_OUT- O/P High Speed Laser Data Differential Drive Output 27 VSS_TXO Analog GND Transmitter Output Ground Connection 28 VDD_TXO Analog +3.3V Transmitter Output Power Supply 29 SLEEP I/P LVTTL Sleep Mode Select 30 VDD_DIG Analog +3.3V Digital Power Supply 31 VSS_DIG Analog GND Digital Ground Connection 32 RSSI I/P Analog 33 VDD_RX Analog +3.3V Receiver Power Supply 34 VSS_RX Analog GND Receiver Ground Connection 35 RX_IN- I/P CML Receiver Input Signal. Differential 100Ω with RX_IN+. 36 RX_IN+ I/P CML Receiver Input Signal. Differential 100Ω with RX_IN-. 37 VSS_RX Analog GND Receiver Ground Connection 38 ADC I/P Analog Voltage Input to On-Chip ADC 39 DAC/TX_FAULT O/P Analog Current Output For APD Loop Control. Can be configured as open-drain TX_FAULT output, pulled high externally using a 4.7kΩ to 10kΩ resistor. 40 APD_CTRL O/P LVTTL 3V3 Push-Pull APD Bias PWM Output. Can be configured as open-drain APD bias shutdown pin, pulled high externally using a 4.7kΩ to 10kΩ resistor. — EP Analog GND Maxim Integrated Transmitter Output Ground Connection Rx Photodiode Monitor (RSSI) Exposed Pad. Solder to board to provide effective thermal connection to circuit board 10 Detailed Description 2.5Gbps Limiting Receiver PREEMP RX_IN+ 50R FILTER RX_OUT+ CML I/P BUFF LIMIT RX_OUT- Registers And memory SCL_MASTER SDA_MASTER Diag RSSI TSENSE_RET /1, /4, /16 Power monitor /1 Tx Signal Detect ben fault shutdown invert Laser safety I/P interface BEN- SINK/ SOURCE TSENSE tracking_adjust BEN+ LOS/SD Temp Sensor Diagnostics And SFF-8472 SLEEP 0V Vdd DEBOUNCE gain Host interface LOS DAC mirror ADC SCL_SLAVE SDA_SLAVE invert apd bias APD Control APD_CTRL RX_IN- threshold rate swing 50R APD DAC DAC Vcm MPD TX_DISABLE TX_SD/ TX_FAULT invert pwadjust 0V Vdd 0V Vdd TX_IN+ target power APC Loop control PRE DRIVE BIAS TX_OUTmodulation 0V Vdd DRIVE TX_OUT+ I/P interface TX_IN- BIAS DAC MOD DAC Modulation control 2.5Gbps Burst mode laser driver Figure 1. MAX24001 Block Diagram Maxim Integrated 11 Receiver Signal Path [Control Register Address Range A4h: 90h to 93h] The signal arriving at RX_IN is terminated with a 100Ω load to minimise return loss. An input buffer adds peaking to compensate for up to 10mm of FR4. The level of peaking is controlled by the rx_input_peak register. The signal can also be inverted using rx_invert. rx_ratesel0 or rx_ratesel1 00 01 BANDWIDTH (GHz) BIT RATE (Gbps) 1 1.8 1.25 2.488 The received signal is then band limited to one of two rates selected by the soft_rate_select bit of the system_control register (A2h: 7Bh). If soft_rate_select = ‘0’ then select rx_ratesel0 else select rx_ratesel1. Filter bandwidths are nominally designed to be 0.7x the available data rates. The CML output stage is a high-current driver that delivers a 200mV to 880mV signal from a low-impedance 50Ω output. The rx_output_swing register is used to control the signal at RX_OUT with 45mV resolution. Preemphasis may also be applied to the output signal using rx_preemphasis. The pre-emphasis (defined as ((B-A)/B) x 100) can be set to 0%, 2%, 6% or 10%. The pre-emphasis ratio remains relatively constant when A is adjusted. A B Figure 2. Rx Pre-Emphasis Control The CML, pre-emphasis and limiting stages may be automatically powered down under loss-of-signal conditions (LOS = ‘1’) by setting the los_squelch register. This feature uses the debounced LOS signal prior to any inversion caused by setting los_invert. Alternatively, the CML, pre-emphasis and limiting stages may be directly powered down by setting the squelch register. Receiver Loss of Signal (LOS) [Control Register Address Range A4h: 9Bh to 9Dh] los_assert 0 los_deassert 1 DAC RX_IN+- los_raw Debounce Peak detect los_invert LOS los_inhibit Maxim Integrated 12 Figure 3. LOS Detection System When the peak signal amplitude detected at RX_IN drops below the threshold level set by los_assert then a lossof-signal condition is reported on the LOS pin and the los_deassert threshold is selected. The signal amplitude must then rise back above the threshold set by los_deassert before the loss-of-signal condition is removed and the los_assert threshold is re-selected. The two thresholds can be used to introduce a wide range of hysteresis into LOS detection. The deassert threshold level should be higher than the assert threshold for correct operation. When the comparator output (los_raw) changes, the los debounce circuit holds the new value at its output for a programmable period of time controlled by los_debounce. Longer debounce timeout periods may be required to accommodate the much longer timeframe pulses caused by the response of the TIA AGC when the signal is suddenly interrupted. The decay of the differential signal is characterized by an unwanted signal crossover as shown in the diagram below. The unwanted pulse on los_raw is rejected by setting the debounce period to > 50μs. Crosses deassert threshold Crosses assert threshold Received signal in 50us typical los_raw Debounce timeout period LOS Figure 4. LOS Debounce Operation The los_invert register is used to configure the pin for Signal Detect (SD) instead of LOS. An output mask (los_inhibit) holds the output to the LOS pin high after power-on reset until the configuration register load from EEPROM or microcontroller is complete. This avoids multiple transitions on the LOS pin during initialization, which can cause fault conditions to occur at the system level. Transmitter Signal Path [Control Register Address Range A4h: 9Eh to A1h] The input to the transmitter signal path supports CML, LVPECL, HSTL, and SSTL electrical signalling schemes with a minimum of external components. The input may be either DC or AC coupled. An external 100Ω resistor provides differential termination. The internal potential dividers set the common mode level at 2.0V when the input is AC-coupled. AC coupled mode only Vdd Vdd 16k TX_IN- 16k 5k I/P interface 100R 5k TX_IN+ 24k 24k 0V 0V Figure 5. TX_IN and BEN Input Termination and Signal Conditioning Maxim Integrated 13 The laser modulation current is controlled by the tx_moddac register with a resolution of 375μA per LSB (nominally). This register may be set by the host, or alternatively set the modlut_en bit to cause the tx_moddac register to be automatically refreshed from the modulation lookup table (LUT) every 10ms. The modulation LUT is stored in external EEPROM at TWI slave address A6h, register address range 80h to FFh. It is indexed using the upper 7 bits of temperature_uncal. If the modramp_en register is set then the value in tx_moddac ramps progressively from the old value to the new value by 1 LSB every cycle of the internal 64MHz clock. This prevents glitches from occurring in the DAC. If ramping is disabled then updates to tx_moddac are effective immediately. The modulation current is switched off between bursts and when the laser safety system asserts a shutdown. burst_invert is used to invert the differential signal on BEN±. tx_invert is used to invert the polarity of the transmit signal path. Eye Optimization The pulse width of the transmitted signal is adjusted by moving the crossing point of the eye up or down using tx_pwadjust_dir. Use the tx_pwadjust_size to control the amount of adjustment, in the direction set by tx_pwadjust_dir. At maximum adjustment, the zero crossing point (a) is moved by 40% of the 0-pk eye opening (b). The tx_pwadjust_hires register can be used to halve the adjustment step size and thus increase resolution (at the expense of halving the range). b 0V Differential signal is balanced (tx_pwadjust_size = 000) a Zero crossing point moved up Width of zero pulses decreases (tx_pwadjust_dir = 0) Zero crossing point moved down Width of zero pulses increases (tx_pwadjust_dir = 1) Figure 6. Crossing Point Adjustment The tx_snubber register is used to snub out overshoot or undershoot in the output eye. Tx Signal Detect [Control Register Address Range A4h: ADh to AEh, BEh to BFh] The Tx Signal Detect feature comprises two related areas of functionality: For external signal and rogue ONU fault detect by the host, the MAX24001 controls the TX_SD pin as follows: TX_SD = '1' when there is light; TX_SD = '0' when there is no light from the laser. For on-chip "Rogue ONU fault detect", the MAX24001 detects the presence of light during the burst gap. This fault condition is input to the laser safety system which can then optionally shut down the laser within 100μs of light being detected. Current threshold Rogue ONU Fault Detect Laser Safety System tx_ shutdown tx_ fault 0 MPD TX_ SD Control TX_SD / TX_FAULT 1 BEN Figure 7. TX_SD Pin Signal Generation Maxim Integrated 14 The MPD current is compared with a threshold current set by the txsd_threshold register. This determines the MPD current level at which both TX_SD and rogue ONU are detected. When BEN = ‘0’ the TX_SD logic transfers the comparator output directly through to tx_sd. In addition, the Rogue ONU Fault Detect logic transfers the comparator output through to the laser safety system. The txsd_rogueonu_delay register specifies the delay (in cycles of the internal 64MHz clock) between the falling edge of BEN and testing for rogue ONU. The rogue_onu_fault condition is not generated during this time. When BEN = ‘1’ the TX_SD logic output goes high when the input from the comparator goes high. This state is latched. The tx_sd signal will then remain high until either the end of the burst, or until the comparator output remains low for a period of time exceeding the time defined by the txsd_deglitch_period register. This prevents tx_sd from toggling during a burst due to the pattern sensitivity of the MPD current. (During bias loop fast-start, tx_sd is held at ‘1’) Selection between TX_SD and TX_FAULT functionality is governed by the txsd_select register. The txsd_allow register holds the pin high until the configuration register load from EEPROM (or microcontroller) is complete. This avoids multiple transitions on the TX_SD pin during initialization. Maxim Integrated 15 Rogue ONU Behavior Impd Comparator threshold BEN TX_SD Figure 8. Rogue ONU Timing TX_SD Behavior Impd BEN Comparator output >50ns (A) (B) (C) (D) (E) TX_SD Figure 9. TX Signal Detect Timing During the gaps the TX_SD logic is transparent and the comparator output is routed directly through to the TX_SD pin. During the bursts: (A) The TX_SD pin is asserted high when the MPD current first exceeds the threshold. (B) The TX_SD pin will not toggle in response to short term fluctuations of the MPD current above and below the threshold (due to the pattern sensitivity of the MPD current). (C) There is a requirement that the TX_SD pin responds within 50ns of the assertion of BEN. The MPD current is settled and the TX_SD circuitry can respond well within 50ns of the start of a burst. However, the MAX24001 will assert TX_SD high whenever a signal is detected during a long burst—even if the signal does not appear until well after the initial 50ns. (D) If the laser stops outputting light during a burst, then there is a delay before TX_SD goes low. This is necessary in order to distinguish between the MPD current dipping below threshold due to a run of zeros, and the MPD current dropping below threshold due to a legitimate loss of signal. The delay is programmable using txsd_deglitch_period. (E) If the signal is restored during a burst then TX_SD is asserted high again. Maxim Integrated 16 Laser Biasing [Control Register Address Range A4h: A2h to A9h] The bias current is controlled by the tx_biasdac register in one of six operating modes: OPERATING MODE DESCRIPTION tx_biasmode Open loop, static tx_biasdac only changes when it is written by the host 000 Open loop, LUT tx_biasdac is constantly refreshed from values read from a temperature indexed lookup table (the bias LUT) 001 Closed loop, natural start An automatic power control (APC) loop constantly adjusts tx_biasdac in order to maintain a target laser output power level. tx_biasdac defaults to near-zero after power-up and then converges naturally on the target level over a duration of time dictated by the loop bandwidth. 100 Closed loop, LUT start The APC loop controls tx_biasdac, and tx_biasdac is preloaded from the bias LUT at power-up. 101 Closed loop, fast start The APC loop controls tx_biasdac, and a fast-start algorithm is invoked at power-up to rapidly converge the loop on the target power level. 110 Closed loop, LUT fast start The APC loop controls tx_biasdac. tx_biasdac is preloaded from the bias LUT at power up, and then a fast-start algorithm is invoked to rapidly converge the loop on the target power level. 111 Operational Overview The tx_biasmode register is a grouping of three individual controls registers: tx_biasmode: bias_lut_enable tx_biasmode: faststart_enable tx_biasmode: apc_enable Open-Loop Operation Clear the apc_enable register for open-loop operation. The laser bias current is controlled by the tx_biasdac register with a resolution of 92.5μA per LSB (nominal). This register may be set by the host, or alternatively set the bias_lut_enable bit to cause the tx_biasdac register to be automatically refreshed from the bias lookup table (LUT) every 10ms. The bias LUT is stored in external EEPROM at TWI slave address A6h, register address range 00h to 7Fh. It is indexed using the upper 7 bits of temperature_uncal. If the biasramp_en register is set then the value in tx_biasdac ramps progressively from the old value to the new by 1 LSB every cycle of the internal 64MHz clock. This prevents glitches from occurring in the DAC. If ramping is disabled then updates to tx_biasdac are effective immediately. Maxim Integrated 17 Closed-Loop Operation Set the apc_enable register for closed-loop operation. The automatic power control (APC) loop compares a value of laser output power produced by the power monitoring circuits with a target level set by tx_apc_target. This proportional error value is scaled using the apc_loop_gain and is then used to adjust the value of tx_biasdac (which has a number of internal precision extension bits). The apc_loop_gain register thus controls the bandwidth of the APC loop. Since the bandwidth of the loop is not very high, it is desirable to set the tx_biasdac register to a point as close as possible to the target laser power level before the APC loop takes over. This is achieved by preloading the tx_biasdac register with a value from the bias LUT and/or running a search algorithm (referred to as fast-start). These actions are both triggered by the bias_lut_enable and faststart_enable bits. When these bits are set, then a table lookup or fast-start will occur at the next available opportunity. Once the lookup or fast-start has occurred then these bits are cleared. The host may therefore re-trigger fast/lut start by resetting bias_lut_enable and faststart_enable at any time. The bits are also set automatically as follows: On power-up: tx_biasmode is configured from EEPROM During SLEEP: The value in faststart_after_sleep is transferred to faststart_enable The value in bias_lut_after_sleep is transferred to bias_lut_enable During TX_DISABLE: The value in faststart_after_txdisable is transferred to faststart_enable The value in bias_lut_after_txdisable is transferred to bias_lut_enable initialising normal operation normal operation sleep Faststart algorithm is executed Bias mode register re-loaded Faststart algorithm is executed Load tx_biasdac from bias LUT Bias mode register re-loaded Faststart algorithm is executed LASER ENABLED Load tx_biasdac from bias LUT Initialise from EEPROM Power-on reset Thus, the required loop behavior when the laser is enabled can be independently configured for reset, sleep mode and tx disable. This is further illustrated in the figure below: disabled normal operation apc_enable 0 1 1 1 1 1 1 1 1 faststart_enable 0 1 1 0 1 1 0 1 0 bias_lut_enable 0 1 0 0 1 0 0 0 0 faststart_after_sleep 1 faststart_after_tx_disable 1 bias_lut_after_sleep bias_lut_after_tx_disable 1 0 Figure 10. Behavior of the tx_biasmode Register in Closed-Loop Mode Maxim Integrated 18 Fast-Start Algorithm Bias current Step size [Control Register Address Range A4h: AAh to Ach] A C MPD current (Laser output power) B D Target MPD current Figure 11. Fast-Start Algorithm Timing During fast-start, the MAX24001 is temporarily reconfigured. The modulation driver sinks a constant current of IMOD/2 on TX_OUT to represent the contribution made by the signal current to the average power. The power monitoring circuit is reconfigured to supply a direct comparison between the received MPD current and the target MPD current. The process of making a change to bias current and then a subsequent comparison of MPD current and target current is referred to as iteration. An iteration has a fixed duration (nominally 62ns). Initially, the bias current is stepped up on every iteration until the MPD current exceeds the threshold. The initial bias current step size A is ideally ½ the modulation current, the rationale being that this is the largest step which can be taken whilst ensuring that the P1 power level is not exceeded. More generally, the initial step size is defined as A = (tx_fstart_initial/256) x IMOD. When the target level is exceeded the step size then decays (C). Halving the step size every iteration amounts to a binary search. In practice, incomplete settling of the loop can result in a small overshoot of the target current level. It is therefore recommended that each step is slightly more than 0.5x the previous step. This is configurable using the fstart_decay register. The fstart_decay register determines the multiplication factor applied to the step size on each subsequent iteration of the fast-start algorithm. Maxim Integrated 19 STEP DECAY MULTIPLIER 32/64 = 0.5 33/64 = 0.516 34/64 = 0.531 35/64 = 0.547 36/64 = 0.563 37/64 = 0.5785 .. 46/64 = 0.719 47/64 = 0.734 fstart_decay 100000 100001 100010 100011 100100 100101 .. 101110 101111 The direction of each current step depends on whether the measured MPD current is above or below the target level. The number of iterations B is controlled by the fstart_duration register. The maximum number of iterations which can be guaranteed to complete within 3 x 400ns bursts is 15. At the end of the fast-start algorithm, the laser output stage switches from sinking DC IMON/2 on TX_OUT to full amplitude signal. This may result in a brief current spike. A facility is provided to optionally shut down the modulation current through the laser during this transition period (D). Use the fstart_recovery_en and fstart_recovery_time registers to shut down the modulation current for 0, 1, or 2 iterations. APC Loop Bandwidth The apc_loop_gain register adjusts the gain of the APC control loop. Loop bandwidth (Hz) is calculated as a function of apc_loop_gain: Bandwidth (Hz) = 2apc _ loop _ gain - 15 ´ k elec ´ k mpd ´ (biasdac _ lsb ´ 4) ´ fCLOCK 2 ´ p ´ 16 ´ mondac _ lsb = 2apc _ loop _gain - 15 ´ k elec ´ k mpd ´ 3.02 ´ 108 Where: mondac_lsb biasdac_lsb fCLOCK kmpd kelec Maxim Integrated = 0.78μA = 92.5μA = 64MHz (typical) = 0.0625 when mpd_range = 10 0.25 when mpd_range = 01 1 when mpd_range = 00 = (MPD current)/(laser current) apc_loop_gain GAIN 0000 0001 0010 : 1100 1101 1110 1111 2 -14 2 -13 2 : -3 2 -2 2 -1 2 1 -15 20 Power Monitoring A power monitoring circuit generates a digital measure of MPD current (laser power) based on time-averaged samples taken during bursts when the laser is enabled. It has three settings in order to accommodate the wide range of monitor photodiode currents. The range setting (mpd_range) is chosen at the time that the module is calibrated, and does not change during normal operation of the APC loop. The unfiltered, 8-bit digital measure of MPD current is used internally by the APC loop. mpd_range 00 01 10 PD MIRROR GAIN 1 1/4 1/16 IMON OPERATING RANGE (µA) 40 to 200 100 to 800 400 to 2000 Tracking error in the TOSA means that the MPD current may vary over temperature in a nonlinear way for a given laser optical power. If the temperature-indexed tracking error lookup table (LUT) is enabled then the digital measure of MPD current is multiplied by the values read from the LUT. Each entry in the LUT represents a number in the range 0.5 (00h) to 1.5 (FFh), and 80h represents unity gain. Set the trackinglut_en bit to enable this feature. A correction factor is retrieved from the tracking error LUT every 10ms. This LUT is stored in external EEPROM at TWI slave address A8h, register address range 80h to FFh. It is indexed using the upper 7 bits of temperature_uncal. The digital measure of MPD current (including tracking error compensation) is used by the APC loop to control bias current. Power Reporting For power reporting purposes, the power monitor output is low-pass filtered to suppress the pattern sensitivity of the MPD current. This filter bandwidth is programmable using the mon_bandwidth register. Bandwidth = 64/(2π x (15-n) ) where n is the 4-bit integer mon_bandwidth value up to a maximum of 14. The filtered measure of laser 2 power can be read from the txpower_uncal register. mon_bandwidth BANDWIDTH at fCLOCK = 64MHz 0000 0001 .. 1000 .. 1110 1111 311Hz 622Hz .. 80kHz .. 5.1MHz No filtering The mpd_range should be set at a level which accommodates the expected range of MPD current. The MAX24001 is not designed to automatically range switch during normal APC loop operation. However, if the APC loop fails and the power monitor saturates then the mpd_range will temporarily switch so that power reporting can cover the full 0 to 2mA range of photodiode current. The range then recovers back to the original setting if the power monitor value drops back below 64. Power Leveling The power_levelling register implements GPON power levelling. Set to 00, 01, or 1x to reduce the modulation amplitude set by tx_moddac by x1, x0.5 and x0.25, respectively. This register will also reduce the power level by having the same effect on the output of the tx_apc_target register. Power levelling does not affect the bias current in open-loop mode. Maxim Integrated 21 Laser Safety [Control Register Address Range A4h: AFh to B3h] The laser safety system generates two signals, tx_fault_int and tx_shutdown_int. Tx_fault_int is pure status. It reports via both register and TX_FAULT pin whether one or more enabled fault conditions have occurred. The TX_FAULT pin can be configured to appear at pin 21 or 39 using pin_config0. Tx_shutdown_int is a control signal. It disables the bias and modulation currents to the laser when one or more enabled fault conditions have occurred. Fault Conditions The fault conditions which affect tx_fault_int and tx_shutdown_int are: Bias Fault APC Fault VREF Fault VDD Fault Tx Disable Fault Soft Tx Fault RogueOnu Fault Alarm Fault This occurs when the BIAS pin is shorted to ground. This occurs when the MPD pin is shorted to ground. This occurs when the RREF pin is shorted to ground. This occurs when brownouts are detected on TX or TXO. Is given by: (TX_DISABLE XOR tx_disable_invert) OR soft_tx_disable where TX_DISABLE is the pin value and soft_tx_disable is in SFF-8472 status_control. This occurs when the soft_tx_fault bit in software_faults register is set. If the laser is on during a gap between bursts then this fault condition is generated. This occurs when one or more of the SFF-8472 DDM alarm flags are set to ‘1’. The flags which contribute to Alarm Fault are programmable via ls_alarmflag_en. When the laser is in shutdown then the bias fault condition is ignored by the laser safety system. When tx_shutdown is deasserted there is a 250μs delay before the bias fault condition is used. This allows the circuit which detect a ground short on the bias pin time to settle before the bias fault condition is seen by the laser safety system. Architecture Fault conditions Cell alarm_fault Cell rogue_onu_fault Cell soft_tx_fault tx_disable_fault vdd_fault vref_fault apc_fault bias_fault Laser safety system (Tx fault) Safety cells Cell Cell tx_fault_int Cell Cell tx_fault_pin Cell 0 tx_disable_fault laser_inhibit ls_txfault_latchen ls_txfault_faulten reset S Q R 1 Latch enable Fault enable laser_inhibit Laser safety system (Tx shutdown) ls_shutdown_latchen tx_shutdown_int ls_shutdown_faulten shutdown Figure 12. Laser Safety System Maxim Integrated 22 The laser safety system (Tx fault) generates the tx_fault_int signal. The status of this signal can be accessed in the SFF-8472 status_control register. The signal is also multiplexed onto the TX_FAULT/TX_SD pin. Every safety cell has its own pair of latch enable and fault enable control register bits. The fault condition can only propagate through to the output when _faulten = ‘1’. When _latchen = ‘1’ a latched version of the fault condition is used. The latch is held in reset when latching is disabled or when the tx_disable_fault signal is asserted. Note that tx_disable_fault is also a fault condition signal. When it is asserted, the laser_inhibit signal holds all latches in reset and forces the tx_fault_int signal to ‘1’. Note that after the power-on reset, laser_inhibit is enabled. During initialization pin_config is the last configuration register to be loaded from EEPROM and therefore has the effect of clearing laser_inhibit and thus enabling the laser. ls_fault_status reports the status of the fault conditions at the inputs to the safety cells. The laser safety system is fully replicated for controlling laser shutdown. The system uses the ls_shutdown_faulten and ls_shutdown_latchen registers and produces the tx_shutdown_int signal for disabling the modulation and bias currents. The internal architecture is otherwise the same as the system for Tx Fault. The shutdown register can be found in hardware_status. The module Tx supply (VCC_TX) can be used in some applications to shut down the laser. This is supported in MAX24001 by detecting the removal of VCC_TX on the VDD_TXO pin. VCC_TX is connected to VDD_TXO as shown in Figure 13. A shutdown is then asserted if the voltage falls below 2.7V. If the connection between VCC_TX and VDD_TXO is not used, VDD_TXO must be connected to another supply. VCC_TX VCC_TX/VDD_TXO Connection VCC_RX VDD_TXO VDD_DIG VDD_RX VDD_RXO VDD_TX 2.7 V VDD DETECT LASER SAFETY TRANSCEIVER IC Figure 13. VDD_TXO Configured to Assert Laser Shutdown Temperature Sensor [Control Register Address Range A4h: B6h, B9h, C1h] The MAX24001 includes an integrated temperature sensor that reports the module temperature at the sensor transistor. The temp_ext_sensor register selects between an internal transistor or an external PNP transistor connected to the TSENSE and TSENSE_RET pins. If an external transistor is used then the PCB tracks connecting an external PNP transistor to the chip each have resistance >8 operation after multiplication). All offset values (including Rx power) are stored as 16-bit fixed point (signed two’s complement) as per SFF-8472 external calibration constants. In all cases, the upper byte of the 16-bit word is stored at the lower address. Rx power has an additional pair of constants to support a rough piecewise linear approximation of the nonlinear characteristic of received optical power vs. RSSI current. This occurs when a series resistor is used between the APD and the APD bias voltage generation circuit. It provides a form of compression, protecting the APD by reducing avalanche gain if current gets too high. Temperature temp_offset Calibrated SFF-8472 DDM temp_slope A2: 60h – 61h x temperature_uncal 8 >>8 + 16 Temperature A/W lookup Figure 16. Calculating the Temperature DDM Supply Voltage vcc_offset Calibrated SFF-8472 DDM vcc_slope A2: 62h – 63h supply_uncal 8 x >>8 + 16 Vcc A/W lookup Figure 17. Calculating the Supply Voltage DDM Maxim Integrated 26 Tx Bias Current bias_offset Calibrated SFF-8472 DDM bias_slope A2: 64h – 65h x bias_uncal 8 + >>8 Tx Bias 16 A/W lookup Figure 18. Calculating the Bias Current DDM Tx Power txpower_offset txpower_slope Calibrated SFF-8472 DDM mpd_range A2: 66h – 67h txpower_reranged txpower_uncal x re-range 12 8 + >>8 16 Tx Power A/W lookup Figure 19. Calculating the Tx Power DDM The power monitor generates an 8-bit measure of MPD current after a gain of 1, 1/4, or 1/16 has been applied. Reranging increases the Tx Power value when gains < 1 have been applied to the MPD current. txpower_reranged = txpower_uncal 8 + 16 Rx Power A/W lookup Figure 20. Calculating the Rx Power DDM The following formulae are used to convert the 3-slope rxpower_uncal value into a linear pseudo 12-bit (0 to 2448) value: 0 < rxpower_uncal ≤ 32 32 ≤ rxpower_uncal ≤ 128 128 ≤ rxpower_uncal ≤ 255 Maxim Integrated linearized_rx_power = rxpower_uncal linearized_rx_power = ((rxpower_uncal – 32) x 4) + 32 linearized_rx_power = ((rxpower_uncal – 128) x16) + 416 27 The selected pair of slope and offset values depend on the value of linearized_rx_power. If linearized_rx_power is greater than rxpower_threshold, then use the slope and offset pair from the address range 14h to 17h. Otherwise use the slope and offset pair from address range 10h to 13h. This coarsely accommodates the nonlinearity of the curve of received optical power vs. RSSI current. Alarm high Alarm low Warning high Warning low Alarm and Warning Flags 1 1 1 0 0 0 0 0 0 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 0 0 1 1 1 1 1 1 FFh Table indexed using uncalibrated data 00h High alarm threshold High warning threshold Low warning threshold Low alarm threshold Figure 21. Using 8-Bit Calibrated Data to Look Up Alarm and Warning Flags 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 Warning low Alarm low Warning high Warning low Alarm high Alarm low Warning high Warning low Alarm high Alarm low Warning high Warning low Alarm high Alarm low Warning high Warning low 3 2 1 0 d 7 Alarm high Unused Warning high RxPower Alarm low TxPower Alarm high Bias se Supply A/W LUT3 nu Temp A/W LUT2 U A/W LUT1 Figure 22. Alarm and Warning LUT Mapping The uncalibrated 8-bit diagnostic data values are used to index the alarm and warning LUTs. Construct a LUT by identifying the required threshold levels in absolute units (V, C, mA, µW) and then reverse the calculations shown by the figures in the previous section to yield corresponding uncalibrated threshold levels. For Tx and Rx power, these should incorporate the range and 3-slope encoding, respectively. The ls_alarmflag_en register controls which of the DDM alarm flags contribute to the laser safety alarm_fault fault condition. Maxim Integrated 28 Power-Up and Sleep Mode [Control Register Address Range A4h:8Ch, B8h] The MAX24001 can be put into a low-power mode of operation when the SLEEP pin is asserted. This is achieved by combining the sleep function with the chip-power sequencing, SLEEP can be configured to independently affect the Rx and Tx signal paths. Rx Signal path: The response to the SLEEP pin is controlled by the rx_respond_to_sleeppin register. Tx Signal path: The response to the SLEEP pin is controlled by the tx_respond_to_sleeppin register. ON SLEEP pin not asserted SLEEP pin asserted AND responding to sleep pin OR (SLEEP pin asserted AND not responding to sleep pin) REDUCED POWER Figure 23. Conditions for Moving In and Out of Sleep Mode The device will only move between these states when power sequencing is enabled (tx_powerup_en and rx_powerup_en are set). The host can alternatively put the MAX24001 to sleep using the tx_force_sleep and rx_force_sleep registers. Maxim Integrated 29 Initialization and Control Overview The MAX24001 is normally used in conjunction with a 2k byte EEPROM. A4h Reserved SFF8079 User EEPROM MAX 24001 Config/ Control SFP MSA Serial ID Diagnost. (external Cal) MAX 24001 (Internal Cal) Memory Memory MAX 24001 registers FFh EEPROM 0 MAX24001 Memory areas A6h A8h AAh ACh AEh A/W LUT1 A/W LUT2 A/W LUT3 Upper A2h Modulation Tracking LUT LUT Bias LUT APD LUT Lower A0h Figure 24. Address Map Normal Operation During initialization, data is transferred from EEPROM areas with TWI slave addresses A0h and A2h into shadow areas of memory on the MAX24001. Device configuration data is transferred from area A4h into MAX24001 registers. During normal operation, the MAX24001 has exclusive access to the lookup tables held in EEPROM using the TWI master interface. The MAX24001 TWI slave interface only decodes slave addresses A0h and A2h, and when the host accesses these areas it is accessing the shadowed memory on the MAX24001. The diagnostic data in the memory is regularly refreshed. Using a Microcontroller If the initialization fails, then the MAX24001 defaults to a state whereby the Tx and Rx paths are not enabled, the main loop is off, and all memory areas are accessible. A microcontroller may then upload data to registers and control the operation of the MAX24001. Module Setup To access EEPROM (cf initialisation_status and system_control registers) ¨ Clear mainloop_en. This stops the main loop. ¨ Wait until eeprom_dma_idle is set. Accesses to EEPROM have then ceased. ¨ Set external_access to direct accesses via the TWI slave interface to EEPROM. All regions of the EEPROM may then be accessed as long as the chip is in security level 2. Access Control [Control register address range A2h: 7Ch to 7Fh, and A4h: 82h to 8Bh] Maxim Integrated 30 Three levels of security are defined. The security level determines which areas of EEPROM and register space may be accessed via the two-wire interface. The security level is selected by the password_entry register and can be read from the security_level register in system_status. Level2 – (password_entry value matches password2). The host has full read and write access to all address spaces. (password2 has priority over password1). Level1 – (password_entry value matches password1). The host has read and write access to A0h and A2h only, as defined by the upper nibbles of the password_configA0 and password_configA2 registers. Level0 – (password_entry value matches neither password1 nor password2). The host has read and write access to A0h and A2h only, as defined by the lower nibbles of the password_configA0 and password_configA2 registers. Password1 and password2 can only be written in level2. The security level will not change when writing a new value to password2. Typically access in level 0 is more restrictive than access in level1. Read and write access to A2h:78h to 7Fh is always permitted. If access is denied then the transaction is discarded in the case of a write, and returns FFh in the case of a read. During burst-mode accesses, access permission and destination are tested on a byte-by-byte basis. Maxim Integrated 31 Initialization Sequence [Control register addresses A4h: 80h, 81h, 8Ch, E0h] PoR Wait for 10ms. Reset timer. Transfer data from EEPROM to registers A4: 80h – 8Fh Conditionally power up the Tx and Rx paths. n OK? During this time the TWI slave interface is disabled. If the transfer fails then the eeprom_unresponsive register bit is set If the content of the data_integrity registers is invalid then the eeprom_data_invalid register bit is set Wait until: tx_powerup_en = tx_powerup_done. And rx_powerup_en = rx_powerup_done OK if eeprom_unresponsive = ‘0’ and eeprom_data_invalid = ‘0’ y Transfer remaining data from EEPROM to registers and on-chip memory: Register data: A4: 90h – BFh Cal constants: A4: 00h – 17h Serial ID: A0: 00h – FFh Digital Diag: A2: 00h - 77h A2: 80h - FFh Main loop Figure 25. Initialization Sequence The data integrity bytes are the first two bytes to be read from EEPROM (addresses A4: 80h to 81h). If data_integrity0 = C3h and data_integrity1 = 5Ah then it is inferred that the EEPROM is correctly programmed and initialization continues. If the read access fails (no EEPROM) then eeprom_unresponsive is set. If the read access succeeds but the data integrity values are incorrect then eeprom_data_invalid is set. In both cases the transfer from EEPROM is aborted to prevent MAX24001 defaults from being overwritten with random data. The Tx and Rx paths will not power up and the MAX24001 will remain in the wait state at the start of the main loop. The data integrity values only exist in EEPROM. They have no corresponding registers. Maxim Integrated 32 Main Operating Loop [Control register address A4h: B7h] Main loop n mainloop_en = 1? y Modulation look-up Conditional – Only do this if modlut_en = 1 Bias look-up Conditional – Only do this if biaslut_en = 1 APD look-up Conditional – Only do this if apdlut_en = 1 Tracking error lookup Reset timer Conditional – Only do this if trackinglut_en = 1 Alarm/Warn look-up Conditional – Only do this if sff_en = 1 Trigger SFF-8472 calibration Conditional – Only do this if sff_en = 1 On first pass, clear laser_inhibit All lookups performed before laser is enabled Wait for 10ms timer to expire. Figure 26. Main Operating Loop The modulation, bias, APD, and tracking error LUTs are all 128 bytes and indexed by the upper 7 bits of the uncalibrated temperature sensor output (temperature_uncal). Typically, LUT entry 14h corresponds with a temperature of -40°C. LUT resolution is then 1.6°C between consecutive table entries. These values are approximate and may vary slightly from batch to batch. Maxim Integrated 33 Two-Wire Interface (TWI) Protocol The SDA_SLAVE and SCL_SLAVE pins are referred to as the slave two-wire interface (slave TWI). The slave TWI provides external access to both registers within the MAX24001 and to any device connected to the SCL_MASTER and SDA_MASTER pins (the master TWI). Typically, an EEPROM is connected to the master TWI. Framing and Data Transfer The two-wire interface comprises a clock line (SCL) and a data line (SDA). An individual transaction is framed by a START condition and a STOP condition. A START condition occurs when a bus master pulls SDA low while SCL is high. A STOP condition occurs when the bus master allows SDA to transition low-to-high when SCL is high. Within the frame the master has exclusive control of the bus. The MAX24001 supports Repeated START conditions whereby the master may simultaneously end one frame and start another without releasing the bus by replacing the STOP condition with a START condition. Within a frame the state of SDA only changes when SCL is low. A data bit is transferred on a low-to-high transition of SCL. Data is arranged in packets of 9 bits. The first 8 bits represent data to be transferred (most significant bit first). The last bit is an acknowledge bit. The recipient of the data holds SDA low during the ninth clock cycle of a data packet to acknowledge (ACK) the byte. Leaving SDA to be pulled high on the ninth bit signals a notacknowledged (NACK) condition. The interpretation of the acknowledge bit by the sender depends on the type of transaction and the nature of the byte being received. SDA is bidirectional so that the master may send data bytes during write transactions and the slave may send data bytes during reads. Device Addressing The first byte to be sent after a START condition is a slave address byte. The first seven bits of the byte contain the target slave address (MSB first). The eighth bit indicates the transaction type – ‘0’ = write, ‘1’ = read. Each slave interface on the bus is assigned a 7-bit slave address. If no slave matches the address broadcast by the master then SDA will be left to be pulled high during the acknowledge bit and the master receives a NACK. The master must then assert a STOP condition. If a slave identifies the address then it acknowledges it by pulling SDA low. The master then proceeds with the transaction identified by the type bit. The two-wire interface of the MAX24001 decodes slave addresses A0h to AFh. START SDA R/W ACK ADDRESS msb 7 6 5 4 3 2 1 STOP lsb 0 SCL Figure 27. Address Decoding Example Write Transaction Figure 28 shows an example of a write transaction. The address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. After the first acknowledge the master sends a single data byte. All signalling is controlled by the master except for the SDA line during the acknowledge bits. During the acknowledge cycle the direction of the SDA line is reversed and the slave pulls SDA low to return a ‘0’ (ACK) to the master. Maxim Integrated 34 START 7 SDA ACK ACK 1 msb 7 W 6 5 4 3 2 1 STOP 0 SCL SDA direction to slave from slave Figure 25. Write Transaction The MAX24001 interprets the first data byte as a register address. This is used to set an internal memory pointer. Subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer. The pointer is autoincremented after each byte. There is no limit to the number of bytes which may be written in a single burst to the internal registers of the MAX24001. Read Transaction START SDA ACK ACK 7 1 R 7 0 NACK 7 STOP 0 SCL SDA direction to slave from slave Figure 26. Read Transaction Figure 29 shows an example of a 2-byte read transaction. The slave address byte is successfully acknowledged by the slave, and the type bit is set high to signify a read. After the ACK the slave returns a byte from the location identified by the internal memory pointer. This pointer is then auto-incremented. The slave then releases SDA so that the master can ACK the byte. If the slave receives an ACK then it will send another byte. The master identifies the last byte by sending a NACK to the slave. The master then issues a STOP to terminate the transaction. Thus, to implement a random access read transaction, a write must first be issued by the master containing a slave address byte and a single data byte (the register address) as shown in Figure 28. This sets up the memory pointer. A read is then sent to retrieve data from this address (see Figure 29). Maxim Integrated 35 Register Descriptions For registers containing a single 8-bit field, the MSB of the field is stored in bit 7 of the register byte. Note that ‘reserved’ register bits are specified as read only. These registers should not be changed from their power-on reset (POR) default settings. Register types are: R R/W E Bit is read only via the slave TWI. Writing to this bit will have no effect. The value may be changed by the MAX24001 to communicate operating status to the host. Bit is readable and writable via the slave TWI. The value will not be changed by the device itself except under a device reset. Event bit. This bit is set to ‘1’ by the MAX24001 when a specified event occurs. It is only cleared to ‘0’ when the host writes ‘1’ to it via the slave TWI. Writing a zero to this register has no effect. This bit is also readable. Slave Address: A2h 6Eh status_control BIT FIELD NAME Status and control information (cf. sff-8472 specification) TYPE POR DESCRIPTION 7 tx_disable_state R/W 0 State of the TX_DISABLE pin 6 soft_tx_disable R/W 0 1: Disable the laser 5 — — — — 4 p_down_status R — State of the SLEEP pin 3 P_down_control R/W 0 1: Assert SLEEP 2 tx_fault_state R — State of the TX_FAULT pin 1 rx_los_state R — State of the LOS/SD pin 0 data_ready_bar R 1 Changes to ‘0’ when the transceiver is powered up and data is ready 7Ah system_status BIT FIELD NAME Additional vendor specific status made available to the user irrespective of security level TYPE POR DESCRIPTION 7 — — — — 6 rogue_onu E 0 1: Rogue_onu condition is detected 5 excessive_bias R 0 1: Bias DAC exceeds tx_bias_threshold 4 eeprom_dma_idle R 0 1: EEPROM is idle and may be accessed 3 eeprom_data_invalid R 0 1: Data integrity check failed during initialization 2 eeprom_unresponsive R 0 1: EEPROM failed to ACK the slave address during initialization security_level R 10 00h = level0, 01h = level1, 10h = level2 1–0 Maxim Integrated 36 7Bh Additional vendor specific control bits made available to the user irrespective of security level system_control BIT FIELD NAME TYPE POR DESCRIPTION — — Undefined 7–6 — 5-4 power_levelling R/W 00 GPON power levelling: 00: x1, 01: x0.5, 1x: x0.25 3 soft_rate_select R/W 0 0: ratesel0 control rx filter, 1: ratesel1 controls rx filter 2 tx_force_sleep R/W 0 1: Force Tx system into low-power SLEEP mode (if respond_to_sleep pin set) 1 rx_force_sleep R/W 0 1: Force Rx system into low-power SLEEP mode 0 external_access R/W 0 Host access routing: 1: EEPROM, 0: internal registers/memory 7Ch password_entry0 R/W 00h 7Dh password_entry1 R/W 00h 7Eh password_entry2 R/W 00h 7Fh password_entry3 R/W 00h Write to this register to select the security level. Level 2 if password_entry = password2 else Level 1 if password_entry = password1 else Level 0 Slave Address: A4h 82h password1_0 R/W 00h 83h password1_1 R/W 00h 84h password1_2 R/W 00h 85h password1_3 R/W 00h 86h password2_0 R/W 00h 87h password2_1 R/W 00h 88h password2_2 R/W 00h 89h password2_3 R/W 00h 8Ah password_configA0 Holds the security level 1 password. Holds the security level 2 password BIT FIELD NAME Enables the access to the upper and lower halves of the A0h address space to be configured for security levels 0 and 1 TYPE POR 7 level1_write_upper R/W 1 1: Write access to upper half of A0h permitted in security level 1 6 level1_read_upper R/W 1 1: Read access to upper half of A0h permitted in security level 1 5 level1_write_lower R/W 1 1: Write access to lower half of A0h permitted in security level 1 4 level1_read_lower R/W 1 1: Read access to lower half of A0h permitted in security level 1 3 level0_write_upper R/W 0 1: Write access to upper half of A0h permitted in security level 0 2 level0_read_upper R/W 0 1: Read access to upper half of A0h permitted in security level 0 1 level0_write_lower R/W 0 1: Write access to lower half of A0h permitted in security level 0 0 level0_read_lower R/W 1 1: Read access to lower half of A0h permitted in security level 0 Maxim Integrated DESCRIPTION 37 8Bh Enables the access to the upper and lower halves of the A2h address space to be configured for security levels 0 and 1 password_configA2 BIT FIELD NAME TYPE POR DESCRIPTION 7 level1_write_upper R/W 1 1: Write access to upper half of A2h permitted in security level 1 6 level1_read_upper R/W 1 1: Read access to upper half of A2h permitted in security level 1 5 level1_write_lower R/W 1 1: Write access to lower half of A2h permitted in security level 1 4 level1_read_lower R/W 1 1: Read access to lower half of A2h permitted in security level 1 3 level0_write_upper R/W 0 1: Write access to upper half of A2h permitted in security level 0 2 level0_read_upper R/W 0 1: Read access to upper half of A2h permitted in security level 0 1 level0_write_lower R/W 0 1: Write access to lower half of A2h permitted in security level 0 0 level0_read_lower R/W 1 1: Read access to lower half of A2h permitted in security level 0 8Ch initialization_config BIT FIELD NAME Early stage chip configuration at the start of the initialisation process TYPE POR DESCRIPTION 7 — — — Undefined 6 — R/W 0 Reserved 5 tx_powerup_en R/W 0 1: Enable automatic power-up sequencing for the Tx system 4 rx_powerup_en R/W 0 1: Enable automatic power-up sequencing for the Rx system 3–0 — R/W 0111 90h rx_input BIT FIELD NAME Reserved Configures the input buffer of the receive path and sets the receiver bandwidth TYPE POR DESCRIPTION 7–4 rx_input_peak R/W 0000 3–2 rx_ratesel1 R/W 11 Sets the receiver bandwidth: 00: 1.25Gbps 01: 2.488Gbps 1–0 rx_ratesel0 R/W 00 Register is selected by soft_rate_select. 92h rx_output BIT FIELD NAME 0000: no peaking, increasing to 1111 for maximum peaking Configures the output stage of the receive path TYPE POR DESCRIPTION — — Undefined 7 — 6 los_squelch R/W 1 1: Power down RX_OUT when LOS = 1 5 Squelch R/W 0 1: Power down RX_OUT (but only if los_squelch = ‘0’) 4 3–0 rx_invert R/W 0 — R/W 0000 Maxim Integrated 1: Invert signal on RX_OUT Reserved 38 93h rx_driver Controls the output amplitude and pre emphasis on RX_OUT BIT FIELD NAME TYPE POR 7–6 — — — DESCRIPTION Undefined Sets pre-emphasis ratio: 5–4 rx_preemphasis R/W 00 00: 01: 10: 11: 0% 2% 6% 10% Sets output voltage swing: 3–0 rx_output_swing R/W 1010 0000: 200mVP-P 1111: 880mVP-P Step size is 45mV 94h Configuration of the APD system and specifically the APD_CTRL and DAC outputs rx_apd_control BIT TYPE POR pwm_frequency R/W 00 0: 250kHz, 1: 500kHz, 2: 1MHz, 3: 2MHz 5 pwm_invert R/W 0 1: invert, 0: normal 4 high_v R/W 0 APD_CTRL output, 0: open, 1: 3.3V driver 3 — R/W 1 Reserved 2 target_lut_enable R/W 0 1: Load the rx_apd_target register periodically from the APD LUT 1 pwm_lut_enable R/W 0 1: Load the rx_apdpwm register periodically from the APD LUT 0 dac_lut_enable R/W 0 1: Load the rx_apddac register periodically from the APD LUT 7–6 95h BIT FIELD NAME rx_apd_pi FIELD NAME DESCRIPTION Gain values for APD proportional-integral controller TYPE POR DESCRIPTION Duty-cycle limit (maximum): 7–6 max_duty R/W 00 0: 1: 2: 3: 207/256 223/256 239/256 255/256 Integral gain of PI controller (rx_apdpwm LSBs/LSB of error value). 5–3 k_integral R/W 000 0: 1: 2: 3: 0 2-8 2-7 2-6 4: 5: 6: 7: 2-5 2-4 2-3 2-2 The error value is the difference between the sampled APD voltage and the rx_apd_target value. Eg. If k_integral = 6 and error value = +2 then the rx_apdpwm register will be incremented by 2 x 2-3 = 0.25. (Note that the rx_apdpwm register is the integer part of a fixed point register with 8 additional bits of precision. ) Proportional gain of PI controller (rx_apdpwm LSBs / LSB of error value): 2–0 k_proportional 96h rx_apd_v_threshold Maxim Integrated R/W 000 TYPE POR R/W FFh 0: 1: 2: 3: 0 20 21 22 4: 5: 6: 7: 23 24 25 26 While the APD voltage exceeds this threshold, APD_CTRL is three-stated. Note that a threshold of FFh amounts to turning off this feature. 39 97h 98h 99h 9Ah 9Bh TYPE POR R/W FFh TYPE POR R/W 00h TYPE POR R/W 00h TYPE POR R/W 00h rx_apd_i_threshold rx_apddac While the APD current exceeds this threshold, APD_CTRL is three-stated. Note that a threshold of FFh amounts to turning off this feature. Sets the APD DAC output current from 0 to 500μA. rx_apdpwm Sets the PWM duty cycle in the range 0/256 to 255/256 rx_apd_target Sets the target voltage of the APD controller. Sets the los debounce period and LOS polarity. This register also contains bits used to control current on RSSI pin los_rssi_config BIT FIELD NAME TYPE POR 7 — — — Undefined 000 000 = 0μs 001 = 16μs 010 = 32μs 011 = 48μs 6–4 los_debounce R/W DESCRIPTION 100 = 64μs 101 = 80μs 110 = 96μs 111 = 112μs Sets gain applied to current flowing through RSSI pin. 00: x1 : RSSI current range 0 to 1275μA 3–2 rx_rssi_scale R/W 11 01: x1.5: RSSI current range 0 to 850μA 10: x1.5: RSSI current range 0 to 850μA 11: x2: RSSI current range 0 to 638μA 1 rx_rssi_sink R/W 1 1: Current flows into RSSI pin, 0: Current flows out of RSSI pin 0 — — — — TYPE POR R/W 00h TYPE POR R/W FFh 9Ch 9Dh los_assert Sets threshold at which LOS is asserted los_deassert Maxim Integrated Sets threshold at which LOS is deasserted 40 9Eh Configures the input circuitry of the transmit path. Pulse width of the transmitted signal is adjusted by moving the crossing point of the eye up or down. tx_input BIT FIELD NAME TYPE POR 7 burst_invert R/W 0 1: Invert differential signal on BEN 6 tx_invert R/W 0 1: Invert differential signal on TX_IN 5 — — — Undefined 4 tx_pwadjust_hires R/W 0 1: Reduce step size of pulse width adjust by half 3 tx_pwadjust_dir R/W 0 0: Move crossing point of eye up, 1: Move crossing point down 2–0 tx_pwadjust_size R/W 000 A0h tx_output BIT 000: No adjustment, 111: Maximum adjustment. At maximum adjustment the zero-crossing point moved by 40% of 0-pk eye opening. This register is used for managing the quality of the output eye TYPE POR modramp_en R/W 1 6–4 tx_snubber R/W 000 Adjust this to improve rise time and pulse width distortion 3–0 — R/W 0000 Reserved TYPE POR A1h tx_moddac R/W 00h 7 A2h FIELD NAME DESCRIPTION FIELD NAME 1: DAC ramps from old value to new, 0: immediate step change Sets the CML output current for the laser driver (modulation current) The mpd_gain register applies gain to the MPD current. It does not change during normal operation and therefore the range must be selected to accommodate all expected values of MPD current. tx_bias BIT DESCRIPTION TYPE POR DESCRIPTION 7 — R/W 0 Reserved 6 — — — Undefined mpd_range R/W 10 10: 400μA to 2000μA 01: 100μA to 800μA 00: 40μA to 200μA biasramp_en R/W 1 1: Bias DAC ramps from old to new, 0: Immediate step change — — Undefined TYPE POR 5–4 3 2–0 — A3h tx_biasmode BIT FIELD NAME DESCRIPTION 7 faststart_after_sleep R/W 0 1: Trigger the fast-start algorithm when emerging from sleep mode 6 bias_lut_after_sleep R/W 0 1: Do single bias LUT lookup when emerging from sleep mode 5 faststart_after_txdisable R/W 0 1: Trigger the fast-start algorithm when tx_disable deasserted 4 bias_lut_after_txdisable R/W 0 1: Do single bias LUT lookup when tx_disable deasserted 3 — 2 apc_enable R/W 0 1: Closed-loop operation. 0 => open-loop operation 1 faststart_enable R/W 0 1: Trigger the fast-start algorithm after power-on reset 0 bias_lut_enable R/W 0 1: Periodic lookups (apc_enable = 0). — — — 1: Do single bias LUT lookup after power-on reset (apc_enable = 1) 0: No lookups from bias LUT Maxim Integrated 41 A4h BIT 7–4 The APC delay register controls the delay between the deassertion of laser shutdown and the activation of the APC loop counter. The APC loop gain sets the gain (and thus the bandwidth) of the APC control loop. tx_apc FIELD NAME apc_delay TYPE R/W DESCRIPTION POR 0000 0000: 0001: 0010: 0011: : 1110: 0μs 128μs 256μs 384μs 1792μs 1111: 1920μs 3–0 A5h A6h A7h apc_loop_gain FIELD NAME 1–0 tx_biasdac A8h tx_bias_threshold POR R/W 00h TYPE POR R/W 28h Bits 7-0 of the 10-bit value which controls the bias current. The default is non-zero so that there is sufficient current for the loop fault detect circuits to operate correctly. TYPE POR DESCRIPTION — — Undefined R/W 00 Bits 9-8 of the 10-bit value which controls the bias current TYPE POR R/W FFh This is the MPD current target level for both the APC loop and the fast-start algorithm. FIELD NAME — mon_bandwidth TYPE POR — — R/W 1000 TYPE POR R/W 80h tx_fstart_initial Maxim Integrated If tx_biasdac exceeds tx_bias_threshold then the excessive_bias bit is set in system_status. Determines the bandwidth of the first order digital lowpass filter which is applied by the power monitoring circuit to the measured value of MPD current. tx_mon_bandwidth BIT AAh 2-2 2-1 1 tx_biasdac1 — 3–0 2-15 2-14 2-13 TYPE tx_biasdac0 7–2 7–4 1000 tx_apc_target BIT A9h R/W 0000: 0001: 0010: : 1101: 1110: 1111: DESCRIPTION Undefined 0000: 0001: … 1000: … 1110: 1111: 311Hz 622Hz 80kHz 5.1MHz No filtering Determines the initial step size of the fast-start algorithm. 42 ABh Determines the multiplication factor applied to the step size on each step of the fast-start algorithm after the MPD current first exceeds the target threshold. tx_fstart_decay BIT FIELD NAME TYPE DESCRIPTION POR 100000: 32/64 = 0.5 100001: 33/64 = 0.516 100010: 34/64 = 0.531 100011: 35/64 = 0.547 7–2 fstart_decay R/W 100101 100100: 36/64 = 0.563 100101: 37/64 = 0.5785 .. 101110: 46/64 = 0.719 101111: 47/64 = 0.734 1–0 — ACh tx_fstart_duration BIT FIELD NAME 7 6 — fstart_recovery_en — Determines the duration of the fast-start algorithm (an iteration is 4 cycles of the 64 MHz system clock) and whether the laser is shut down for one or two cycles afterwards while the modulation control circuits settle. TYPE POR R/W 1 fstart_recovery_time R/W 0 5–0 fstart_duration R/W 001111 ADh txsd_config BIT 7–4 3–2 FIELD NAME txsd_rogueonu_delay txsd_threshold Undefined DESCRIPTION 1: Briefly shut down bias and modulation after the fast-start algorithm 0: Shut down for single iteration, 1: Shut down for 2 iterations The fast-start algorithm runs for a number of iterations specified by this register. Configures the TX signal detect feature. TYPE POR R/W 0011 DESCRIPTION The delay (in 64MHz clock cycles) between the falling edge of BEN and the testing for rogue ONU. R/W 00 MPD current level above which signal is detected during bursts and rogue ONU is detected during gaps. 00: 20μA 01: 40μA 10: 60μA 11: 80mA 1 — — — Undefined 0 — — — Undefined TYPE POR AEh txsd_deglitch_period R/W 02h The approximate time between the loss of transmitted signal and the deassertion of TX_SD during a burst: 00h: 01h: 02h: a: 16ns to 31ns 31ns to 62ns 46ns to 92ns b to c b = (a + 1) x 15.625ns Maxim Integrated c = 2b 43 AFh ls_txfault_faulten BIT FIELD NAME Enables the fault conditions associated with the tx_fault laser safety system TYPE POR DESCRIPTION 7 Alarm R/W 1 1: Enable this fault condition for the tx_fault laser safety system 6 rogue_onu R/W 1 1: Enable this fault condition for the tx_fault laser safety system 5 soft_tx_fault R/W 1 1: Enable this fault condition for the tx_fault laser safety system 4 tx_disable R/W 0 1: Enable this fault condition for the tx_fault laser safety system 3 Vdd R/W 1 1: Enable this fault condition for the tx_fault laser safety system 2 Vref R/W 1 1: Enable this fault condition for the tx_fault laser safety system 1 Apc R/W 1 1: Enable this fault condition for the tx_fault laser safety system 0 Bias R/W 1 1: Enable this fault condition for the tx_fault laser safety system B0h ls_txfault_latchen BIT FIELD NAME Latches the fault conditions associated with the tx_fault laser safety system TYPE POR DESCRIPTION 7 Alarm R/W 1 1: Enable latching for this fault condition 6 rogue_onu R/W 1 1: Enable latching for this fault condition 5 soft_tx_fault R/W 0 1: Enable latching for this fault condition 4 tx_disable R/W 0 1: Enable latching for this fault condition 3 Vdd R/W 1 1: Enable latching for this fault condition 2 Vref R/W 1 1: Enable latching for this fault condition 1 Apc R/W 1 1: Enable latching for this fault condition 0 Bias R/W 1 1: Enable latching for this fault condition B1h ls_shutdown_faulten BIT FIELD NAME Enables the fault conditions associated with the shutdown laser safety system TYPE POR DESCRIPTION 7 Alarm R/W 1 1: Enable this fault condition for the shutdown laser safety system 6 rogue_onu R/W 1 1: Enable this fault condition for the shutdown laser safety system 5 soft_tx_fault R/W 0 1: Enable this fault condition for the shutdown laser safety system 4 tx_disable R/W 1 1: Enable this fault condition for the shutdown laser safety system 3 Vdd R/W 1 1: Enable this fault condition for the shutdown laser safety system 2 Vref R/W 1 1: Enable this fault condition for the shutdown laser safety system 1 Apc R/W 1 1: Enable this fault condition for the shutdown laser safety system 0 Bias R/W 1 1: Enable this fault condition for the shutdown laser safety system Maxim Integrated 44 B2h ls_shutdown_latchen BIT FIELD NAME Latches the fault conditions associated with the shutdown laser safety system TYPE POR DESCRIPTION 7 Alarm R/W 1 1: Enable latching for this fault condition 6 rogue_onu R/W 1 1: Enable latching for this fault condition 5 soft_tx_fault R/W 0 1: Enable latching for this fault condition 4 tx_disable R/W 0 1: Enable latching for this fault condition 3 Vdd R/W 1 1: Enable latching for this fault condition 2 Vref R/W 1 1: Enable latching for this fault condition 1 Apc R/W 1 1: Enable latching for this fault condition 0 Bias R/W 1 1: Enable latching for this fault condition B3h Controls which of the DDM alarm flags contribute to the laser safety alarm_fault fault condition. ls_alarmflag_en BIT FIELD NAME TYPE POR DESCRIPTION 7 temp_hifault_en R/W 0 1: Alarm fault occurs when temp exceeds high temp threshold 6 temp_lofault_en R/W 0 1: Alarm fault occurs when temp below low temp threshold 5 supply_hifault_en R/W 0 1: Alarm fault occurs when supply exceeds high supply threshold 4 supply_lofault_en R/W 0 1: Alarm fault occurs when supply below low supply threshold 3 bias_hifault_en R/W 0 1: Alarm fault occurs when bias exceeds high bias threshold 2 bias_lofault_en R/W 0 1: Alarm fault occurs when bias below low bias threshold 1 txpower_hifault_en R/W 0 1: Alarm fault occurs when txpower exceeds high txpower threshold 0 txpower_lofault_en R/W 0 1: Alarm fault occurs when txpower below low txpower threshold The samples of supply and rxpower may be lowpass filtered using a filter with programmable bandwidth. B4h 00: 01: 10: 11: adc_filter fs/(2 x pi x 64) = 0.25Hz fs/(2 x pi x32) = 0.5Hz fs/(2 x pi x16) = 1Hz fs/(2 x pi x 8) = 2Hz fS = 100Hz based on measurements every 10ms. BIT FIELD NAME TYPE POR DESCRIPTION — — Undefined 7–6 — 5–4 rxpower_bandwidth R/W 00 Selects rxpower filter bandwidth 3–2 supply_bandwidth R/W 00 Selects supply filter bandwidth 1–0 — — — Undefined B5h adc_config BIT FIELD NAME 7–6 — 5–4 adc_supplysel 3–0 — Maxim Integrated Configure the ADC TYPE POR DESCRIPTION — — Undefined R/W 00 00: VDD_TX 10: VDD_RX 01: VDD_TXO 11: VDD_RXO — — Undefined 45 B6h temp_config BIT FIELD NAME Configures the temperature sensor TYPE POR DESCRIPTION 7 temp_ext_sensor R/W 0 1: Use external sensor, 0: Use internal sensor 6 — R/W 11 Reserved 5 leave_PU R/W 1 0: Enable tempsense_pu — — Undefined 4–0 — B7h main_config BIT FIELD NAME Selects the operations performed when the main loop is enabled. Operations are performed once per iteration of the loop. TYPE POR DESCRIPTION 7 biaslut_en R/W 1 1: Load tx_biasdac register form the bias LUT 6 sff_en R/W 1 1: Recalculate sff-8472 DDMs 5 — — — Undefined 4 trackinglut_en R/W 1 Power monitor uses values from the tracking LUT 3 apdlut_en R/W 1 1: Load the rx_apddac, rx_apdpwm or rx_apd_target register from the APD LUT 2 modlut_en R/W 1 1: Load the tx_moddac register from the modulation LUT 1 — — — Undefined 0 mainloop_en R/W 0 1: Enable the main loop B8h sleep_config BIT FIELD NAME Configures Sleep mode TYPE POR DESCRIPTION 7–6 — — — Undefined 5 — — — Reserved 4 rx_respond_to_sleeppin R/W 0 1: Power down Rx when SLEEP pin asserted, 0: Ignore SLEEP pin 3–2 — — — Undefined 1 — — — Reserved 0 tx_respond_to_sleeppin R/W 0 1: Power down Tx when SLEEP pin asserted, 0: Ignore SLEEP pin B9h temp_calibrate BIT FIELD NAME 7–6 — 5–0 temp_calibrate BAh Used during calibration of temperature sensor TYPE POR — — R/W 011111 TYPE POR R/W FFh rx_power_threshold Maxim Integrated DESCRIPTION Undefined Calibration trim register The threshold that defines which pair of Rx Power calibration constants is used. If the 3-slope encoded sample of rx power is above this threshold then select rxpower_slope1 and rxpower_offset1. Otherwise select rxpower_slope0 and rxpower_offset0. 46 BEh pin_config0 BIT FIELD NAME Pin function and polarity configuration TYPE POR DESCRIPTION — — Undefined 7 — 6 dac_select R/W 1 1: DAC pin 39, 0: TX_FAULT pin 39 5 txsd_select R/W 0 1: TX_SD pin 21, 0: TX_FAULT pin 21 4 txfault_invert R/W 0 1: Invert the signal to TX_FAULT pin, 0: No inversion 3 los_invert R/W 0 1: LOS pin = 1 when signal detected and LOS pin = 0 when no signal 2 — R/W 0 Reserved 1 — R/W 0 Reserved 0 tx_disable_invert R/W 0 1: Signal from TX_DISABLE pin is inverted, 0: No inversion BFh pin_config1 BIT 7–4 0: LOS pin = 1 when no signal detected and LOS = 0 when signal FIELD NAME — Masks outputs which should remain quiet during initialization TYPE POR DESCRIPTION — — Undefined 3 apd_inhibit R/W 1 1: APD_CTRL disabled (= Hi-Z), 0: Normal function 2 txsd_allow R/W 0 0: TX_SD disabled (= 1), 1: Normal function 1 los_inhibit R/W 1 1: LOS disabled (= 1), 0: Normal function 0 laser_inhibit R/W 1 1: TX_OUT and BIAS are shutdown, 0: Normal function C0h software_faults BIT 7–1 0 C1h FIELD NAME — soft_tx_fault 5 TYPE POR — — Undefined R/W 0 1: Asserts the soft_tx_fault laser safety fault condition temp_control BIT 7–6 This register is used to set fault conditions via the TWI FIELD NAME — tempsense_pu 4–0 — E0h initialization_status BIT FIELD NAME DESCRIPTION Configures the temperature sensor TYPE POR DESCRIPTION — — Undefined R/W 1 0: temperature sensor powers down between reads — — Undefined Reports status associated with device initialization TYPE POR DESCRIPTION 7 — E 0 Reserved 6 — — — Undefined 5 eeprom_dma_idle R 0 1: EEPROM is idle and may be accessed 4 — R 1 Reserved 3 tx_powerup_done R 0 1: Tx path power up during initialization is complete 2 rx_powerup_done R 0 1: Rx path power up during initialization is complete 1 eeprom_data_invalids R 0 1: Data integrity check failed during initialization 0 eeprom_unresponsive R 0 1: EEPROM failed to ACK the slave address during initialization Maxim Integrated 47 E1h ls_fault_status BIT FIELD NAME Reports real time status of fault conditions at input to the laser safety system TYPE POR DESCRIPTION 7 Alarm R — 1: Fault condition currently exists 6 rogue_onu R — 1: Fault condition currently exists 5 soft_tx_fault R — 1: Fault condition currently exists 4 tx_disable R — 1: Fault condition currently exists 3 Vdd R — 1: Fault condition currently exists 2 Vref R — 1: Fault condition currently exists 1 Apc R — 1: Fault condition currently exists 0 Bias R — 1: Fault condition currently exists E2h Records when the fault conditions at the input to the laser safety system have been asserted. Write ‘1’ to these bits to clear back to ‘0’ ls_fault_events BIT FIELD NAME TYPE POR DESCRIPTION 7 Alarm E — 1: Fault condition has occurred 6 rogue_onu E — 1: Fault condition has occurred 5 soft_tx_fault E — 1: Fault condition has occurred 4 tx_disable E — 1: Fault condition has occurred 3 Vdd E — 1: Fault condition has occurred 2 Vref E — 1: Fault condition has occurred 1 Apc E — 1: Fault condition has occurred 0 Bias E — 1: Fault condition has occurred E4h hardware_status BIT TYPE POR — — — Undefined 4 txsd_pin R — Indicates the status of the TXSD pin 3 tx_fault_pin R — Indicates the status of the TX_FAULT pin 2 Shutdown R — Indicates the status of the internal shutdown signal 1 sleep_pin R — Indicates the status of the SLEEP pin 0 tx_disable_pin R — Indicates the status of the TX_DISABLE pin TYPE POR R — 7–5 E6h FIELD NAME Reports the real-time status of selected digital pins temperature_uncal Maxim Integrated DESCRIPTION The temperature sample value before calibration 48 E7h E8h E9h EAh EBh TYPE POR R — TYPE POR R — TYPE POR R — TYPE POR R — TYPE POR R — supply_uncal The supply sample value before calibration bias_uncal The bias sample value before calibration txpower_uncal The tx_power value before re-ranging and calibration rxpower_uncal The rxpower sample value before calibration apdadc_uncal Maxim Integrated The uncalibrated measure of APD voltage 49 Simplified Interface Models VDD VDD 50Ω VDD 50Ω RX_OUT+ RX_IN+ 50Ω 50Ω RX_OUT- RX_INVCM VDD 24kΩ 16kΩ VCC VDD TX_OUT+/- VDD 5kΩ TX_IN+ VDD VDD 24kΩ 16kΩ TX_IN5kΩ VDD VDD LOS, TX_SD VDD BIAS MPD Figure 27. Interface Diagrams Maxim Integrated 50 ONU Application Diagrams VDD 24kW VCC TX_IN+ BEN+ 130W 16kW VDD VDD 5kW 82Ω VDD 24kW VCC 16kW VDD 130W 5kW TX_INBEN- 82Ω Figure 28. LVPECL External Terminations VDD VCC 24kW 50W TX_IN+ BEN+ VDD VDD 5kW VCC 50W 16kW VDD 24kW 100W 16kW VDD 5kW TX_INBEN- Figure 29. CML External Terminations Maxim Integrated 51 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4055+2 21-0140 90-0002 Maxim Integrated 52 Revision History REVISION NUMBER REVISION DATE 0 11/12 Initial release 1 7/13 Made corrections to Pin Description, Figure 15, 94h register table 2 2/14 Made corrections to Pin Description, apc loop bandwidth section, Figure 15, mismatch font, mpd_range section, Register Map section, Figure 29, and bold typeface for register table headings DESCRIPTION PAGES CHANGED — 10, 24, 39 10, 12, 20, 21, 25– 29, 36–49, 50, 52 53 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated, 160 Ri o Robles, San Jose, CA 95134 1-408-601-1000 Ó 2014 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.