MAX8756ETI+T

19-3569; Rev 2; 4/07 KIT ATION EVALU E L B AVAILA Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers Features o Fixed Switching Frequency 200kHz, 300kHz, or 500kHz 250kHz, 300kHz, or 400kHz (MAX8756 Only) o No Current-Sense Resistor Required o 40/60 Optimal Interleaving o Reduced Input-Capacitor Requirement o Output Voltage Fixed or Adjustable Outputs (Dual Mode™) 3.3V/5V Fixed or 1V to 5.5V Adjustable 1.5V/1.8V Fixed or 1V to 2.3V Adjustable (MAX8756 Only) o 4V to 26V Input Range o Independently Selectable PWM, Skip, and LowNoise Mode Operation o Soft-Start and Soft-Stop o 2V Precision Reference with 0.75% Accuracy o Independent Power-Good Outputs Ordering Information TEMP RANGE PINPACKAGE MAX8716ETG -40°C to +85°C 24 Thin QFN 4mm x 4mm T2444-4 MAX8716ETG+ -40°C to +85°C 24 Thin QFN 4mm x 4mm T2444-4 MAX8717ETI -40°C to +85°C 28 Thin QFN 5mm x 5mm T2855-6 PART Applications 2 to 4 Li+ Cell Battery-Powered Devices Notebook and Subnotebook Computers PDAs and Mobile Communicators Main or I/O Power Supplies PKG CODE +Denotes a lead-free package. Ordering Information continued at end of data sheet. Dual Mode is a trademark of Maxim Integrated Products, Inc. Pin Configurations TOP VIEW DH1 19 12 BST2 12 CSH2 CSH2 CSH1 24 CSL1 22 9 CSL2 CSL1 25 FB1 23 8 FB2 FB1 26 PGOOD1 24 7 PGOOD2 PGOOD1 ILIM1 6 15 13 BST2 5 16 14 10 4 17 23 11 3 18 BST1 21 2 19 DH2 DH2 20 1 20 22 BST1 + 21 DH1 CSH1 MAX8716ETG LX2 13 DL2 LX2 14 VDD DL2 15 PGND VDD 16 AGND GND 17 DL1 DL1 18 LX1 LX1 TOP VIEW 11 CSL2 10 FB2 27 9 PGOOD2 28 8 ILIM2 MAX8717ETI MAX8756ETI+ MAX8757ETI+ 5 6 7 ON1 ON2 REF 4 FSEL 3 SKIP2 2 VCC ON2 1 SKIP1 TQFN A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. ON1 SKIP2 REF VCC SKIP1 + TQFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8716/MAX8717/MAX8756/MAX8757 General Description The MAX8716/MAX8717/MAX8756/MAX8757 are dual, step-down, interleaved, fixed-frequency, switch-mode power-supply (SMPS) controllers with synchronous rectification. The MAX8716/MAX8717/MAX8756/MAX8757 are intended for main (5V/3.3V) power generation, while the MAX8756 is optimized for I/O power rails in batterypowered systems. Fixed-frequency operation with optimal interleaving minimizes input ripple current from the lowest input voltages up to the 26V maximum input. Optimal 40/60 interleaving allows the input voltage to go down to 8.3V before duty-cycle overlap occurs in 5V/3.3V applications, compared to 180° out-of-phase regulators where the dutycycle overlap occurs when the input drops below 10V. Accurate output current limit is achieved using a sense resistor. Alternatively, power dissipation can be reduced using lossless inductor current sensing. Independent ON/OFF controls and power-good signals allow flexible power sequencing. Soft-start reduces inrush current, while soft-stop gradually ramps the output voltage down preventing negative voltage dips. A low-noise mode maintains high light-load efficiency while keeping the switching frequency out of the audible range. The MAX8716 is available in a 24-pin thin QFN package, and the MAX8717/MAX8756/MAX8757 are available in a 28-pin thin QFN package. MAX8716/MAX8717/MAX8756/MAX8757 Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers ABSOLUTE MAXIMUM RATINGS (Note 1) VDD, VCC, CSL1, CSH1, CSL2, CSH2 to AGND ......-0.3V to +6V ON1, ON2, SKIP1, SKIP2, PGOOD1, PGOOD2 to AGND ...............................................-0.3V to +6V FB1, FB2, ILIM1, ILIM2, FSEL to AGND ...................-0.3V to +6V REF to AGND..............................................-0.3V to (VCC + 0.3V) BST1, BST2 to AGND .............................................-0.3V to +36V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V) AGND to PGND .....................................................-0.3V to +0.3V REF Short Circuit to AGND.........................................Continuous REF Current ......................................................................+10mA Continuous Power Dissipation (TA = +70°C) 24-Pin Thin QFN 4mm x 4mm (derate 20.8mW/°C above +70°C)..........................................................1666.7mW 28-Pin Thin QFN 5mm x 5mm (derate 21.3mW/°C above +70°C)..........................................................1702.1mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: For the 24-pin TQFN version, AGND and PGND refer to a single pin designated GND. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VIN = 12V, FSEL = REF, SKIP_ = 0, VON_ = VILIM_ = VCC = VDD = 5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT SUPPLIES Input Voltage Range VIN 26 VBIAS VCC, VDD VUVLO 200mV typical hysteresis 4.5 5.5 V VCC rising 3.9 4.15 4.4 VCC falling MAX8716, MAX8717, MAX8757 MAX8756 3.7 3.95 4.2 0.8 1.3 1 1.8 CSL_ and FB_ forced above their regulation points ILOAD(MAX) + ⎜ INDUCTOR ⎟ ⎝ ⎠ 2 where ILIMIT_ equals the minimum current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum current-limit threshold is 50mV. Connect ILIM_ to VCC for a default 50mV current-limit threshold. In adjustable mode, the current-limit threshold is precisely 1/10 the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 500mV to 2V adjustment range corresponds to a 50mV to 200mV current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the currentlimit tolerance. The current-sense method (Figure 8) and magnitude determines the achievable current-limit accuracy and power loss. Typically, higher current-sense limits provide tighter accuracy, but also dissipate more power. Most applications employ a current-limit threshold (VLIM) of 50mV to 100mV, so the sense resistor can be determined by: RSENSE_ = VLIM_ / ILIM_ For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 8a. This configuration constantly monitors the inductor current, allowing accurate current-limit protection. Alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series RC circuit across the inductor (Figure 8b) with an equivalent time constant: L = CEQ × REQ RL where RL is the inductor’s series DC resistance. In this configuration, the current-sense resistance equals the inductor’s DC resistance (RSENSE = RL). Use the worstcase inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. ______________________________________________________________________________________ Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers DH_ NH RSENSE L LX_ MAX8716 DL_ MAX8717 MAX8756 PGND MAX8757 COUT DL NL CSH_ CSL_ a) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) DH_ NH CIN NL DL INDUCTOR LX_ MAX8716 DL_ MAX8717 MAX8756 PGND MAX8757 COUT REQ CEQ CSH_ CSL_ b) LOSSLESS INDUCTOR SENSING RBIAS = REQ Figure 8. Current-Sense Configurations Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors (see the Output-Capacitor Stability Considerations section), the filter capacitor’s ESR dominates the output voltage ripple. So the output capacitor’s size depends on the maximum ESR required to meet the output-voltage-ripple (VRIPPLE(P-P)) specifications: VRIPPLE(P-P) = RESRILOAD(MAX)LIR In Idle Mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode currentsense threshold (VIDLE = 0.2VLIMIT). In Idle Mode, the no-load output ripple can be determined as follows: V R VRIPPLE(P−P) = IDLE ESR RSENSE The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may effect the overall stability (see the OutputCapacitor Stability Considerations section). ______________________________________________________________________________________ 23 MAX8716/MAX8717/MAX8756/MAX8757 INPUT (VIN) CIN Output-Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: ƒ ƒ ESR ≤ SW π where: ƒ ESR = 1 2πRESR COUT For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V SANYO polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. For low input-voltage applications where the duty cycle exceeds 50% (VOUT / VIN ≥ 50%), the output ripple voltage should not be greater than twice the internal slope-compensation voltage: VRIPPLE ≤ 0.02 x VOUT where VRIPPLE equals ΔIINDUCTOR x RESR. The worstcase ESR limit occurs when VIN = 2 x VOUT, so the above equation can be simplified to provide the following boundary condition: RESR ≤ 0.04 x L x ƒOSC Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: short/long pulses or cycle skipping resulting in a lower switching frequency. Instability occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering too early or skipping a cycle. Cycle skipping is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can 24 cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents. For an out-of-phase regulator, the total RMS current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of overlap as defined in Figure 9. The 40/60 optimal interleaved architecture of the MAX8716/MAX8717/MAX8756/MAX8757 allows the input voltage to go as low as 8.3V before the duty cycles begin to overlap. This offers improved efficiency over a regular 180° out-of-phase architecture where the duty cycles begin to overlap below 10V. Figure 9 INPUT CAPACITOR RMS CURRENT vs. INPUT VOLTAGE 5.0 4.5 4.0 IN PHASE 3.5 IRMS (A) MAX8716/MAX8717/MAX8756/MAX8757 Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers 50/50 INTERLEAVING 3.0 2.5 2.0 1.5 40/60 OPTIMAL INTERLEAVING 1.0 0.5 5V/5A AND 3.3V/5A 0 6 8 10 12 14 16 18 20 VIN (V) INPUT RMS CURRENT FOR INTERLEAVED OPERATION IRMS = (IOUT1 - IIN)2 (DLX1 - DOL) + (IOUT2 - IIN)2 (DLX2 - DOL) + (IOUT1 + IOUT2 - IIN)2 DOL + IIN2 (1 - DLX1 - DLX2 + DOL) V DLX1 = OUT1 VIN V DLX2 = OUT2 VIN DOL = DUTY-CYCLE OVERLAP FRACTION V I +V I IIN = OUT1 OUT1 OUT2 OUT2 VIN INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION ( IRMS = ILOAD VOUT (VIN - VOUT) VIN ) Figure 9. Input RMS Current ______________________________________________________________________________________ Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, optimum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX8716/MAX8717/MAX8756/MAX8757 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drainto-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the lowside MOSFET since it is a zero-voltage switched device when used in the step-down topology. Power MOSFET Dissipation Worst-case conduction losses occur at the duty-factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: V PD (NH RESISTIVE) = OUT (ILOAD )2RDS(ON) VIN Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH SWITCHING) = ⎛ VIN(MAX)ILOADfSW ⎞ ⎛ QG(SW) ⎞ COSS VIN2 fSW ⎜ ⎟⎜ I ⎟ + η TOTAL 2 ⎝ ⎠ ⎝ GATE ⎠ where COSS is the NH, MOSFET's output capacitance, Q G(SW) 2 , is the change needed to turn on the N H MOSFET, and I GATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: ⎡ ⎛ V ⎞⎤ PD (NL RESISTIVE) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD )2 RDS(ON) ⎢ ⎝ VIN(MAX) ⎠ ⎥ ⎣ ⎦ The absolute worst case for MOSFET power dissipation occurs under heavy-overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ⎛ ΔI ⎞ ILOAD = ILIMIT − ⎜ INDUCTOR ⎟ ⎝ ⎠ 2 where ILIMIT is the peak current allowed by the currentlimit circuit, including threshold tolerance and senseresistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. ______________________________________________________________________________________ 25 MAX8716/MAX8717/MAX8756/MAX8757 shows the input-capacitor RMS current vs. input voltage for an application that requires 5V/5A and 3.3V/5A. This shows the improvement of the 40/60 optimal interleaving over 50/50 interleaving and in-phase operation. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. Choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime. MAX8716/MAX8717/MAX8756/MAX8757 Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical. (ΔI UP). This results in a minimum operating voltage defined by the following equation: Boost Capacitors where VCHG and VDIS are the parasitic voltage drops in the charge and discharge paths, respectively. A reasonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: CBST = QGATE 200mV where QGATE is the total gate charge specified in the high-side MOSFET’s data sheet. For example, assume the FDS6612A n-channel MOSFET is used on the high side. According to the manufacturer’s data sheet, a single FDS6612A has a maximum gate charge of 13nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 13nC = 0.065μF 100mV Selecting the closest standard value, this example requires a 0.1µF ceramic capacitor. Applications Information Duty-Cycle Limits Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the Electrical Characteristics table). For the best dropout performance, use the slowest switching-frequency setting (FSEL = GND). However, keep in mind that the transient performance gets worse as the stepdown regulators approach the dropout voltage, so bulk output capacitance must be added (see the voltage sag and soar equations in the Design Procedure section). The absolute point of dropout occurs when the inductor current ramps down during the off-time (ΔIDOWN) as much as it ramps up during the on-time 26 ⎛ 1 ⎞ VIN(MIN) = VOUT + VCHG + h ⎜ − 1⎟ (VOUT + VDIS ) ⎝ DMAX ⎠ Maximum Input Voltage The MAX8716/MAX8717/MAX8756/MAX8757 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the Electrical Characteristics table). Operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by SKIP. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (VIN(SKIP)): ⎛ ⎞ 1 VIN(SKIP) = VOUT ⎜ ⎟ ⎝ ƒ OSC t ON(MIN) ⎠ where fOSC is the switching frequency selected by FSEL. PCB Layout Guidelines Careful PCB layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 10). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PCB layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. ______________________________________________________________________________________ Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers Layout Procedure 1) Place the power components first, with ground terminals adjacent (NL_ source, CIN, COUT_, and DL_ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL_ and NH_ to keep LX_, GND, DH_, and the DL_ gatedrive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST_ diode and capacitor and LDO5 bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 10. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. Chip Information TRANSISTOR COUNT: 5879 PROCESS: BiCMOS ______________________________________________________________________________________ 27 MAX8716/MAX8717/MAX8756/MAX8757 • Minimize current-sensing errors by connecting CSH_ and CSL_ directly across the current-sense resistor (RSENSE_). • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSH_, CSL_). CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN VIA TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND VIA TO VCC BYPASS CAPACITOR VIA TO REF BYPASS CAPACITOR VIA TO VCC PIN VIA TO REF PIN MAX8717/MAX8756/MAX8757 BOTTOM LAYER MAX8717/MAX8756/MAX8757 TOP LAYER KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO THE EVALUATION KIT) INDUCTOR SINGLE n-CHANNEL MOSFETS DH LX DL COUT CIN COUT INPUT OUTPUT COUT OUTPUT INPUT GROUND GROUND HIGH-POWER LAYOUT LOW-POWER LAYOUT Figure 10. PCB Layout Example Ordering Information (continued) TEMP RANGE PINPACKAGE MAX8717ETI+ -40°C to +85°C 28 Thin QFN 5mm x 5mm T2855-6 MAX8756ETI+ -40°C to +85°C 28 Thin QFN 4mm x 4mm T2855-6 MAX8757ETI+ -40°C to +85°C 28 Thin QFN 5mm x 5mm T2855-6 PART PKG CODE +Denotes a lead-free package. 28 DUAL n-CHANNEL MOSFET INDUCTOR CIN MAX8716/MAX8717/MAX8756/MAX8757 Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers ______________________________________________________________________________________ Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers 24L QFN THIN.EPS PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 F 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 F 2 2 ______________________________________________________________________________________ 29 MAX8716/MAX8717/MAX8756/MAX8757 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX8716/MAX8717/MAX8756/MAX8757 Interleaved High-Efficiency, Dual Power-Supply Controllers for Notebook Computers Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.