19-0866; Rev 1; 1/08
KIT
ATION
EVALU
E
L
B
A
AVAIL
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Features
The MAX9796 combines a high-efficiency Class D, mono
audio power amplifier with a mono DirectDrive™ receiver
amplifier and a stereo DirectDrive headphone amplifier.
Maxim’s 3rd-generation, ultra-low EMI, Class D audio
power amplifiers provide Class AB performance with
Class D efficiency. The MAX9796 delivers 2.3W into a 4Ω
load from a 5V supply and offers efficiencies up to 80%.
Active emissions limiting circuitry and spread-spectrum
modulation greatly reduce EMI, eliminating the need for
output filtering found in traditional Class D devices.
♦ Unique Spread-Spectrum Modulation and Active
Emissions Limiting Significantly Reduces EMI
♦ Up to 3 Stereo Inputs
♦ 2.3W Mono Speaker Output (4Ω, VDD = 5V)
♦ 50mW Mono Receiver/Stereo Headphone Outputs
(32Ω, VDD = 3.3V)
♦ High PSRR (68dB at 217Hz)
♦ 80% Efficiency (VDD = 3.3V, RL = 8Ω, POUT =
600mW)
♦ I2C Control—Input Configuration, Volume
Control, Output Mode
♦ Click-and-Pop Suppression
♦ Low Total Harmonic Distortion (0.03% at 1kHz)
♦ Current-Limit and Thermal Protection
♦ Available in Space-Saving, 36-Bump UCSP
(3mm x 3mm)
The MAX9796 features a fully differential architecture, a
full-bridged output, and comprehensive click-and-pop
suppression. The device utilizes a flexible, user-defined
mixer architecture that includes an input mixer, volume
control, and output mixer. All controls are done through
an I2C interface.
The mono receiver amplifier and stereo headphone
amplifier use Maxim’s DirectDrive architecture, that produces a ground-referenced output from a single supply,
eliminating the need for large DC-blocking capacitors,
saving cost, space, and component height.
The MAX9796 is available in a 36-bump UCSP™ (3mm
x 3mm) package and is specified over the extended
-40°C to +85°C temperature range.
Ordering Information
PART
PINPACKAGE
TEMP RANGE
MAX9796EBX+T
PKG
CODE
-40°C to +85°C 36 UCSP-36*
B36-4
+Denotes a lead-free package.
*Four center bumps depopulated.
Applications
Pin Configuration
Cell Phones
Portable Multimedia Players
TOP VIEW
(BUMPS ON BOTTOM)
Handheld Gaming Consoles
Simplified Block Diagram
1
2
3
4
5
6
CPVDD
C1P
CPGND
C1N
CPVSS
HPL
PVDD
I.C.
VBIAS
INC1
VSS
HPR
OUT+
SDA
INC2
OUTRx
PGND
SCL
INB2
VDD
OUT-
SHDN
INA1
INA2
INB1
I.C.
PVDD
OUT-
PGND
OUT+
PVDD
GND
A
SINGLE SUPPLY 2.7V TO 5.5V
B
GAIN
CONTROL
C
MIXER/
MUX
I2C
INTERFACE
MAX9796
D
E
F
MAX9796
UCSP is a trademark of Maxim Integrated Products, Inc.
UCSP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX9796
General Description
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................................+6V
PVDD to PGND .......................................................................+6V
CPVDD to CPGND..................................................................+6V
CPVSS to CPGND .....................................................-6V to +0.3V
VSS to CPGND..........................................................-6V to +0.3V
C1N .......................................(CPVSS - 0.3V) to (CPGND + 0.3V)
C1P.......................................(CPGND - 0.3V) to (CPVDD + 0.3V)
HPL, HPR to GND...................(CPVSS - 0.3V) to (CPVDD + 0.3V)
GND to PGND and CPGND................................................±0.3V
VDD to PVDD and CPVDD ....................................................±0.3V
SDA, SCL to GND.....................................................-0.3V to +6V
All other pins to GND..................................-0.3V to (VDD + 0.3V)
Continuous Current In/Out of PVDD, PGND, CPVDD, CPGND,
OUT_ _, HPR, and HPL................................................±800mA
Continuous Input Current CPVSS....................................+260mA
Continuous Input Current (all other pins) .........................±20mA
Duration of Short Circuit Between
OUT+ and OUT-......................................................Continuous
Duration of HP_ OUT_ Short Circuit to
GND or PVDD ..........................................................Continuous
Continuous Power Dissipation (TA = +70°C)
36-Bump (3mm x 3mm) UCSP Multilayer Board
(derate 17.0mW/°C above +70°C) ...........................1360.5mW
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between
OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1µF. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
GENERAL
Supply Voltage Range
VDD,
PVDD,
CPVDD
Inferred from PSRR test
2.7
Output mode 1, 6, 11 (Rx mode)
Quiescent Current
Mute Current
Shutdown Current
IDD
IMUTE
ISHDN
Turn-On Time
tON
Input Resistance
RIN
6.3
10
Output mode 4, 9, 14 (HP mode)
8
12.6
Output mode 2, 7, 12 (SP mode)
11.8
17.5
Output mode 3, 8, 13 (SP and HP modes)
15.1
21
Current in mute
4.7
10
Hard shutdown
SHDN = GND
0.1
10
Soft shutdown
See the I2C Interface
section
8.5
15
Time from shutdown or power-on to full
operation
30
mA
µA
ms
B and C pair inputs, TA = +25°C,
VOL = max
17.5
28
41.0
kΩ
8.0
kΩ
A pair inputs, TA = +25°C, +20dB
3.5
5.5
Common-Mode Rejection Ratio
CMRR
TA = +25°C, VIN = ±500mV
45
50
Input DC Bias Voltage
VBIAS
IN_ inputs
1.12
1.25
2
mA
_______________________________________________________________________________________
dB
1.38
V
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between
OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1µF. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
±5.5
±23.5
UNITS
SPEAKER AMPLIFIER
Output Offset Voltage
Click-and-Pop Level
VOS
KCP
TA = +25°C
TMIN ≤ TA ≤ TMAX
Peak voltage, TA =
+25°C, A-weighted,
32 samples per
second (Notes 3, 4)
±40
Into shutdown
Power-Supply Rejection Ratio
(Note 3)
Output Power (Note 4)
PSRR
POUT
TA = +25°C
THD+N = 1%,
TA = +25°C
-60
Into mute
-63
Out of mute
-62
Signal-to-Noise Ratio
Gain
THD+N
SNR
fOSC
η
AV
f = 1kHz
VOUT = 1.8VRMS,
RL = 8Ω (Note 3)
68
f = 1kHz, 100mVP-P
ripple
60
f = 20kHz, 100mVP-P
ripple
50
RL = 4Ω, VDD = 5V,
f = 1kHz
2300
RL = 8Ω, VDD = 3.3V,
f = 1kHz
600
RL = 8Ω, VDD = 5V,
f = 1kHz
1300
RL = 8Ω,
POUT = 800mW
0.03
RL = 4Ω,
POUT = 830mW
0.04
BW = 20Hz to 20kHz
A-weighted
dB
70
1.6
Total Harmonic Distortion Plus
Noise (Note 4)
Efficiency
48
f = 217Hz, 100mVP-P
ripple
Current Limit
Output Frequency
-62
Out of shutdown
VDD = 2.7V to 5.5V
mV
dB
mW
A
%
81
dB
84
Fixed-frequency modulation (SSM = 0)
1100
Spread-spectrum modulation (SSM = 1)
1100
±30
kHz
POUT = 470mW, f = 1kHz both channel
driven, L = 68µH in series with 8Ω load
80
%
12
dB
_______________________________________________________________________________________
3
MAX9796
ELECTRICAL CHARACTERISTICS (continued)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between
OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1µF. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RECEIVER AMPLIFIER
Output Offset Voltage
Click-and-Pop Level
VOS
TA = +25°C
KCP
Peak voltage, TA =
+25°C, A-weighted,
32 samples per
second (Notes 3, 5)
±1.8
Into shutdown
-62
Into mute
-67
Out of shutdown
-63
Out of mute
VDD = 2.7V to 5.5V
Power-Supply Rejection Ratio
(Note 3)
Output Power
Gain
Total Harmonic Distortion Plus
Noise
Signal-to-Noise Ratio
PSRR
POUT
TA = +25°C
TA = +25°C,
THD+N = 1%
SNR
80
f = 217Hz, 100mVP-P
ripple
80
f = 1kHz, 100mVP-P
ripple
70
f = 20kHz, 100mVP-P
ripple
62
RL = 16Ω
60
RL = 32Ω
50
3
RL = 16Ω (VOUT = 800mVRMS, f = 1kHz)
0.03
RL = 32Ω (VOUT = 800mVRMS, f = 1kHz)
0.024
RL = 16Ω, VOUT =
800mVRMS (Note 3)
dB
-66
58
AV
THD+N
mV
BW = 20Hz to 20kHz
87
A-weighted
89
dB
mW
dB
%
dB
Slew Rate
SR
0.3
V/µs
Capacitive Drive
CL
300
pF
±1.8
mV
HEADPHONE AMPLIFIERS
Output Offset Voltage
Click-and-Pop Level
VOS
KCP
ESD Protection
TA = +25°C
Peak voltage, TA =
+25°C, A-weighted,
32 samples per
second (Notes 2, 5)
HP_
Into shutdown
-61
Into mute
-65
Out of shutdown
-60
Out of mute
-64
Contact
±4
Air
±8
VDD = 2.7V to 5.5V
Power-Supply Rejection Ratio
(Note 3)
4
PSRR
TA = +25°C
58
dB
kV
80
f = 217Hz, 100mVP-P
ripple
80
f = 1kHz, 100mVP-P
ripple
70
f = 20kHz, 100mVP-P
ripple
62
_______________________________________________________________________________________
dB
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between
OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1µF. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Output Power
POUT
CONDITIONS
TA = +25°C,
THD+N = 1%
MIN
60
RL = 32Ω
50
Current Limit
Gain
AV
Channel-to-Channel Gain
Tracking
Total Harmonic Distortion Plus
Noise
TA = +25°C
THD+N
Signal-to-Noise Ratio
SNR
TYP
RL = 16Ω
UNITS
mW
170
mA
+3
dB
±1
%
RL = 16Ω (VOUT = 800mVRMS, f = 1kHz)
0.03
RL = 32Ω (VOUT = 800mVRMS, f = 1kHz)
0.024
RL = 16Ω, VOUT =
800mVRMS
MAX
BW = 20Hz to 20kHz
92
A-weighted
93
%
dB
Slew Rate
SR
0.3
V/µs
Capacitive Drive
CL
300
pF
75
dB
L to R, R to L, f = 10kHz, RL = 16Ω,
VOUT = 160mVRMS
Crosstalk
VOLUME CONTROL
HP gain (max)
IN+6dB = 0
(minimum gain
setting)
Volume Control
IN+6dB = 1
(maximum gain
setting)
Mono Gain
All outputs
Input Pair A Control
Mute Attenuation (Minimum
Volume)
3
SP gain (max)
12
HP gain (min)
-72
SP gain (min)
-63
HP gain (max)
9
SP gain (max)
18
HP gain (min)
-61
SP gain (min)
-57
Mono + 6dB = 0
0
Mono + 6dB = 1
6
INA+20dB = 0 (minimum gain setting)
Set by IN+6dB
INA+20dB = 1 (maximum gain setting)
20
VIN = 1VRMS
80
dB
dB
dB
dB
DIGITAL INPUTS (SHDN, SDA, SCL)
Input-Voltage High
VIH
Input-Voltage Low
VIL
1.4
V
0.4
Input Hysteresis (SDA, SCL)
VHYS
200
SDA, SCL Input Capacitance
CIN
10
Input Leakage Current
IIN
Pulse Width of Spike Suppressed
tSP
pF
1.0
50
V
mV
µA
ns
_______________________________________________________________________________________
5
MAX9796
ELECTRICAL CHARACTERISTICS (continued)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between
OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1µF. TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
DIGITAL OUTPUTS (SDA Open Drain)
Output Low Voltage SDA
Output Fall Time SDA
VOL
ISINK = 6mA
tOF
VH(MIN) to VL(MAX) bus capacitance = 10pF
to 400pF, ISINK = 3mA
250
ns
I2C INTERFACE TIMING
Serial-Clock Frequency
fSCL
DC
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
START Condition Hold
tHD:STA
0.6
µs
STOP Condition Setup Time
tSU:STA
0.6
µs
Clock Low Period
tLOW
1.3
µs
Clock High Period
tHIGH
0.6
µs
Data Setup Time
tSU:DAT
100
ns
Data Hold Time
tHD:DAT
0
Maximum Receive SCL/SDA Rise
Time
Maximum Receive SCL/SDA Fall
Time
400
kHz
900
ns
tR
300
ns
tF
300
ns
Setup Time for STOP Condition
tSU:STO
Capacitive Load for Each Bus
Line
Cb
0.6
µs
400
pF
All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.
Measured at headphone outputs.
Amplifier inputs AC-coupled to GND.
Testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For RL = 8Ω L = 68µH,
RL = 4Ω L = 47µH.
Note 5: Testing performed at room temperature with an 8Ω resistive load in series with 68µH inductive load connected across BTL
outputs for speaker amplifier. Testing performed with 32Ω resistive load connected between OUT_ and GND for headphone
amplifier. Testing performed with a 32Ω resistive load connected between OUTRx and GND for mono receiver amplifier.
Mode transitions are controlled by SHDN pin.
Note 1:
Note 2:
Note 3:
Note 4:
6
_______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1µF. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
POUT = 1W
1
MAX9796 toc02
1
MAX9796 toc01
1
VDD = 5V
RL = 8Ω
VDD = 3.3V
RL = 4Ω
POUT = 500mW
0.1
POUT = 350mW
0.1
POUT = 1.6W
THD+N (%)
THD+N (%)
THD+N (%)
0.1
0.01
MAX9796 toc03
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
POUT = 750mW
POUT = 800mW
0.01
0.01
VDD = 5V
RL = 4Ω
0.001
0.001
0.001
10
100
1k
10k
100k
10
100
1k
10k
10
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
POUT = 200mW
0.1
THD+N (%)
THD+N (%)
FFM
POUT = 450mW
VDD = 5V
RL = 4Ω
10
20Hz
SSM
0.1
0.01
100
MAX9796 toc06
VDD = 5V
RL = 8Ω
POUT = 500mW
THD+N (%)
VDD = 3.3V
RL = 8Ω
MAX9796 toc05
1
MAX9796 toc04
1
1
10kHz
0.1
0.01
1kHz
0.01
0.001
0.001
10
100
1k
10k
100k
10k
100k
0.6
1.2
1.8
3.0
2.4
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
VDD = 3.3V
RL = 4Ω
10
20Hz
1kHz
1kHz
1
10kHz
0.1
0.01
0.001
0.6
0.9
1.2
OUTPUT POWER (W)
1.5
1.8
1
10kHz
0.1
0.01
20Hz
0.001
0.3
VDD = 3.3V
RL = 8Ω
10
THD+N (%)
THD+N (%)
0.1
100
MAX9796 toc08
MAX9796 toc07
100
MAX9796 toc09
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
10kHz
0
0
OUTPUT POWER (W)
10
THD+N (%)
1k
FREQUENCY (Hz)
VDD = 5V
RL = 8Ω
0.01
100
FREQUENCY (Hz)
100
1
0.001
10
20Hz
1kHz
0.001
0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
1.0
1.2
0
0.2
0.4
0.6
0.8
OUTPUT POWER (W)
_______________________________________________________________________________________
7
MAX9796
Typical Operating Characteristics
Typical Operating Characteristics (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1µF. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.)
EFFICIENCY
vs. OUTPUT POWER
RL = 4Ω
40
30
60
50
RL = 4Ω
40
30
20
VDD = 3.3V
f = 1kHz
10
0
1
3
2
0
0
0.5
2.5
2.0
1.5
3.5
4.0
4.5
OUTPUT POWER
vs. LOAD
0.8
THD+N = 1%
0.6
3.0
THD+N = 10%
2.5
2.0
1.5
1.0
0
4.5
5.0
5.5
1
100
10
OUTPUT MAGNITUDE (dBV)
-40
-50
-60
-70
-80
-90
-100
20
FIXED-FREQUENCY MODULATION MODE
RL = 8Ω
VDD = 5V
f = 1kHz
UNWEIGHTED
VOUT = -60dBV
0
-20
-40
INBAND OUTPUT SPECTRUM
-60
-80
-100
100k
FIXED-FREQUENCY MODULATION MODE
RL = 8Ω
VDD = 5V
f = 1kHz
A-WEIGHTED
VOUT = -60dBV
0
-20
-40
-60
-80
-100
-140
-140
10k
20
-120
-120
-110
-120
100
10
LOAD (Ω)
INBAND OUTPUT SPECTRUM
MAX9796 toc16
VDD = 3.3V
VRIPPLE = 100mVP-P
RL = 8Ω
FREQUENCY (Hz)
0.6
LOAD (Ω)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
1k
THD+N = 10%
0.8
0
1
SUPPLY VOLTAGE (V)
100
1.0
THD+N = 1%
OUTPUT MAGNITUDE (dBV)
4.0
1.2
0.2
MAX9796 toc17
3.5
5.5
0.4
THD+N = 1%
0
3.0
VDD = 3.3V
f = 1kHz
1.4
0.5
0.2
5.0
1.6
OUTPUT POWER (W)
OUTPUT POWER (W)
1.0
VDD = 5V
f = 1kHz
3.5
MAX9796 toc14
4.0
MAX9796 toc13
1.2
10
3.0
OUTPUT POWER
vs. LOAD
0.4
8
1.0
OUTPUT POWER
vs. SUPPLY VOLTAGE
THD+N = 10%
0
-10
-20
-30
THD+N = 1%
SUPPLY VOLTAGE (V)
1.6
2.5
1.5
OUTPUT POWER (W)
RL = 8Ω
f = 1kHz
1.4
THD+N = 10%
2.0
OUTPUT POWER (W)
2.0
1.8
2.5
0.5
0
0
3.0
1.0
20
VDD = 5V
f = 1kHz
10
OUTPUT POWER (W)
70
RL = 4Ω
f = 1kHz
3.5
MAX9796 toc15
50
4.0
MAX9796 toc18
60
RL = 8Ω
80
EFFICIENCY (%)
EFFICIENCY (%)
70
90
OUTPUT POWER (W)
RL = 8Ω
80
100
MAX9796 toc11
90
MAX9796 toc10
100
OUTPUT POWER
vs. SUPPLY VOLTAGE
MAX9796 toc12
EFFICIENCY
vs. OUTPUT POWER
PSRR (dB)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
0
5k
10k
FREQUENCY (Hz)
15k
20k
0
5k
10k
FREQUENCY (Hz)
_______________________________________________________________________________________
15k
20k
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
-120
0
5k
10k
-40
-60
-80
-100
VDD = 5V
RL = 8Ω
INPUTS AC GROUNDED
-140
0
20k
15k
-20
-120
-140
-140
MAX9796 toc21
20
MAX9796 toc20
0
-120
5k
10k
20k
15k
FREQUENCY (Hz)
FREQUENCY (Hz)
WIDEBAND OUTPUT SPECTRUM
SPREAD-SPECTRUM MODE
TURN-ON RESPONSE
0.1
1
10
100
TURN-OFF RESPONSE
MAX9796 toc24
MAX9796 toc22
0
1000
FREQUENCY (MHz)
MAX9796 toc23
20
OUTPUT MAGNITUDE (dBV)
SPREAD-SPECTRUM MODULATION MODE
RL = 8Ω
VDD = 5V
f = 1kHz
A-WEIGHTED
VOUT = -60dBV
OUTPUT MAGNITUDE (dBV)
OUTPUT MAGNITUDE (dBV)
0
20
OUTPUT MAGNITUDE (dBV)
SPREAD-SPECTRUM MODULATION MODE
RL = 8Ω
VDD = 5V
f = 1kHz
UNWEIGHTED
VOUT = -60dBV
MAX9796 toc19
20
WIDEBAND OUTPUT SPECTRUM
FIXED-FREQUENCY MODE
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
SCL
2V/div
SCL
2V/div
SPEAKER
OUTPUT
200mA/div
SPEAKER
OUTPUT
200mA/div
-20
-40
-60
-80
-100
-120
VDD = 5V
RL = 8Ω
INPUTS AC GROUNDED
-140
0.1
1
10
1000
100
10ms/div
10ms/div
FREQUENCY (MHz)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
INPUTS AC GROUNDED
14
12
10
1
0.20
VDD = 5V
RL = 32Ω
0.1
THD+N (%)
SHUTDOWN CURRENT (μA)
INPUTS AC GROUNDED
MAX9796 toc26
0.25
MAX9796 toc25
16
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
0.15
0.10
POUT = 20mW
0.01
0.05
POUT = 40mW
8
8
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
MAX9796 toc27
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
MAX9796
Typical Operating Characteristics (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1µF. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.)
0.001
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1µF. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.)
VDD = 3.3V
RL = 16Ω
VDD = 3.3V
RL = 32Ω
100
VDD = 5V
RL = 32Ω
10
f = 1kHz
0.1
THD+N (%)
THD+N (%)
POUT = 40mW
THD+N (%)
0.1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
MAX9796 toc29
1
MAX9796 toc28
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX9796 toc30
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
POUT = 40mW
0.01
1
f = 10kHz
0.1
0.01
POUT = 20mW
0.01
POUT = 10mW
f = 20Hz
0.001
0.001
10
100
1k
10k
100k
0.001
10
100
1k
10k
100k
20
0
80
OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. COMMON-MODE VOLTAGE
VDD = 3.3V
RL = 32Ω
10
VDD = 3.3V
fIN = 1kHz
POUT = 30mW
GAIN = +3dB
RL = 32Ω
10
f = 1kHz
f = 10kHz
0.1
0.01
1
THD+N (%)
THD+N (%)
f = 1kHz
f = 10kHz
0.1
f = 20Hz
f = 20Hz
0.001
0.001
0.001
120
0
350
300
250
200
150
VDD = 5V
f = 1kHz
RL = 32Ω
POUT = POUTR + POUTL
100
50
OUTPUT POWER
vs. SUPPLY VOLTAGE
400
RL = 16Ω
350
300
250
200
RL = 32Ω
150
100
VDD = 3.3V
f = 1kHz
POUT = POUTR + POUTL
50
0
80
TOTAL OUTPUT POWER (mW)
120
2.5
65
60
THD+N = 10%
55
50
45
THD+N = 1%
40
35
RL = 32Ω
f = 1kHz
30
0
40
0
80
MAX9796 toc35
400
POWER DISSIPATION
vs. OUTPUT POWER
60
450
POWER DISSIPATION (mW)
450
0.5
1.0
1.5
2.0
COMMON-MODE VOLTAGE (V)
40
500
MAX9796 toc34
500
OUTPUT POWER (mW)
20
OUTPUT POWER (mW)
30
60
90
OUTPUT POWER (mW)
POWER DISSIPATION
vs. OUTPUT POWER
0
0.1
0.01
0.01
0
1
MAX9796 toc36
1
MAX9796 toc33
100
MAX9796 toc32
100
MAX9796 toc31
10
THD+N (%)
60
FREQUENCY (Hz)
VDD = 3.3V
RL = 16Ω
10
40
FREQUENCY (Hz)
100
POWER DISSIPATION (mW)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
0
40
80
120
TOTAL OUTPUT POWER (mW)
160
2.7
3.2
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
______________________________________________________________________________________
5.2
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
140
120
100
THD+N = 10%
60
140
120
100
40
THD+N = 10%
80
60
40
VDD = 5V
f = 1kHz
THD+N = 1%
40
THD+N = 1%
C1 = C2 = 0.68μF
0
100
1000
0
10
LOAD (Ω)
100
1000
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
-30
-40
-50
HPR
-60
-70
20
VDD = 3.3V
f = 1kHz
RL = 32Ω
0
OUTPUT MAGNITUDE (dBV)
VDD = 3.3V
VIN = 100mVP-P
RL = 32Ω
-20
1000
-20
-40
-60
-80
-100
-80
-90
-120
HPL
-140
-100
10
100
1k
10k
FREQUENCY (Hz)
0
100k
CROSSTALK (dB)
-40
-50
-60
-70
-80
-90
-100
-110
-120
RIGHT TO LEFT
LEFT TO RIGHT
10
100
1k
10k
FREQUENCY (Hz)
10k
15k
20k
CROSSTALK vs. INPUT AMPLITUDE
MAX9796 toc42
OUT_ = 1VP-P
RL = 32Ω
5k
FREQUENCY (Hz)
CROSSTALK vs. FREQUENCY
0
-10
-20
-30
CROSSTALK (dB)
100
LOAD RESISTANCE (Ω)
OUTPUT FREQUENCY SPECTRUM
MAX9796 toc40
POWER-SUPPLY REJECTION RATIO (dB)
0
-10
10
LOAD (Ω)
MAX9796 toc41
10
C1 = C2 = 1μF
20
20
0
C1 = C2 = 2.2μF
60
100k
0
-10
-20
-30
-40
-50
-60
MAX9796 toc43
20
VDD = 3.3V
f = 1kHz
THD+N = 1%
80
OUTPUT POWER (mW)
160
OUTPUT POWER (mW)
160
VDD = 3.3V
f = 1kHz
180
100
MAX9796 toc38
180
OUTPUT POWER (mW)
200
MAX9796 toc37
200
80
OUTPUT POWER vs. LOAD RESISTANCE
AND CHARGE-PUMP CAPACITOR SIZE
OUTPUT POWER
vs. LOAD
MAX9796 toc39
OUTPUT POWER
vs. LOAD
fIN = 1kHz
RL = 32Ω
GAIN = +3dB
RIGHT TO LEFT
-70
-80
-90
-100
-110
-120
LEFT TO RIGHT
0
0.4
0.8
INPUT AMPLITUDE (VRMS)
1.2
______________________________________________________________________________________
11
MAX9796
Typical Operating Characteristics (continued)
(VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain =
0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1µF. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.)
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
MAX9796
Pin Description
12
BUMP
NAME
A1
CPVDD
A2
C1P
A3
CPGND
A4
C1N
A5
CPVSS
FUNCTION
Charge-Pump Power Supply
Charge-Pump Flying Capacitor Positive Terminal
Charge-Pump GND
Charge-Pump Flying Capacitor Negative Terminal
Charge-Pump Output. Connect to VSS.
A6
HPL
Left Headphone Output
B1, F1, F5
PVDD
Class D Power Supply
B2, E6
I.C.
B3
VBIAS
Common-Mode Bias
B4
INC1
Input C1. Left input or positive input (see Table 5a).
Internal Connection. Leave unconnected. This pin is internally connected to the signal path. Do not
connect together or to any other pin.
B5
VSS
Headphone Amplifier Negative Power Supply. Connect to CPVSS.
B6
HPR
Right Headphone Output
C1, F4
OUT+
Positive Speaker Output
C2
SDA
C5
INC2
Serial Data Input. Connect a 1kΩ pullup resistor from SDA to VDD.
C6
OUTRx
Mono Receiver Output
D1, F3
PGND
Power Ground
D2
SCL
Serial Clock Input. Connect a 1kΩ pullup resistor from SCL to VDD.
D5
INB2
Input B2. Right input or negative input (see Table 5a).
Analog Power Supply
Input C2. Right input or negative input (see Table 5a).
D6
VDD
E1, F2
OUT-
Negative Speaker Output
E2
SHDN
Active-Low Hardware Shutdown
E3
INA1
Input A1. Left input or positive input (see Table 5a).
E4
INA2
Input A2. Right input or negative input (see Table 5a).
E5
INB1
Input B1. Left input or positive input (see Table 5a).
F6
GND
Analog Ground
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
VDD
VDD
C2
1μF
CPVSS
VSS
A5
B5
1μF
VDD
0.1μF
1μF
PVDD
D6
F1, B1, F5
C1N A4
10kΩ
CPGND A3
C1
1μF
C1P A2
VDD
CHARGE
PUMP
CPVDD A1
DirectDrive
C3
1μF
1μF
INA1
E3
INA2
E4
INPUT A: 0dB,
6dB, OR 20dB
3dB
1μF
1μF
INB1
E5
INB2
D5
LEFT
VOLUME
C5
3dB
B6 HPR
C6 OUTRx
12dB
MONO
VOLUME
B4
INC2
OUTPUT
MIXER
A6 HPL
INPUT
MIXER
INPUT B: 0dB
OR 6dB
1μF
1μF
INC1
3dB
RIGHT
VOLUME
C1, F4 OUT+
CLASS D
AMPLIFIER
INPUT C: 0dB
OR 6dB
E1, F2 OUT-
1μF
VBIAS
B3
1μF
SDA
SCL
SHDN
C2
MAX9796
D2
I2C CONTROL
E2
F6
GND
D1
PGND
F3
PGND
______________________________________________________________________________________
13
MAX9796
Typical Application Circuit
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Detailed Description
The MAX9796 ultra-low-EMI, filterless, Class D audio
power amplifier features several improvements to
switch-mode amplifier technology. The MAX9796 features active emissions limiting circuitry to reduce EMI.
Zero dead-time technology maintains state-of-the-art
efficiency and THD+N performance by allowing the
output FETs to switch simultaneously without crossconduction. A unique filterless modulation scheme and
a spread-spectrum modulation create a compact, flexible, low-noise, efficient audio power amplifier while
occupying minimal board space. The differential input
architecture reduces common-mode noise pickup with
or without the use of input-coupling capacitors. The
MAX9796 can also be configured as a single-ended
input amplifier without performance degradation.
The MAX9796 features three fully differential input pairs
(INA_, INB_, INC_) that can be configured as stereo
single-ended or mono differential inputs. I2C provides
control for input configuration, volume level, and mixer
configuration. DirectDrive allows the headphone and
mono receiver amplifiers to output ground-referenced
signals from a single supply, eliminating the need for
large DC-blocking capacitors. Comprehensive clickand-pop suppression minimizes audible transients during the turn-on and turn-off of amplifiers.
Class D Speaker Amplifier
Comparators monitor the audio inputs and compare the
complementary input voltages to a sawtooth waveform.
The comparators trip when the input magnitude of the
sawtooth exceeds their corresponding input voltage.
The active emissions limiting circuitry slightly reduces
the turn-on rate of the output H-bridge by slew-rate limiting the comparator output pulse. Both comparators
reset at a fixed time after the rising edge of the second
comparator trip point, generating a minimum-width
pulse (tON(MIN), 100ns typ) at the output of the second
comparator (Figure 1). As the input voltage increases
or decreases, the duration of the pulse at one output
increases while the other output pulse duration remains
the same. This causes the net voltage across the
speaker (VOUT+ - VOUT-) to change. The minimumwidth pulse helps the device to achieve high levels of
linearity.
tSW
VIN-
VIN+
OUT-
OUT+
tON(MIN)
VOUT+ - VOUT-
Figure 1. Outputs with an Input Signal Applied
14
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Fixed-Frequency Modulation
The MAX9796 features a fixed-frequency modulation
mode with a 1.1MHz switching frequency, set through
the I2C interface (Table 2). In fixed-frequency modulation mode, the frequency spectrum of the Class D output consists of the fundamental switching frequency
and its associated harmonics (see the Wideband
Output Spectrum Fixed-Frequency Mode graph in the
Typical Operating Characteristics).
Spread-Spectrum Modulation
The MAX9796 features a unique spread-spectrum
modulation that flattens the wideband spectral components. Proprietary techniques ensure that the cycle-to-
tSW
tSW
cycle variation of the switching period does not
degrade audio reproduction or efficiency (see the
Typical Operating Characteristics). Select the spreadspectrum modulation mode through the I2C interface
(Table 2). In spread-spectrum modulation mode, the
switching frequency varies randomly by ±30kHz
around the center frequency (1.16MHz). The modulation scheme remains the same, but the period of the
sawtooth waveform changes from cycle to cycle
(Figure 2). Instead of a large amount of spectral energy
present at multiples of the switching frequency, the
energy is now spread over a bandwidth that increases
with frequency. Above a few megahertz, the wideband
spectrum looks like white noise for EMI purposes (see
Figure 3).
tSW
tSW
VIN-
VIN+
OUT-
OUT+
tON(MIN)
VOUT+ - VOUT-
Figure 2. Output with an Input Signal Applied (Spread-Spectrum Modulation Mode)
______________________________________________________________________________________
15
MAX9796
Operating Modes
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
40
35
EN55022B LIMIT
AMPLITUDE (dBμV/m)
30
25
20
15
10
5
30
60
80
100
120
140
160
180
200
220
240
260
280
300
FREQUENCY (MHz)
Figure 3. EMI with 76mm of Speaker Cable
VIN = 0V
sumption, especially when idling. When no signal is present at the input of the MAX9796, the outputs switch as
shown in Figure 4. Because the MAX9796 drives the
speaker differentially, the two outputs cancel each other,
resulting in no net idle mode voltage across the speaker,
minimizing power consumption.
DirectDrive
OUT-
OUT+
VOUT+ - VOUT- = 0V
Figure 4. Outputs with No Input Signal
Filterless Modulation/Common-Mode Idle
The MAX9796 uses Maxim’s unique modulation scheme
that eliminates the LC filter required by traditional Class
D amplifiers, improving efficiency, reducing component
count, conserving board space and system cost.
Conventional Class D amplifiers output a 50% duty-cycle
square wave when no signal is present. With no filter, the
square wave appears across the load as a DC voltage,
resulting in finite load current, increasing power con16
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias from
the headphone. Without these capacitors, a significant
amount of DC current flows to the headphone, resulting
in unnecessary power dissipation and possible damage to both headphone and headphone amplifier.
Maxim’s DirectDrive architecture uses a charge
pump to create an internal negative supply voltage.
This allows the headphone outputs of the MAX9796 to
be biased at GND, almost doubling dynamic range
while operating from a single supply. With no DC
component, there is no need for the large DC-blocking capacitors. Instead of two large (220µF, typ) tantalum capacitors, the MAX9796 charge pump
requires two small ceramic capacitors, conserving
board space, reducing cost, and improving the frequency response of the headphone amplifier. See the
Output Power vs. Load Resistance and Charge-Pump
Capacitor Size graph in the Typical Operating
Characteristics for details of the possible capacitor
sizes. There is a low DC voltage on the driver outputs
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
VDD
VDD / 2
VOUT
GND
CONVENTIONAL DRIVER-BIASING SCHEME
+VDD
2) During an ESD strike, the driver’s ESD structures are
the only path to system ground. Thus, the amplifier
must be able to withstand the full ESD strike.
3) When using the headphone jack as a lineout to other
equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment,
resulting in possible damage to the amplifiers.
Charge Pump
The MAX9796 features a low-noise charge pump. The
switching frequency of the charge pump is half the
switching frequency of the Class D amplifier, regardless of the operating mode. The nominal switching frequency is well beyond the audio range, and thus does
not interfere with the audio signals, resulting in an SNR
of 93dB. Although not typically required, additional
high-frequency noise attenuation can be achieved by
increasing the size of C2 (see the Typical Application
Circuit). The charge pump is active in both speaker
and headphone modes.
Signal Path
The audio inputs of the MAX9796 (INA, INB, and INC)
are preamplified and then mixed by the input mixer to
create three internal signals: left (L), right (R), and mono
(M). Tables 5a and 5b show how the inputs are mixed to
create L, R, and M. These signals are then independently volume adjusted by the L, R, and M volume control
and routed to the output mixer. The output mixer mixes
the internal L, R, and M signals to create a variety of
audio mixes that are output to the headphone, speaker,
MAX9796
due to amplifier offset. However, the offset of the
MAX9796 is typically 1.4mV, which, when combined
with a 32Ω load, results in less than 44nA of DC current
flow to the headphones.
In addition to the cost and size disadvantages of the
DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier’s
low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return
(sleeve) to the DC bias voltage of the headphone
amplifiers. This method raises some issues:
1) The sleeve is typically grounded to the chassis.
Using the midrail biasing approach, the sleeve must
be isolated from system ground, complicating product design.
VOUT
GND
-VDD
DirectDrive BIASING SCHEME
Figure 5. Traditional Amplifier Output vs. MAX9796 DirectDrive
Output
and the mono receiver amplifiers. Figure 6 shows the
signal path that the audio signals take.
Signal amplification takes place in three stages. In the
first stage, the inputs (INA, INB, and INC) are preamplified. The amount by which each input is amplified is
determined by the bits INA+20dB (B4 in the Input Mode
Control Register) and IN+6dB (B3 in the Global Control
Register). After preamplification, they are mixed in the
input mixer to create the internal signals L, R and M.
In the second stage of amplification, the internal L, R,
and M signals are independently volume adjusted.
Finally, each output amplifier has its own internal gain.
The speaker, headphone, and mono receiver amplifiers
have fixed gains of 12dB, 3dB and 3dB, respectively.
______________________________________________________________________________________
17
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
-75dB TO 0dB
12dB
SPEAKER
RVOL
PREAMPLIFIER
-75dB TO 0dB
3dB
HEADPHONE
INPUT
MIXER
INPUT
OUTPUT
MIXER
LVOL
INPUT A:
0dB, 6dB, 20dB
INPUT B AND C:
0dB, 6dB
0dB OR 6dB
-75dB TO 0dB
3dB
RECEIVER
MONO
MONO+6dB
MVOL
Figure 6. Signal Path
Current-Limit and Thermal Protection
The MAX9796 features current limiting and thermal protection to protect the device from short circuits and
overcurrent conditions. The headphone amplifier pulses in the event of an overcurrent condition with a pulse
every 100µs as long as the condition is present. Should
the current still be high, the above cycle is repeated.
The speaker amplifier current-limit protection clamps
the output current without shutting down the output.
This can result in a distorted output. Current is limited
to 1.6A in the speaker amplifiers and 170mA in the
headphone and mono receiver amplifiers.
The MAX9796 has thermal protection that disables the
device at +150°C until the temperate decreases to
+120°C.
Click-and-Pop Suppression
In conventional single-supply headphone amplifiers,
the output-coupling capacitor is a major contributor of
audible clicks and pops. Upon startup, the amplifier
charges the coupling capacitor to its bias voltage, typically half the supply. Likewise, during shutdown, the
capacitor is discharged to GND. This results in a DC
shift across the capacitor, which in turn, appears as an
audible transient at the speaker. Since the MAX9796
18
headphone amplifier does not require output-coupling
capacitors, this problem does not arise.
In most applications, the output of the preamplifier driving the MAX9796 has a DC bias of typically half the
supply. During startup, the input-coupling capacitor is
charged to the preamplifier’s DC bias voltage, resulting
in a DC shift across the capacitor and an audible clickand-pop. An internal delay of 30ms eliminates the clickand-pop caused by the input filter.
Shutdown
The MAX9796 features a 0.1µA hard shutdown mode
that reduces power consumption to extend battery life
and a soft shutdown where current consumption is typically 8.5µA. Hard shutdown is controlled by connecting
SHDN to GND, disabling the amplifiers, bias circuitry,
charge pump, and I2C. In shutdown, the headphone
amplifier output impedance is 1.4kΩ and the speaker
output impedance is 300kΩ. Similarly, the MAX9796
enters soft shutdown when the SHDN bit = 0 (see Table
2). The I2C interface is active and the contents of the
command register are not affected when in soft shutdown. This allows the master to write to the MAX9796
while in shutdown. The I2C interface is completely disabled in hardware shutdown. When the MAX9796 is reenabled the default settings are applied (see Table 3).
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
MAX9796
SDA
tBUF
tSU, STA
tSU, DAT
tHD, STA
tHD, DAT
tLOW
tSP
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
REPEATED
START
CONDITION
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 7. 2-Wire Serial-Interface Timing Diagram
I2C Interface
The MAX9796 features an I2C 2-wire serial interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9796 and the master at clock rates up
to 400kHz. Figure 7 shows the 2-wire interface timing
diagram. The MAX9796 is a receive-only slave device
relying on the master to generate the SCL signal. The
master, typically a microcontroller, generates SCL and
initiates data transfer on the bus. The MAX9796 cannot
write to the SDA bus except to acknowledge the receipt
of data from the master. The MAX9796 does not
acknowledge a read command from the master.
A master device communicates to the MAX9796 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9796 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9796 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9796 from highvoltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
S
Sr
P
SCL
SDA
Figure 8. START, STOP, and REPEATED START Conditions
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
8). A START condition from the master signals the
beginning of a transmission to the MAX9796. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
______________________________________________________________________________________
19
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Early STOP Conditions
The MAX9796 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The MAX9796 is available with one preset slave
address (see Table 1). The address is defined as the
seven most significant bits (MSBs) followed by the
read/write (R/W) bit. The address is the first byte of
information sent to the MAX9796 after the START condition. The MAX9796 is a slave device only capable of
being written to. The R/W bit should be a zero when
configuring the MAX9796.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9796 uses to handshake receipt of each byte of
data (see Figure 9). The MAX9796 pulls down SDA during the master-generated 9th clock pulse. Monitoring
ACK allows for detection of unsuccessful data transfers.
An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master
may reattempt communications.
Write Data Format
A write to the MAX9796 includes transmission of a
START condition, the slave address with the R/W bit set
to 0 (Table 1), one byte of data to configure the
Command Register, and a STOP condition. Figure 10
illustrates the proper format for one frame.
The MAX9796 only accepts write data, but it acknowledges the receipt of the address byte with the R/W bit
set high. The MAX9796 does not write to the SDA bus
in the event that the R/W bit is set high. Subsequently,
the master reads all 1’s from the MAX9796. Always set
the R/W bit to zero to avoid this situation.
Programming the MAX9796
The MAX9796 is programmed through six control registers. Each register is addressed by the three MSBs
(B5–B7) followed by five configure bits (B0–B4) as
shown in Table 2. Correct programming of the MAX9796
requires writing to all six control registers. Upon poweron, their default settings are as listed in Table 3.
Table 1. MAX9796 Address Map
SLAVE ADDRESS
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
1
1
0
1
0
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
COMMAND BYTE IS STORED ON
RECEIPT OF STOP CONDITION
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9796
9
NOT ACKNOWLEDGE
S
SLAVE ADDRESS
0 ACK COMMAND BYTE
SDA
ACK P
ACKNOWLEDGE
FROM MAX9796
R/W
ACKNOWLEDGE
Figure 10. Write Data Format Example
Figure 9. Acknowledge
Table 2. Control Registers
FUNCTION
B7
B6
B5
B4
B3
COMMAND
B2
Input Mode Control
0
0
0
Mono Volume Control
0
0
1
MVOL (Table 7)
Left Volume Control
0
1
0
LVOL (Table 7)
Right Volume Control
0
1
1
Output Mode Control
1
0
0
MONO+6dB
Global Control Register
1
0
1
SHDN
20
B1
B0
DATA
INA+20dB
INMODE (Tables 5a and 5b)
RVOL (Table 7)
OUTMODE (Table 9)
IN+6dB
MUTE
______________________________________________________________________________________
SSM
MONO
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
MAX9796
Table 3. Power-On Reset Conditions
COMMAND
DATA
DESCRIPTION
Input Mode (000)
10000
Input A gain = +20dB; input A, B, and C singled-ended stereo inputs
Mono Volume (001)
11111
Maximum volume
Left Volume (010)
11111
Maximum volume
Right Volume (011)
11111
Maximum volume
Output Mode (100)
01000
Mode 8: stereo headphone, mono speaker
Global Control Register (101)
00011
Powered-off, input B/C gain = 0dB, MUTE off, SSM on, MONO on
Input Mode Control
The MAX9796 has three flexible inputs that can be configured as single-ended stereo inputs or differential
mono inputs. All input signals are summed into three
unique signals, Left (L), Right (R), and Mono (M), which
are routed to the output amplifiers. The bit B4 allows
the option of boosting low-level signals on INA. B4 can
be set as follows:
1 = Input A’s gain +20dB for low-level signals such as
FM receivers.
0 = Input A’s gain is either 0dB or +6dB as set by
IN+6dB (bit B3 of the Control Register).
Tables 5a and 5b show how the inputs–INA, INB, and
INC–are mixed to create the internal signals left (L),
right (R), and mono (M).
Table 4. Input Mode Control Register
Input Mode Control
B7
B6
B5
B4
B3
0
0
0
INA+20dB
B2
B1
B0
INMODE (Tables 5a and 5b )
Table 5a. Input Mode
PROGRAMMING MODE
INPUT CONFIGURATION
INMODE
INA1
INA2
INB1
INB2
INC1
INC2
0
L
R
L
R
L
R
0
1
L
R
L
R
M+
M-
1
0
L
R
M+
M-
L
R
0
1
1
L
R
M+
M-
M+
M-
0
1
0
0
L
R
R+
R-
L+
L-
0
1
0
1
L
R
L+
L-
R+
R-
0
1
1
0
M+
M-
L
R
L
R
0
1
1
1
M+
M-
L
R
M+
M-
1
0
0
0
M+
M-
M+
M-
L
R
1
0
0
1
M+
M-
M+
M-
M+
M-
1
0
1
0
M+
M-
R+
R-
L+
L-
1
0
1
1
M+
M-
L+
L-
R+
R-
B3
B2
B1
B0
0
0
0
0
0
0
0
0
______________________________________________________________________________________
21
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Table 5b. Internal Signals L, R, and M
PROGRAMMING MODE
B3
0
INMODE
B2
B1
0
0
INTERNAL SIGNALS LEFT (L), RIGHT (R), AND MONO (M)
B0
0
L
R
M
INA1 + INB1 + INC1
INA2 + INB2 + INC2
—
0
0
0
1
INA1 + INB1
INA2 + INB2
INC1 - INC2
0
0
1
0
INA1 + INC1
INA2 + INC2
INB1 - INB2
0
0
1
1
INA1
INA2
(INB1 - INB2) + (INC1 INC2)
0
1
0
0
INA1 + (INC1 - INC2)
INA2 + (INB1 - INB2)
—
0
1
0
1
INA1 + (INB1 - INB2)
INA2 + (INC1 - INC2)
—
0
1
1
0
INB1 + INC2
INB2 + INC2
INA1 - INA2
0
1
1
1
INB1
INB2
(INA1 - INA2) + (INC1 INC2)
1
0
0
0
INC1
INC2
(INA1 - INA2) + (INB1 INB2)
1
0
0
1
—
—
(INA1 - INA2) + (INB1 INB2)
1
0
1
0
INC1 - INC2
INB1 - INB2
INA1 - INA2
1
0
1
1
INB1 - INB2
INC1 - INC2
INA1 - INA2
Mono/Left/Right Volume Control
The MAX9796 has separate volume control for each of
the internal signals: left (L), right (R), and mono (M). The
final gain of each signal is determined by the way the
following bits are set: MVOL, LVOL, RVOL, INA+20dB,
IN+6dB, and MONO+6dB. Table 7 shows how to configure the L, R, and M amplifiers for specific gains.
Table 6. Mono/Left/Right Volume Control Registers
B7
B6
B5
Mono Volume Control
0
0
1
B4
B3
MVOL
B2
Left Volume Control
0
1
0
LVOL
Right Volume Control
0
1
1
RVOL
B1
B0
Table 7. Volume Control Settings
MVOL/LVOL/RVOL
22
GAIN (dB)
MVOL/LVOL/RVOL
GAIN (dB)
B4
B3
B2
B1
B0
Mute
0
1
0
0
0
-47
-75
0
1
0
0
1
-44
0
-71
0
1
0
1
0
-41
1
1
-67
0
1
0
1
1
-38
0
0
-63
0
1
1
0
0
-35
1
0
1
-59
0
1
1
0
1
-32
0
1
1
0
-55
0
1
1
1
0
-29
0
1
1
1
-51
0
1
1
1
1
-26
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
MVOL/LVOL/RVOL
MVOL/LVOL/RVOL
GAIN (dB)
GAIN (dB)
B4
B3
B2
B1
B0
-23
1
1
0
0
0
-7
-21
1
1
0
0
1
-6
0
-19
1
1
0
1
0
-5
1
-17
1
1
0
1
1
-4
0
0
-15
1
1
1
0
0
-3
1
0
1
-13
1
1
1
0
1
-2
1
1
0
-11
1
1
1
1
0
-1
1
1
1
-9
1
1
1
1
1
0
B4
B3
B2
B1
B0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
Output Mode Control
MONO+6dB in the Output Mode Control register allows
an extra 6dB of gain on the internal mono signal:
1 = Additional 6dB of gain is applied to the internal
Mono (M) signal path.
0 = No additional gain is applied to the Internal Mono
(M) signal path.
The MAX9796 has four output amplifiers: a mono
receiver amplifier, a stereo DirectDrive headphone
amplifier, and one mono Class D amplifier.
Table 8. Output Mode Control Register
Output Mode Control
B7
B6
B5
B4
1
0
0
Mono+6dB
Table 9 shows how each of the three internal signals,
left (L), right (R), and mono (M), are mixed and routed
B3
B2
B1
B0
OUTMODE (Table 9)
to the various outputs.
Table 9. Output Modes
MODE
OUTMODE
RECEIVER
LEFT HP
RIGHT HP
SPK
—
—
—
—
—
—
—
—
—
M
M
M
B3
B2
B1
B0
0
0
0
0
0
1
0
0
0
1
M
2
0
0
1
0
—
3
0
0
1
1
—
M
4
0
1
0
0
—
M
M
—
5
0
1
0
1
—
—
—
—
6
0
1
1
0
L+R
—
—
—
7
0
1
1
1
—
—
—
L+R
8
1
0
0
0
—
L
R
L+R
9
1
0
0
1
—
L
R
—
10
1
0
1
0
—
—
—
—
11
1
0
1
1
M+L+R
—
—
—
12
1
1
0
0
—
—
—
L+R+M
13
1
1
0
1
—
L+M
R+M
L+R+M
14
1
1
1
0
—
L+M
R+M
—
15
1
1
1
1
MUTE
MUTE
MUTE
MUTE
— = Amplifier off, R = Right signal
L = Left signal, M = Mono signal
______________________________________________________________________________________
23
MAX9796
Table 7. Volume Control Settings (continued)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Global Control Register
The Global Control Register is used for global configurations, those affecting all inputs and outputs. The bits
in the Control Register affect the inputs and outputs as
shown in Table 11.
Table 10. Global Control Register
Global Control Register
B7
B6
B5
B4
B3
B2
B1
B0
1
0
1
SHDN
IN+6dB
MUTE
SSM
MONO
Table 11. Global Control Register Configurations
BIT
NAME
B4
SHDN
B3
IN+6dB
B2
MUTE
B1
SSM
B0
MONO
FUNCTION
1 = Normal operation.
0 = Low-power shutdown mode. I2C settings are saved.
1 = All input signals are boosted by 6dB.
0 = All input signals are passed unamplified.
This bit does not affect INA if the INA+20dB bit (B4 of the Input Mode Control Register) is set to 1, in
which case INA is boosted by 20dB.
1 = Mute all outputs.
0 = All outputs are active.
1 = Spread-spectrum Class D modulation.
0 = Fixed-frequency Class D modulation.
1 = Speaker outputs L+R in modes 7, 8, 12, and 13 (see Table 9).
0 = Speaker outputs L in modes 7, 8, 12, and 13 (see Table 9).
Applications Information
Class D Filterless Operation
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s PWM output. The filters add cost, increase the solution size of
the amplifier, and can decrease efficiency. The traditional PWM scheme uses large differential output
swings (2 x VDD(P-P)) and causes large ripple currents.
Any parasitic resistance in the filter components results
in a loss of power, lowering the efficiency.
The MAX9796 does not require an output filter. The
device relies on the inherent inductance of the speaker
coil and the natural filtering of both the speaker and the
human ear to recover the audio component of the
square-wave output. Eliminating the output filter results
in a smaller, less costly, more efficient solution.
Because the switching frequency of the MAX9796
speaker output is well beyond the bandwidth of most
24
speakers, voice coil movement due to the square-wave
frequency is very small. Although this movement is
small, a speaker not designed to handle the additional
power may be damaged. For optimum results, use a
speaker with a series inductance >10µH. Typical 8Ω
speakers, for portable audio applications, exhibit series
inductances in the range of 20µH to 100µH.
Input Amplifier
Differential Input
The MAX9796 features a programmable differential
input structure, making it compatible with many
CODECs, and offering improved noise immunity over a
single-ended input amplifier. In devices such as cellular phones, high-frequency signals from the RF transmitter can be picked up by the amplifier’s input traces.
The signals appear at the amplifier’s inputs as common-mode noise. A differential input amplifier amplifies
the difference of the two inputs and any signal common
to both is cancelled.
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
DC-Coupled Input
The input amplifier can accept DC-coupled inputs that
are biased to the amplifier’s bias voltage. DC-coupling
eliminates the input-coupling capacitors; reducing component count to potentially six external components (see
the Typical Application Circuit). However, the highpass
filtering effect of the capacitors is lost, allowing low-frequency signals to feed through to the load.
Unused Inputs
Connect any unused input directly to VBIAS. This saves
input capacitors on unused inputs and provides the
highest noise immunity on the input.
Component Selection
Input Filter
An input capacitor (CIN) in conjunction with the input
impedance of the MAX9796 forms a highpass filter that
removes the DC bias from the incoming signal. The ACcoupling capacitor allows the amplifier to automatically
bias the signal to an optimum DC level. Assuming zero
source impedance, the -3dB point of the highpass filter
is given by:
f−3dB =
1
2πRINCIN
Choose CIN so that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics
have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased
distortion at low frequencies.
Other considerations when designing the input filter
include the constraints of the overall system and the
actual frequency band of interest. Although high-fidelity
audio calls for a flat-gain response between 20Hz and
20kHz, portable voice-reproduction devices, such as
cell phones and two-way radios, need only concentrate
on the frequency range of the spoken human voice
(typically 300Hz to 3.5kHz). In addition, speakers used
in portable devices typically have a poor response
below 300Hz. Taking these two factors into consideration, the input filter may not need to be designed for a
20Hz to 20kHz response, saving both board space and
cost due to the use of smaller capacitors.
Class D Output Filter
The MAX9796 does not require a Class D output filter.
The device passes EN55022B emissions standards
with 152mm of unshielded speaker cables. However,
output filtering can be used if a design is failing radiated emissions due to board layout or cable length, or
the circuit is near EMI-sensitive devices. Use a ferrite
bead filter when radiated frequencies above 10MHz
are of concern. Use an LC filter when radiated frequencies below 10MHz are of concern, or when long leads
(>152mm) connect the amplifier to the speaker. Figure
11 shows optional speaker amplifier output filters.
External Component Selection
BIAS Capacitor
VBIAS is the output of the internally generated DC bias
voltage. The VBIAS bypass capacitor, CVBIAS improves
PSRR and THD+N by reducing power supply and other
noise sources at the common-mode bias node, and
also generates the clickless/popless, startup/shutdown
DC bias waveforms for the speaker amplifiers. Bypass
VBIAS with a 1µF capacitor to GND.
22Ω
0.033μF
0.1μF
33μH
OUT_+
0.47μF
OUT_33μH
0.033μF
0.1μF
22Ω
Figure 11. Speaker Amplifier Output Filter
______________________________________________________________________________________
25
MAX9796
Single-Ended Input
The MAX9796 can be configured as a single-ended
input amplifier by appropriately configuring the Input
Control Register (see Tables 5a and 5b).
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩ for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most
surface-mount ceramic capacitors satisfy the ESR
requirement. For best performance over the extended
temperature range, select capacitors with an X7R dielectric or better. Table 12 lists suggested manufacturers.
Flying Capacitor (C1)
The value of the flying capacitor (C1) affects the output
resistance of the charge pump. A C1 value that is too
small degrades the device’s ability to provide sufficient
current drive, which leads to a loss of output voltage.
Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1µF, the on-resistance
of the switches and the ESR of C1 and C2 dominate.
Output Capacitor (C2)
The output capacitor value and ESR directly affect the
ripple at CPVSS. Increasing the value of C2 reduces
output ripple. Likewise, decreasing the ESR of C2
reduces both ripple and output resistance. Lower
capacitance values can be used in systems with low
maximum output power levels. See the Output Power
vs. Load Resistance and Charge-Pump Capacitor Size
graph in the Typical Operating Characteristics.
CPVDD Bypass Capacitor (C3)
The CPVDD bypass capacitor (C3) lowers the output
impedance of the power supply and reduces the
impact of the MAX9796’s charge-pump switching transients. Bypass CPVDD with C3 to PGND and place it
physically close to the CPVDD and PGND. Use a value
for C3 that is equal to C1.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Connect all of the power-supply inputs (CPVDD, VDD,
and PVDD) together. Bypass CPVDD with a 1µF capacitor to CPGND. Bypass VDD with a 1µF capacitor to
GND. Bypass PVDD with a 1µF capacitor in parallel with
a 0.1µF capacitor to PGND. Place the bypass capacitors as close as possible to the MAX9796. Place a bulk
capacitor between PVDD and PGND, if needed.
Use large, low-resistance output traces. Current drawn
from the outputs increase as load impedance decreases. High output trace resistance decreases the power
delivered to the load. Large output, supply, and GND
traces allow more heat to move from the MAX9796 to the
PCB, decreasing the thermal impedance of the circuit.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature profile, as well as the latest information of reliability
testing results, refer to Application Note: UCSP—A
Wafer-Level Chip-Scale Package available on Maxim’s
website at www.maxim-ic.com/ucsp.
UCSP Thermal Consideration
When operating at maximum output power, the UCSP
thermal dissipation can become a limiting factor. The
UCSP package does not dissipate heat as efficiently as
packages with a thermal pad. As a result, in some
applications, the thermal performance of the package
may limit performance.
Table 12. Suggested Capacitor Manufacturers
PHONE
FAX
Taiyo Yuden
SUPPLIER
800-348-2496
847-925-0899
www.t-yuden.com
WEBSITE
TDK
847-803-6100
847-390-4405
www.component.tdk.com
Chip Information
PROCESS: BiCMOS
26
______________________________________________________________________________________
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
36L,UCSP.EPS
PACKAGE OUTLINE, 6x6 UCSP
21-0082
K
1
1
______________________________________________________________________________________
27
MAX9796
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX9796
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/07
Initial release
—
1
1/08
Updated Typical Application Circuit
13
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.
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