EE87C196MC

8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MC 16 Kbytes of On-Chip OTPROM* 87C196MC, ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM 80C196MC ROMless Y High-Performance CHMOS 16-Bit CPU Y 16 Kbytes of On-Chip OTPROM/ Factory-Programmed OTPROM Y 488 bytes of On-Chip Register RAM Y Register to Register Architecture Y Up to 53 I/O Lines Y Peripheral Transaction Server (PTS) with 11 Prioritized Sources Y Y Event Processor Array (EPA) Ð 4 High Speed Capture/Compare Modules Ð 4 High Speed Compare Modules Y Two 16-Bit Timers with Quadrature Decoder Input Y 3-Phase Complementary Waveform Generator Y 13 Channel 8/10-Bit A/D with Sample/ Hold with Zero Offset Adjustment H/W Y 14 Prioritized Interrupt Sources Y Flexible 8-/16-Bit External Bus Y 1.75 ms 16 x 16 Multiply Y 3 ms 32/16 Divide Y Idle and Power Down Modes Extended Temperature Standard The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brushless motors. The 8XC196MC is based on Intel’s MCSÉ 96 16-bit microcontroller architecture and is manufactured with Intel’s CHMOS process. The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor control applications. This peripheral allows for pulse width modulation, three phase sine wave generation with minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses with resolutions of 0.125 ms (edge trigger) or 0.250 ms (centered). The 8XC196MC has 16 Kbytes on-chip OTPROM/ROM and 488 bytes of on-chip RAM. It is available in three packages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L). Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins. Operational characteristics are guaranteed over the temperature range of b 40§ C to a 85§ C. The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83C196MC contains 16 Kbytes on-chip ROM. All references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted. *OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package and cannot be erased. It is user programmable. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1995 April 1994 Order Number: 270946-005 8XC196MC 270946 – 1 NOTE: Connections between the standard I/O ports and the bus are not shown. Figure 1. 87C196MC Block Diagram 2 8XC196MC 8XC196MC Memory Map PROCESS INFORMATION This device is manufactured on PX29.5, a CHMOS III-E process. Additional process and reliability information is available in the Intel® Quality System Handbook. 270946 – 16 EXAMPLE: N87C196MC is 84-Lead PLCC OTPROM, 16 MHz. For complete package dimensional data, refer to the Intel Packaging Handbook (Order Number 240800). NOTE: 1. EPROMs are available as One Time Programmable (OTPROM) only. Figure 3. The 8XC196MC Family Nomenclature Thermal Characteristics Package Type ija ijc PLCC 35§ C/W 13§ C/W QFP 56§ C/W 12§ C/W SDIP TBD TBD All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology. Description External Memory or I/O Address 0FFFFH 06000H Internal ROM/EPROM or External Memory (Determined by EA) 5FFFH 2080H Reserved. Must contain FFH. (Note 5) 207FH 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM/EPROM Security Key 202FH 2020H Reserved. Must contain FFH. (Note 5) 201FH 201CH Reserved. Must Contain 20H (Note 5) 201BH CCB1 201AH Reserved. Must Contain 20H (Note 5) 2019H CCB0 2018H Reserved. Must contain FFH. (Note 5) 2017H 2014H Lower Interrupt Vectors 2013H 2000H SFR’s 1FFFH 1F00H External Memory 1EFFH 0200H 488 Bytes Register RAM (Note 1) 01FFH 0018H CPU SFR’s (Notes 1, 3) 0017H 0000H NOTES: 1. Code executed in locations 0000H to 03FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196KC for SFR descriptions. 5. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly. 3 8XC196MC 270946 – 2 NOTE: *The pin sequence is correct. The 64-Lead SDIP package does not include the following pins: P1.4/ACH12, P2.7/COMPARE3, P5.1/INST, CLKOUT. Figure 2. 64-Lead Shrink DIP (SDIP) Package 4 8XC196MC 270946 – 3 NOTE: NC means No Connect. Do not connect these pins. Figure 3. 84-Lead PLCC Package 5 8XC196MC 270946 – 4 NOTE: NC means No Connect. Do not connect these pins. Figure 4. 80-Lead Shrink EIAJQFP (Quad Flat Pack) 6 8XC196MC PIN DESCRIPTIONS (Alphabetically Ordered) Symbol ACH0–ACH12 (P0.0–P0.7, P1.0–P1.4) ANGND ALE/ADV(P5.0) BHE/WRH (P5.5) BUSWIDTH (P5.7) CAPCOMP0–CAPCOMP3 (P2.0–P2.3) CLKOUT COMPARE0–COMPARE3 (P2.4–P2.7) EA EXTINT INST (P5.1) NMI PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 Function Analog inputs to the on-chip A/D converter. ACH0 – 7 share the input pins with P0.0–7 and ACH8 – 12 share pins with P1.0 – 4. If the A/D is not used, the port pins can be used as standard input ports. Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. Address Latch Enable or Address Valid output, as selected by CCR. Both options allow a latch to demultiplex the address/data bus on the signal’s falling edge. When the pin is ADV, it goes inactive (high) at the end of the bus cycle. ALE/ADV is active only during external memory accesses. Can be used as standard I/O when not used as ALE/ADV. Byte High Enable or Write High output, as selected by the CCR. BHE will go low for external writes to the high byte of the data bus. WRH will go low for external writes where an odd byte is being written. BHE/WRH is activated only during external memory writes. Input for bus width selection. If CCR bits 1 and 2 e 1, this pin dynamically controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as standard I/O when not used as BUSWIDTH. The EPA Capture/Compare pins. These pins share P2.0 – P2.3. If not used for the EPA, they can be configured as standard I/O pins. Output of the internal clock generator. The frequency is (/2 of the oscillator frequency. It has a 50% duty cycle. The EPA Compare pins. These pins share P2.4 – P2.7. If not used for the EPA, they can be configured as standard I/O pins. External Access enable pin. EA e 0 causes all memory accesses to be external to the chip. EA e 1 causes memory accesses from location 2000H to 5FFFH to be from the on-chip OTPROM/QROM. EA e 12.5V causes execution to begin in the programming mode. EA is latched at reset. A programmable input on this pin causes a maskable interrupt vector through memory location 203CH. The input may be selected to be a positive/negative edge or a high/low level using WGÐPROTECT (1FCEH). INST is high during the instruction fetch from the external memory and throughout the bus cycle. It is low otherwise. This pin can be configured as standard I/O if not used as INST. A positive transition on this pin causes a non-maskable interrupt which vectors to memory location 203EH. If not used, it should be tied to VSS. May be used by Intel Evaluation boards. 8-bit high impedance input-only port. Also used as A/D converter inputs. Port0 pins should not be left floating. These pins also used to select programming modes in the OTPROM devices. 5-bit high impedance input-only port. P1.0 – P1.4 are also used as A/D converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock input and direction select respectively. 8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O pins (CAPCOMP0 – 3 and COMPARE0 – 3). 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which uses strong internal pullups. 8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals (ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard I/O. 7 8XC196MC PIN DESCRIPTIONS Symbol PORT6 PWM0, PWM1 (P6.6, P6.7) RD (P5.3) READY (P5.6) RESET T1CLK (P1.2) T1DIR (P1.3) VPP WG1–WG3/WG1 –WG3 (P6.0–P6.5) WR/WRL (P5.2) XTAL1 XTAL2 PMODE (P0.4–7) PACT (P2.5) PALE (P2.1) PROG (P2.2) PVER (P2.0) CPVER (P2.6) AINC (P2.4) 8 (Alphabetically Ordered) (Continued) Function 8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave Form Generator outputs. Can be used as standard output ports. Programmable duty cycle, Programmable frequency Pulse Width Modulator pins. The duty cycle has a resolution of 256 steps, and the frequency can vary from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as standard output if PWM is not used. Read signal output to external memory. RD is low only during external memory reads. Can be used as standard I/O when not used as RD. Ready input to lengthen external memory cycles. If READY e 0, the memory controller inserts wait states until the next positive transition of CLKOUT occurs with READY e 1. Can be used as standard I/O when not used as READY. Reset input to and open-drain output from the chip. Held low for at least 16 state times to reset the chip. Input high for normal operation. RESET has an Ohmic internal pullup resistor. Timer 0 Clock input. This pin has two other alternate functions: ACH10 and P1.2. Timer 0 Direction input. This pin has two other alternate functions: ACH11 and P1.3. The programming voltage is applied to this pin. It is also the timing pin for the return from Power Down circuit. Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC. If the Power Down feature is not used, connect the pin to VCC. 3 phase output signals and their complements used in motor control applications. The pins can also be configured as standard output pins. Write and Write Low output to external memory. WR will go low every external write. WRL will go low only for external writes to an even byte. Can be used as standard I/O when not used as WR/WRL. Input of the oscillator inverter and the internal clock generator. This pin should be used when using an external clock source. Output of the oscillator inverter. Determines the EPROM programming mode. A low signal in Auto Programming mode indicates that programming is in process. A high signal indicates programming is complete. A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address/command information (input to slave). A falling edge in Slave Programming Mode begins programming. A rising edge ends programming. A high signal in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly. Cumulative Program Verification. Pin is high if all locations since entering a programming mode have programmed correctly. Auto Increment. Active low input enables the auto increment mode. Auto increment will allow reading or writing of sequential EPROM locations without address transactions across the PBUS for each read or write. 8XC196MC ABSOLUTE MAXIMUM RATINGS NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. Ambient Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage from EA or VPP to VSS or ANGNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ a 13.00V Voltage on VPP or EQ to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to 13.0V Voltage on Any Other Pin to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V(1) *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W(2) NOTES: 1. This includes VPP and EA on ROM or CPU only devices. 2. Power dissipation is based on package heat transfer limitations, not device power consumption. OPERATING CONDITIONS Description Min Max Units TA Symbol Ambient Temperature Under Bias b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V FOSC Oscillator Frequency 8 16 MHz NOTE: ANGND and VSS should be nominally at the same potential. Also VSS and VSS1 must be at the same potential. DC ELECTRICAL CHARACTERISTICS Symbol Parameter (Over Specified Operating Conditions) Min Max Units VIL Input Low Voltage b 0.5 0.3 VCC V Test Conditions VIH Input High Voltage 0.7 VCC VCC a 0.5 V VOL Output Low Voltage Port 2 and 5, P6.6, P6.7, CLKOUT 0.3 0.45 1.5 V V V IOL e 200 mA IOL e 3.2 mA IOL e 7 mA VOL1 Output Low Voltage on Port 3/4 1.0 V IOL e 15 mA VOL2 Output Low Voltage on Port 6.0–6.5 0.45 V IOL e 10 mA VOH Output High Voltage VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA Vth a –Vthb Hysteresis Voltage Width on RESET 0.2 V Typical 9 8XC196MC DC ELECTRICAL CHARACTERISTICS Symbol Parameter ILI Input Leakage Current on All Input Only Pins ILI1 (Over Specified Operating Conditions) (Continued) Min Typ Max Units Test Conditions g 10 mA 0V k VIN k VCC – 0.3V (in RESET) Input Leakage Current on Port0 and Port1 g3 mA 0V k VIN k VREF IIL Input Low Current on BD Ports (Note 1) b 70 mA VIN e 0.3 VCC IIL1 Input Low Current on P5.4 and P2.6 during Reset b7 mA 0.2 VCC IOH Output High Current on P5.4 and P2.6 during Reset mA 0.7 VCC ICC Active Mode Current in Reset 70 mA IREF A/D Conversion Reference Current 2 5 mA XTAL1 e 16 MHz, VCC e VPP e VREF e 5.5V IIDL Idle Mode Current 15 30 mA IPD Power-Down Mode Current RRST RESET Pin Pullup Resistor CS Pin Capacitance (Any Pin to VSS) b2 50 5 6k 50 mA 65k X 10 pF NOTES: 1. BD (Bidirectional ports) include: P2.0 – P2.7, except P2.6 P3.0 – P3.7 P4.0 – P4.7 P5.0 – P5.3 P5.5 – P5.7 2. During normal (non-transient) conditions, the following total current limits apply: P6.0 – P6.5 IOL: 40 mA IOH: 28 mA P3 IOL: 90 mA IOH: 42 mA P4 IOL: 90 mA IOH: 42 mA P5, CLKOUT IOL: 35 mA IOH: 35 mA P2, P6.6, P6.7 IOL: 63 mA IOH: 63 mA 10 VCC e VPP e VREF e 5.5V FTEST e 1.0 MHz 8XC196MC EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: Signals: H Ð High A Ð Address L Ð Low V Ð Valid B Ð BHE C Ð CLKOUT X Z D Ð DATA G Ð Buswidth Ð No Longer Valid Ð Floating L Ð ALE/ADV BR Ð BREQ R Ð RD W Ð WR/WRH/WRL X H Ð HOLD Ð XTAL1 Y Ð READY Q Ð Data Out HA Ð HLDA AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. The system must meet the following specifications to work with the 87C196MC: Symbol Parameter FXTAL Frequency on XTAL1 TOSC 1/FXTAL TAVYV Address Valid to READY Setup TLLYV ALE Low to READY Setup TYLYH Not READY Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVGV Address Valid to BUSWIDTH Setup TLLGV ALE Low to BUSWIDTH Setup TCLGX Buswidth Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid TRLDV Min Max Units Notes 8 16 MHz 3 62.5 125 ns 2 TOSC b 75 ns TOSC b 70 ns No Upper Limit 4 ns 0 TOSC b 30 ns 1 TOSC b 15 2 TOSC b 40 ns 1 2 TOSC b 75 ns TOSC b 60 0 ns 4 ns 3 TOSC b 55 ns 2 RD Active to Input Data Valid TOSC b 22 ns 2 TCLDV CLKOUT Low to Input Data Valid TOSC b 50 ns TRHDZ End of RD to Input Data Float TOSC ns TRXDX Data Hold after RD Inactive 0 ns NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC * N, where N e number of wait states. 3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz. 4. These timings are included for compatibility with older b90 and BH products. They should not be used for newer highspeed designs. 11 8XC196MC AC ELECTRICAL CHARACTERISTICS (Continued) Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz. The 87C196MC will meet the following timing specifications: Symbol Parameter Min 30 Max Units 110 ns TXHCH XTAL1 to CLKOUT High or Low TCLCL CLKOUT Cycle Time TCHCL CLKOUT High Period TOSC b 10 TOSC a 15 ns TCLLH CLKOUT Falling Edge to ALE Rising b5 15 ns TLLCH ALE Falling Edge to CLKOUT Rising b 20 15 ns TLHLH ALE Cycle Time 2 TOSC ns 4 TOSC ns TLHLL ALE High Period TOSC b 10 TAVLL Address Setup to ALE Falling Edge TOSC b 15 ns TLLAX Address Hold after ALE Falling TOSC b 40 ns TLLRL ALE Falling Edge to RD Falling TOSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge TRLRH RD Low Period TRHLH RD Rising Edge to ALE Rising Edge TRLAZ RD Low to Address Float TLLWL ALE Falling Edge to WR Falling TCLWL CLKOUT Low to WR Falling Edge TQVWH Data Stable to WR Rising Edge TCHWH CLKOUT High to WR Rising Edge TOSC a 10 3 ns 4 30 ns TOSC b 5 TOSC a 25 ns 3 TOSC TOSC a 25 ns 1 5 ns TOSC b 10 0 ns 25 TOSC b 23 b 10 ns ns 15 ns TWLWH WR Low Period TOSC b 30 TWHQX Data Hold after WR Rising Edge TOSC b 25 TWHLH WR Rising Edge to ALE Rising Edge TOSC b 10 TWHBX BHE, INST Hold after WR Rising TOSC b 10 ns TWHAX AD8–15 Hold after WR Rising TOSC b 30 ns TRHBX BHE, INST Hold after RD Rising TOSC b 10 ns TRHAX AD8–15 Hold after RD Rising TOSC b 30 ns NOTES: 1. Assuming back to back cycles. 2. 8-bit bus only. 3. If wait states are used, add 2 TOSC*N, where N e number of wait states. 12 Notes TOSC a 15 ns ns ns 3 1 2 2 8XC196MC SYSTEM BUS TIMINGS 270946 – 5 13 8XC196MC READY TIMINGS (One Wait State) 270946 – 6 BUSWIDTH TIMINGS 270946 – 7 14 8XC196MC EXTERNAL CLOCK DRIVE Symbol Parameter 1/TXLXL Oscillator Frequency TXLXL Oscillator Period TXHXX High Time 22 ns TXLXX Low Time 22 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CRYSTAL CONNECTIONS Min Max Units 8 16.0 MHz 62.5 125 ns EXTERNAL CLOCK CONNECTIONS 270946 – 14 NOTE: Keep oscillator components close to chip and use short, direct traces to XTAL1, XTAL2 and VSS. When using crystals, C1 e 20 pF, C2 e 20 pF. When using ceramic resonators, consult manufacturer for recommended circuitry. 270946 – 15 * Required if TTL driver used. Not needed if CMOS driver is used. EXTERNAL CLOCK DRIVE WAVEFORMS 270946 – 8 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF. AC TESTING INPUT, OUTPUT WAVEFORMS 270946 – 9 AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. FLOAT WAVEFORMS 270946 – 10 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded VOH/VOL Level occurs IOL/IOH e s g 15 mA. 15 8XC196MC A TO D CHARACTERISTICS The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed by loading a byte into the ADÐTIME Special Function Register. This allows optimizing the A/D operation for specific applications. The ADÐTIME register is functional for all possible values, but the accuracy of the A/D converter is only guaranteed for the times specificed in the operating conditions table. The value loaded into ADÐTIME bits 5, 6, 7 determines the sample time, TSAM, and is calculated using the following formula: SAM e (TSAM c FOSC) b 2 8 TSAM e Sample time, ms FOSC e Processor frequency, MHz SAM e Value loaded into ADÐTIME bits 5, 6, 7 SAM must be in the range 1 through 7. The value loaded into ADÐTIME bits 0–5 determines the conversion time, TCONV, and is calculated using the following formula: CONV e 16 (TCONV c FOSC) b 3 b1 2B TCONV e Conversion time, ms FOSC e Processor frequency, MHz B e 8 for 8-bit conversion B e 10 for 10-bit conversion CONV e Value loaded into ADÐTIME bits 0 – 5 CONV must be in the range 2 through 31. The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. VREF must be close to VCC since it supplies both the resistor ladder and the analog portion of the converter and input port pins. There is also an ADÐTEST SFR that allows for conversion on ANGND and VREF as well as adjusting the zero offset. The absolute error listed is WITHOUT doing any adjustments. A/D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet. Testing is performed with VREF e 5.12V and 16.0 MHz operating frequency. After a conversion is started, the device is placed in the IDLE mode until the conversion is complete. 8XC196MC 10-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time 10.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz ms(2) NOTES: ANGND and VSS should nominally be at the same potential. 1. VREF must be within 0.5V of VCC. 2. The value of ADÐTIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS Parameter Typical(1) Resolution Absolute Error Full Scale Error 0.25 g 0.5 Zero Offset Error 0.25 g 0.5 Non-Linearity 1.0 g 2.0 Differential Non-Linearity (Over Specified Operating Conditions) Min Max Units* 1024 10 1024 10 Levels Bits 0 g4 LSBs LSBs LSBs g4 LSBs l b1 a2 LSBs g 0.1 0 g 1.0 LSBs Repeatability g 0.25 0 Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 Channel-to-Channel Matching Off Isolation Feedthrough VCC Power Supply Rejection b 60 Input Series Resistance Voltage on Analog Input Pin DC Input Leakage LSB/C LSB/C LSB/C dB(2, 3) b 60 b 60 Sampling Capacitor LSBs dB(2) dB(2) 750 2K X(4) ANGND b 0.5 VREF a 0.5 V(5, 6) 3 g1 pF 0 g 3.0 mA NOTES: *An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 17 8XC196MC 8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature b 40 a 85 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.00 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time 7.0 20.0 ms(2) FOSC Oscillator Frequency 8.0 16.0 MHz ms(2) NOTES: ANGND and VSS should nominally be at the same potential. 1. VREF must be within 0.5V of VCC. 2. The value of ADÐTIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS Parameter Typical(1) Resolution Absolute Error Full Scale Error g 0.5 Zero Offset Error g 0.5 Non-Linearity Differential Non-Linearity Channel-to-Channel Matching (Over the Above Operating Conditions) Min Max Units* 256 8 256 8 Level Bits 0 g1 LSBs LSBs LSBs 0 g1 LSBs l b1 a1 LSBs 0 g 1.0 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 LSB/C LSB/C LSB/C Off Isolation Feedthrough VCC Power Supply Rejection b 60 Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage dB(2, 3) b 60 b 60 dB(2) dB(2) 750 2K X(4) VSS b 0.5 VREF a 0.5 V(5, 6) 3 g1 pF 0 g 3.0 mA NOTES: *An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook for A/D glossary of terms). 1. These values are expected for most parts at 25§ C but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer Break-Before-Make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. These values may be exceeded if the pin current is limited to g 2 mA. 6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions performed with processor in IDLE mode. 18 8XC196MC EPROM SPECIFICATIONS OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature during Programming 20 30 §C VCC Supply Voltage during Programming 4.5 5.5 V(1) VREF Reference Supply Voltage during Programming 4.5 5.5 V(1) VPP Programming Voltage 12.25 12.75 V(2) VEA EA Pin Voltage 12.25 12.75 V(2) FOSC Oscillator Frequency during Auto and Slave Mode Programming 6.0 8.0 MHz TOSC Oscillator Frequency during Run-Time Programming 6.0 12.0 MHz NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max 1100 Units TSHLL Reset High to First PALE Low TOSC TLLLH PALE Pulse Width 50 TOSC TAVLL Address Setup Time 0 TOSC TLLAX Address Hold Time 100 TPLDV PROG Low to Word Dump Valid TPHDX Word Dump Data Hold TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(1) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low TILIH AINC Pulse Width TILVH TILPL TPHVL PROG High to PVER Valid TOSC 50 50 TOSC TOSC 0 TOSC 240 TOSC PVER Hold after AINC Low 50 TOSC AINC Low to PROG Low 170 TOSC 220 TOSC NOTE: 1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. 19 8XC196MC DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Supply Current (When Programming) Min Max Units 100 mA NOTE: Do not apply VPP until VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 2709461 – 11 NOTE: P3.0 must be high (‘‘1’’) 20 8XC196MC SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 270946 – 12 NOTE: P3.0 must be low (‘‘0’’) SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 270946 – 13 21 8XC196MC 87C196MC DESIGN CONSIDERATIONS When an indirect shift during divide occurs the upper 3 bits of the shift count are not masked completely. If the shift count register has the value 32*n where n e 1, 3, 5 or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. DATA SHEET REVISION HISTORY This data sheet (270946-004) is valid for devices with a ‘‘B’’ at the end of the topside tracking number. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. The following important differences exist between this data sheet (270946-002) and the previous version (270946-003): 1. The data sheet was reorganized to standard format. 2. Added 83C196MC device. 3. Added package thermal characteristics. 4. Added note on missing pins on SDIP package. 5. Removed SFR maps (now in user’s manual). 6. Added note on TLLYV and TLLGV specifications. 7. Changed 10-bit mode TCONV (MIN) to 10.0 ms from 15.0 ms. 8. Changed 10-bit mode TCONV (MAX) to 20.0 ms from 18.0 ms. 9. Changed VREF (MIN) in 8- and 10-bit mode to 4.0V from 4.5V. The following important differences exist between data sheet 270946-003 and the previous version (270946-002): 1. The data sheet title was changed to better reflect the purpose of the 87C196MC as an AC Inverter/ DC Brushless Motor Control Microcontroller. 2. The standard temperature range for this part now covers b 40§ C to a 85§ C. 22 3. EXTINT function description now includes WGÐPROTECT (1FCEH) as the name and address of the register used to select positive/negative or high/low detection for EXTINT. 4. The memory range 01F00H – 01FBFH was added to the SFR map as RESERVED. 5. IIL changed from b 60 mA to b 70 mA. 6. IREF changed from 5 mA to 2 mA maximum and the typical specification was removed. 7. The READY description of the READY TIMINGS (One Wait State) graphic was modified to denote the shifting of the leading edge of READY versus frequency. At 16 MHz the falling edge of READY occurs before the falling edge of ALE. 8. AC Testing Input, Output Waveform was changed to reflect inputs driven at 3.5V for a Logic ‘‘1’’ and .45V for a Logic ‘‘0’’ and timing measurements made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. 9. Float Waveform was changed from IOL/IOH e g 15 mA to IOL/IOH s g 15 mA 10. ADÐTIME register for 10-bit conversions was changed from 0C7H to 0D8H. The number of sample time states was changed from 24 to 25 states, the conversion time states was changed from 80 to 240 states, and the total conversion time for ADÐTIME e D8H replaced the total conversion time for ADÐTIME e C7H. 11. The number of sample time states for an 8-bit conversion was changed from 20 states to 21 states. 12. There is a single entry in the ERRATA section of this version of the data sheet concerning the results of an indirect shift during divide. The following important differences exist between this data sheet (270946-002) and the previous version (270946-001): 1. TA Ambient Temperature Under Bias Min changed from b 20§ C to b 40§ C. 2. IREF A/D Conversion Reference Current Max changed from 5 mA to 2 mA. 3. Testing levels changed from TTL values to CMOS values. 4. A/D Input Series Resistance Max changed from 1.2 KX to 2 KX.