2ED2181 (4) S06F
2ED2103S06F
650 V half bridge gate driver with integrated bootstrap diode
Features
Product summary
VS_OFFSET = 650 V max
Io+pk / Io-pk (typ.) = 290 mA / 700 mA
VCC = 10 V to 20 V
Delay matching = 10 ns max.
Propagation delay = 90 ns
Unique Infineon Thin-Film-Silicon On Insulator (SOI)-technology
Negative VS transient voltage immunity of -100 V
Floating channel designed for bootstrap operation
Operating voltages (VS node) up to + 650 V
Maximum bootstrap voltage (VB node) of + 675 V
Integrated ultra-fast, low resistance bootstrap diode
Logic operational up to –11 V on VS Pin
Negative voltage tolerance on inputs of –5 V
Independent under voltage lockout for both channels
Schmitt trigger inputs with hysteresis
3.3 V, 5 V and 15 V input logic compatible
Maximum supply voltage of 25 V
DSO-8 package
RoHS compliant
Package
DSO-8
Potential applications
Driving IGBTs, enhancement mode N-Channel MOSFETs in various power electronic applications.
Typical Infineon recommendations are as below:
Motor drives, general purpose inverters having TRENCHSTOP ™ IGBT6 or 600 V EasyPACK™ modules
Refrigeration compressors, induction cookers, other major home appliances having RCD series IGBTs or
TRENCHSTOP™ family IGBTs or their equivalent power stages
Battery operated small home appliances such as power tools, vacuum cleaners using low voltage OptiMOS™
MOSFETs or their equivalent power stages
Totem pole, half-bridge and full-bridge converters in offline AC-DC power supplies for industrial SMPS having
high voltage CoolMOS™ super junction MOSFETs or TRENCHSTOP™ H3 and WR5 IGBT series
High power LED and HID lighting having CoolMOS™ super junction MOSFETs
Electric vehicle (EV) charging stations and battery management systems
Driving 650 V SiC MOSFETs in above applications
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22
Ordering information
Base part number
Package type
2ED2103S06F
DSO – 8
Datasheet
www.infineon.com/soi
Standard pack
Form
Quantity
Tape and Reel
2500
Orderable part number
2ED2103S06FXUMA1
Please read the Important Notice and Warnings at the end of this document
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2ED2103S06F
650V half bridge driver with integrated bootstrap diode
Description
The 2ED2103S06F is a high voltage, high speed power MOSFET and IGBT driver with independent high and low
side referenced output channels. Based on Infineon’s SOI-technology there is an excellent ruggedness and noise
immunity with capability to maintain operational logic at negative voltages of up to - 11 VDC on VS pin (VCC = 15 V)
on transient voltages. There are not any parasitic thyristor structures present in the device, hence no parasitic
latch up may occur at all temperature and voltage conditions. The logic input is compatible with standard CMOS
or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET, SiC
MOSFET or IGBT in the high side configuration, which operate up to 650 V.
Up to 650V
VCC
1
VCC
VB
8
IN
2
HIN
HO
7
LIN
3
LIN
VS
6
4
COM
LO
5
TO LOAD
Refer to lead assignments for
correct pin configuration. This
diagram shows electrical
connections only. Please refer to
our application notes and design
tips for proper circuit board
layout.
*Bootstrap diode is monolithically integrated
Figure 1
Typical application block diagram
Summary of feature comparison of the 2ED210x family:
Table 1
Part No.
Package
2ED2101S06F
DSO – 8
2ED2103S06F
DSO – 8
2ED2104S06F
DSO – 8
Datasheet
www.infineon.com/soi
Drive
current
source /
sink
+ 0.29 A
/ - 0.7 A
+ 0.29 A
/ - 0.7 A
+ 0.29 A
/ - 0.7 A
Cross
conduction
Input logic
prevention
logic
Deadtime
Ground
tON / tOFF
pins
HIN, LIN
No
None
COM
HIN, LIN
Yes
Internal 520 ns
COM
IN, SD
Yes
Internal 520 ns
COM
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2ED2103S06F
650V half bridge driver with integrated bootstrap diode
1
Table of contents
Features
Product summary ........................................................................................................................ 1
Product validation ....................................................................................................................................................... 1
Description ……........................................................................................................................................................... 2
1
Table of contents ................................................................................................................... 3
2
Block diagram........................................................................................................................ 4
3
3.1
3.2
Pin configuration and functionality .......................................................................................... 5
Pin configuration ..................................................................................................................................... 5
Pin functionality ...................................................................................................................................... 5
4
4.1
4.2
4.3
4.4
Electrical parameters ............................................................................................................. 6
Absolute maximum ratings ..................................................................................................................... 6
Recommended operating conditions..................................................................................................... 6
Static electrical characteristics ............................................................................................................... 7
Dynamic electrical characteristics .......................................................................................................... 8
5
Application information and additional details .......................................................................... 9
5.1
IGBT / MOSFET gate drive ....................................................................................................................... 9
5.2
Switching and timing relationships ........................................................................................................ 9
5.3
Deadtime ............................................................................................................................................... 10
5.4
Matched propagation delays ................................................................................................................ 10
5.5
Input logic compatibility ....................................................................................................................... 10
5.6
Undervoltage lockout ........................................................................................................................... 11
5.7
Bootstrap diode..................................................................................................................................... 12
5.8
Calculating the bootstrap capacitance CBS .......................................................................................... 12
5.9
Tolerant to negative tranisents on input pins ...................................................................................... 14
5.10
Negative voltage transient tolerance of VS pin .................................................................................... 14
5.11
NTSOA – Negative Transient Safe Operating Area ............................................................................... 16
5.12
Higher headroom for input to output signal transmission with logic operation upto -11 V .............. 17
5.13
Maximum switching frequency ............................................................................................................. 17
5.14
PCB layout tips ...................................................................................................................................... 18
6
Qualification information....................................................................................................... 20
7
Related products................................................................................................................... 20
8
Package details ..................................................................................................................... 21
9
Part marking information ...................................................................................................... 22
10
Additional documentation and resources................................................................................. 23
10.1
Infineon online forum resources .......................................................................................................... 23
11
Revision history .................................................................................................................... 24
Datasheet
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2ED2103S06F
650 V high-side and low-side driver with integrated bootstrap diode
2
Block diagram
8
VB
7
HO
6
VS
1
VCC
5
LO
4
COM
UV
DETECT
R
2ED2103S06F
HIN
VSS/COM
LEVEL
SHIFT
2
DT
Pulse
Filter
Pulse
Generator
BS diode
UV
DETECT
VSS/COM
LEVEL
SHIFT
3
Figure 2
Q
Deadtime
+5V
LIN
R
S
Delay
Match
Block diagrams
Datasheet
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2ED2103S06F
650 V high-side and low-side driver with integrated bootstrap diode
3
Pin configuration and functionality
3.1
Pin configuration
1
VCC
VB
8
2
HIN
HO
7
3
/LIN
VS
6
4
COM
LO
5
8-Lead DSO-8 (150 mil)
2ED2103S06F
Figure 3
3.2
2ED2103S06F pin assignments (top view)
Pin functionality
Table 2
Symbol
Description
HIN
Logic input for high side gate driver output (HO), in phase with HO
/LIN
Logic input for low side gate driver output (LO), out of phase with LO
COM
Low-side gate drive return
LO
Low-side driver output
VCC
Low-side and logic supply voltage
VS
High voltage floating supply return
HO
High-side driver output
VB
High-side gate drive floating supply
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2ED2103S06F
650 V high-side and low-side driver with integrated bootstrap diode
4
Electrical parameters
4.1
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Table 3
Symbol
VB
VS
VHO
VCC
VLO
VIN
dVS/dt
PD
RthJA
TJ
TS
TL
Absolute maximum ratings
Definition
High-side floating well supply voltage
High-side floating well supply return voltage
Floating gate drive output voltage
Low side supply voltage
Low-side output voltage
Logic input voltage (HIN & /LIN)
Allowable VS offset supply transient relative to COM
Package power dissipation @ TA +25ºC
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Note 1
Min.
Max.
VCC – 6
VCC – VBS– 6
675
650
VB + 0.5
25
VCC + 0.5
VCC + 0.5
50
0.625
200
150
150
260
VS – 0.5
-1
–0.5
-5
—
—
—
—
-55
—
Units
V
V/ns
W
ºC/W
ºC
Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins V CC and VB in case of
activated bootstrap diode.
4.2
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with
supplies of (VCC – COM) = (VB – VS) = 15 V.
Table 4
Recommended operating conditions
Symbol
Definition
VB
Bootstrap voltage
VBS
High-side floating well supply voltage
VS
High-side floating well supply offset voltage Note 2
VHO
Floating gate drive output voltage
VCC
Low-side supply voltage
VLO
Low-side output voltage
VIN
Logic input voltage(HIN & /LIN)
TA
Ambient temperature
Min
VS + 10
10
-11
VS
10
0
-4
-40
Max
VS + 20
20
650
VB
20
VCC
VCC
125
Units
V
ºC
Note 2: Logic operation for VS of – 11 V to +650 V.
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650 V high-side and low-side driver with integrated bootstrap diode
4.3
Static electrical characteristics
(VCC– COM) = (VB – VS) = 15 V and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN parameters are referenced
to COM and are applicable to the respective input leads: HIN and /LIN. The VO and IO parameters are referenced
to VS / COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are referenced to
COM. The VBSUV parameters are referenced to VS.
Table 5
Static electrical characteristics
Symbol
Min.
Typ.
Max.
8.2
8.9
9.6
7.3
8.0
8.7
—
0.9
—
8.2
8.9
9.6
7.3
8.0
8.7
—
—
—
—
—
—
180
0.9
1
160
400
0.05
0.02
230
—
12.5
245
650
0.2
0.1
—
Peak output current turn-on1
—
290
—
Io-mean Mean output current from 12 V to 9 V
450
650
—
VBSUV+
VBSUVVBSUVHY
VCCUV+
VCCUVVCCUVHY
ILK
IQBS
IQCC
VOH
VOL
Io+mean
Io+
Units
Test Conditions
V
VB = VS = 650 V
uA
VIN = 0V or 5V
V
IO = 2 mA
mA
CL = 22 nF
VO = 0 V
PW ≤ 10 µs
CL = 22 nF
VO = 15 V
PW ≤ 10 µs
V
Vcc=10 V to 20 V
µA
VIN = 5 V
VIN = 0 V
Io-
Peak output current turn-off1
—
700
—
VIH
VIL
IIN+
IIN-
Logic “1” input voltage
Logic “0” input voltage
Input bias current (Output = High)
Input bias current (Output = Low)
Bootstrap diode forward voltage between Vcc
and VB
Bootstrap diode forward current between Vcc
and VB
Bootstrap diode resistance
Allowable Negative VS pin voltage for IN
Signal propagation to HO
1.7
0.7
—
—
2.1
0.9
25
—
2.4
1.1
60
10
—
1
1.2
V
IF=0.3 mA
50
80
120
mA
VCC-VB=4 V
20
36
54
Ω
VF1=4V,VF2=5 V
—
-11
-10
V
Vcc=15 V
VFBSD
IFBSD
RBSD
VS
1
Definition
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going
threshold
VBS supply undervoltage hysteresis
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative going
threshold
VCC supply undervoltage hysteresis
High-side floating well offset supply leakage
Quiescent VBS supply current
Quiescent VCC supply current
High level output voltage drop, Vcc- VLO , VB- VHO
Low level output voltage drop, VO
Mean output current from 3 V to 6 V
Parameter not subject to production test. Parameter guaranteed by design and characterization.
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2ED2103S06F
650 V high-side and low-side driver with integrated bootstrap diode
4.4
Dynamic electrical characteristics
VCC = VBS= 15 V, TA = 25 oC and CL = 1000 pF unless otherwise specified.
Table 6
Symbol
tON
tOFF
tR
tF
MT
DT
1
Dynamic electrical characteristics
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Delay matching time (HS & LS turnon/off)1
Dead time
Min.
Typ.
Max.
—
—
—
—
90
90
70
35
110
110
170
90
—
—
10
400
520
650
Units
Test Conditions
Vin = 5V
VS = 0 V
ns
Parameter not subject to production test. Parameter guaranteed by design and characterization.
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650 V high-side and low-side driver with integrated bootstrap diode
5
Application information and additional details
5.1
IGBT / MOSFET gate drive
The 2ED2103S06F HVIC is designed to drive MOSFET or IGBT power devices. Figure 4 and Figure 5 illustrate
several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used
to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch
is defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is
sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output
voltage.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
HO
(or LO)
+
IO-
VHO (or VLO)
VS
(or COM)
-
VS
(or COM)
Figure 4
HVIC Sourcing current
Figure 5
5.2
Switching and timing relationships
HVIC Sinking current
The relationships between the input and output signals of the 2ED2103S06F are illustrated below in Figure 6
and Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and tF)
associated with this device.
Figure 6
Switching timing diagram
Datasheet
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Figure 7
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Input/output logic diagram
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2ED2103S06F
650 V high-side and low-side driver with integrated bootstrap diode
5.3
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime is fixed for 2ED2103S06F.
The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power
switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the
second power switch is turned on. This minimum deadtime is automatically inserted whenever the external
deadtime is shorter than interal deadtime; external deadtimes larger than internal deadtime are not modified by
the gate driver. Figure 8 illustrates the deadtime period and the relationship between the output gate signals.
Figure 8
5.4
Deadtime waveform definition
Matched propagation delays
The 2ED2103S06F is designed with propagation delay matching circuitry. With this feature, the IC’s response at
the output to a signal at the input requires approximately the same time duration (i.e., t ON, tOFF) for both the lowside channels and the high-side channels; the maximum difference is specified by the delay matching parameter
(MT). The propagation turn-on delay (tON) of the 2ED2103S06F is matched to the propagation turn-on delay (tOFF).
Figure 9
Delay matching waveform definition
5.5
Input logic compatibility
The input pins of are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc
supply voltage. With typical high threshold (VIH) of 2.1 V and typical low threshold (VIL) of 0.9 V, along with very
little temperature variation as summarized in Figure 10, the input pins are conveniently driven with logic level
PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 0.9 V)
offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is
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650 V high-side and low-side driver with integrated bootstrap diode
typically less than 0.5 V. 2ED210x family also features tight control of the input pin threshold voltage levels which
eases system design considerations and ensures stable operation across temperature. The 2ED210x features
floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is
held in the low state. This is achieved using pull-down resistors on all the input pins (HIN, LIN) as shown in the
block diagram. The 2ED210x family has input pins that are capable of sustaining voltages higher than the bias
voltage applied on the Vcc pin of the device.
Input Signal
(IRS23364D)
VIH
Input Logic
Level
VIL
High
Low
Figure 10
HIN & LIN input thresholds
5.6
Undervoltage lockout
Low
This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and
the VBS (high-side circuitry) power supply. Figure 11 is used to illustrate this concept; VCC (or VBS) is plotted over
time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled
or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC won’t turn-on. Additionally, if the
VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition and shutdown the high and low-side gate drive outputs.
Upon power-up, should the VBS voltage fail to reach the VBSUV+ threshold, the IC won’t turn-on. Additionally, if the
VBS voltage decreases below the VBSUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could
be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is
high; this could result in very high conduction losses within the power device and could lead to power device
failure.
VCC
(or VBS)
VCCUV(or VBSUV-)
VCCUV+
(or VBSUV+)
Time
UVLO Protection
(Gate Drive Outputs Disabled)
Normal
Operation
Figure 11
Normal
Operation
UVLO protection
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650 V high-side and low-side driver with integrated bootstrap diode
5.7
Bootstrap diode
An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap
capacitor. The integrated diode with its resistance helps save cost and improve reliability by reducing external
components as shown below Figure 12 and Figure 13.
Figure 12
2ED210x with integrated components
Figure 13
Standard bootstrap gate driver
The low ohmic current limiting resistor provides essential advantages over other competitor devices with high
ohmic bootstrap structures. A low ohmic resistor such as in the 2ED210x family allows faster recharching of the
bootstrap capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is usable
for all kind power electronic converters. The bootstrap diode is a real pn-diode and is temperature robust. It can
be used at high temperatures with a low duty cycle of the low side transistor.
The bootstrap diode of the 2ED210x family works with all control algorithms of modern power electronics, such
as trapezoidal or sinusoidal motor drives control.
5.8
Calculating the bootstrap capacitance CBS
Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique
a supply voltage for the floating high side sections of the gate drive can be easily established according to Figure
14. This method has the advantage of being simple and low cost but may force some limitations on duty-cycle
and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper
capacitor choice can reduce drastically these limitations.
Figure 14
Half bridge bootstrap circuit in 2ED210x
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When the low side MOSFET turns on, it will force the potential of pin VS to GND. The existing difference between
the voltage of the bootstrap capacitor VCBS and VCC results in a charging current IBS into the capacitor CBS. The
current IBS is a pulse current and therefore the ESR of the capacitor CBS must be very small in order to avoid losses
in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low side is
turned off and high side is conducting current. But now the bootstrap diode DBS blocks a reverse current, so that
the charges on the capacitor cannot flow back to the capacitor CVCC. The bootstrap diode DBS also takes over the
blocking voltage between pin VB and VCC. The voltage of the bootstrap capacitor can now supply the high side
gate drive sections. It is a general design rule for the location of bootstrap capacitors CBS, that they must be placed
as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes, which
may trigger the undervoltage lockout threshold of the individual high side driver section. However, all parts of
the 2ED210x family, which have the UVLO also contain a filter at each supply section in order to actively avoid
such undesired UVLO triggers.
The current limiting resistor RBS according to Figure 14 reduces the peak of the pulse current during the low side
MOSFET turn-on. The pulse current will occur at each turn-on of the low side MOSFET, so that with increasing
switching frequency the capacitor CBS is charged more frequently. Therefore a smaller capacitor is suitable at
higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high side
quiescent current and the gate charge of the high side MOSFET to be turned on.
The minimum size of the bootstrap capacitor is given by
𝐶𝐵𝑆 =
𝑄𝐺𝑇𝑂𝑇
∆𝑉𝐵𝑆
VBS is the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V.
It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit
VBS ≤ (VCC – VF– VGSmin– VDSon)
VGSmin > VBSUV- , VGSmin is the minimum gate source voltage we want to maintain and VBSUV- is the high-side supply
undervoltage negative threshold.
VCC is the IC voltage supply, VF is bootstrap diode forward voltage and VDSon is drain-source voltage of low side
MOSFET.
Please note, that the value QGTOT may vary to a maximum value based on different factors as explained below and
the capacitor shows voltage dependent derating behavior of its capacitance.
The influencing factors contributing VBS to decrease are:
- MOSFET turn on required Gate charge (QG)
- MOSFET gate-source leakage current (ILK_GS)
- Floating section quiescent current (IQBS)
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE)
- Charge required by the internal level shifters (𝑄𝐿𝑆 ): typical 1nC
- Bootstrap capacitor leakage current (ILK_CAP)
- High side on time (THON)
Considering the above,
𝑄𝐺𝑇𝑂𝑇 = 𝑄𝐺 + 𝑄𝐿𝑆 + (𝐼𝑄𝐵𝑆 + 𝐼𝐿𝐾𝐺𝑆 + 𝐼𝐿𝐾 + 𝐼𝐿𝐾𝐷𝐼𝑂𝐷𝐸 + 𝐼𝐿𝐾𝐶𝐴𝑃 ) ∗ 𝑇𝐻𝑂𝑁
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ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are
used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor
and low ESR ceramic capacitor may result in an efficient solution).
The above CBS equation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance values
are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap
capacitance is therefore in the range up to 4.7 μF for most switching frequencies. The performance of the
integrated bootstrap diode supports the requirement for small bootstrap capacitances.
5.9
Tolerant to negative transients on input pins
Typically the driver's ground pin is connected close to the source pin of the MOSFET or IGBT. The microcontroller
which sends the HIN and LIN PWM signals refers to the same ground and in most cases there will be an offset
voltage between the microcontroller ground pin and driver ground because of ground bounce. The 2ED210x
family can handle negative voltage spikes up to 5 V. The recommended operating level is at negative 4 V with
absolute maximum of negative 5 V. Standard half bridge or high-side/low-side drivers only allow negative voltage
levels down to -0.3 V. The 2ED210x family has much better noise immunity capability on the input pins.
Figure 15
Negative voltage tolerance on inputs of up to –5 V
5.10
Negative voltage transient tolerance of VS pin
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase
inverter circuit is shown in Figure 16, here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figure 16 and Figure 17) switches from on to off, while the U phase
current is flowing to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode
(D2) in parallel with the low-side switch of the same inverter leg. At the same instance, the voltage node V S1,
swings from the positive DC bus voltage to the negative DC bus voltage.
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DC+ BUS
D1
Q1
Input
Voltage
VS1
Q2
D3
Q3
VS2
U
D2
Q4
D5
Q5
VS3
V
D4
W
To
Load
D6
Q6
DC- BUS
Figure 16
Three phase inverter
Also when the V phase current flows from the inductive load back to the inverter (see Figure 17 C) and D)), and
Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather
it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”
DC+ BUS
DC+ BUS
Q1
ON
Q1
OFF
DC+ BUS
DC+ BUS
D1
Q3
OFF
D3
IU
Q3
OFF
D3
IV
VS1
VS2
VS2
VS1
IV
IU
Q2
OFF
D2
Q2
OFF
A)
DC- BUS
Figure 17
A) Q1 conducting
D2
DC- BUS
Q4
OFF
B)
D4
DC- BUS
B) D2 conducting
Q4
ON
C)
C) D3 conducting
DC- BUS
D)
D) Q4 conducting
The circuit shown in Figure 18-A depicts one leg of the three phase inverter; Figure 18-B and Figure 18-C show a
simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the
power circuit from the die bonding to the PCB tracks are lumped together in L C and LE for each IGBT. When the
high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and
the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily
flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in
these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load
and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential
than the VS pin).
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DC+ BUS
DC+ BUS
DC+ BUS
+
LC1
VLC1
-
D1
Q1
+
LE1
VLE1
VS1
VS1
LC2
D1
Q1
OFF
Q1
ON
IU
-
VS1
-
VLC2
IU
+
Q2
D2
Q2
OFF
D2
-
Q2
OFF
VD2
+
-
LE2
VLE2
+
DC- BUS
A
DC- BUS
B
DC- BUS
C
Figure 18
Figure A shows the Parasitic Elements. Figure B shows the generation of VS positive. Figure C shows
the generation of VS negative
5.11
NTSOA – Negative Transient Safe Operating Area
In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS
transient voltage can exceed this range during some events such as short circuit and over-current shutdown,
when di/dt is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the 2ED2103’s robustness can be seen in Figure 19, where the 2ED2103’s Safe Operating Area is
shown at VBS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area
(outside SOA) may lead to IC permanent damage; vice versa unwanted functional anomalies or permanent
damage to the IC do not appear if negative Vs transients fall inside the SOA.
Recommended safe operating area
Figure 19
Negative VS transient SOA for 2ED2103S06F @ VBS=15 V
Even though the 2ED2103S06F has been shown able to handle these large negative VS transient conditions, it is
highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
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5.12
Higher headroom for input to output signal transmission with logic
operation up to -11 V
If there is not enough voltage for the level shifter to transmit a valid signal to the high side. High side driver
doesn’t turn on. The level shifter circuit is with respect to COM (refer to Block Diagram on page 4), the voltage
from VB to COM is the supply voltage of level shifter. Under the condition of VS is negative voltage with respect to
COM, the voltage of VS - COM is decreased, as shown in Figure 20. There is a minimum operational supply voltage
of level shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HIN signal to
HO. If VB – VS voltage is different, the minimum VS voltage changes accordingly.
VS
COM
- 11 V
Figure 20
Headroom for HV level shifter data transmission
5.13
Maximum switching frequency
The 2ED210x family is capable of switching at higher frequencies as compared to standard half-bridge or high
side / low side gate drivers. They are available in PG-DSO-8 package. It is essential to ensure that the component
is not thermally overloaded when operating at higher frequencies. This can be checked by means of the thermal
resistance junction to ambient and the calculation or measurement of the dissipated power. The thermal
resistance is given in the datasheet (section 4) and refers to a specific layout. Changes of this layout may lead to
an increased thermal resistance, which will reduce the total dissipated power of the driver IC. One should
therefore do temperature measurements in order to avoid thermal overload under application relevant
conditions of ambient temperature and housing.
The maximum chip temperature TJ can be calculated with
𝑇𝐽 = Pd ∙ 𝑅𝑡ℎ𝐽𝐴 + 𝑇𝐴_𝑚𝑎𝑥 , where TA_max is the maximum ambient temperature.
The dissipated power Pd by the driver IC is a combination of several sources. These are explained in detail in the
application note “Advantages of Infineon’s Silicon on Insulator (SOI) technology based High Voltage Gate Driver
ICs (HVICs)”
The output section is the major contributor for the power dissipation of the gate driver IC. The external gate
resistors also contribute to the power dissipation of the gate driver IC. The bigger the external gate resistor, the
smaller the power dissipation in the gate driver.
The losses of the output section are calculated by means of the total gate charge of the power MOSFET or IGBT
it is driving Qgtot, the supply voltage VCC, the switching frequency fP, and the ext. gate resistor Rgon and Rgoff. Different
cases for turn-on and turn-off must be considered, because many designs use different resistors for turn-on and
turn-off. This leads to a specific distribution of losses in respect to the external gate resistor R gxx_ext and the
internal resistances (Ron_int and Roff_int) of the output section.
Turn on losses: 𝑃𝑑𝑜𝑛 =
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2
2
× 𝑄𝑔𝑡𝑜𝑡 × 𝑉𝑐𝑐 × 𝑓𝑝 ×
𝑅𝑜𝑛_𝑖𝑛𝑡
𝑅𝑜𝑛_𝑖𝑛𝑡+𝑅𝑔𝑜𝑛_𝑒𝑥𝑡
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𝑅𝑜𝑓𝑓_𝑖𝑛𝑡
Turn off losses: 𝑃𝑑𝑜𝑓𝑓 = 2 × 𝑄𝑔𝑡𝑜𝑡 × 𝑉𝑐𝑐 × 𝑓𝑝 × 𝑅𝑜𝑓𝑓_𝑖𝑛𝑡+𝑅𝑔𝑜𝑓𝑓_𝑒𝑥𝑡
Junction Temperature ( ℃ )
The above two losses are then added to the remaining static losses within the gate driver IC and we arrive at the
below figure as example which estimates the gate driver IC temperature rise when switching a given MOSFET at
different switching frequencies.
150
Vbus = 400 V
Vbus = 200 V
125
100
75
50
25
25
125
225
325
425
525
Frequency (kHz)
* Assumptions for above curves: LLC topology, Power switch = IPP60R600P6, Ta = 25 °C, VBUS = 400 V, VCC = 12 V,
Rgon = 15 Ω, Rgoff = 12 Ω
Figure 21
5.14
Estimated temperature rise in the 2ED210x family gate drivers for different switching
frequencies when switching CoolMOSTM SJ MOSFETs
PCB layout tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied
to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the
Case Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
22). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 22
Avoid antenna loops
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Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic
1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible
to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients
at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such
conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)
minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain
excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between
the VS pin and the switch node (see Figure 23 - A), and in some cases using a clamping diode between COM and
VS (see Figure 23 - B). See DT04-4 at www.infineon.com for more detailed explanations.
Figure 23
Resistor between the VS pin and the switch node and clamping diode between COM and VS
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Table 7
Qualification information1
Qualification information
Qualification level
Moisture sensitivity level
Charged device model
ESD
Human body model
IC latch-up test
RoHS compliant
7
Industrial2
Note: This family of ICs has passed JEDEC’s Industrial
qualification. Consumer qualification level is granted by
extension of the higher Industrial level.
MSL2, 260°C
DSO-8
(per IPC/JEDEC J-STD-020E)
Class C3 (1.0 kV)
(per ANSI/ESDA/JEDEC JS-002-2018)
Class 2 (2 kV)
(per ANSI/ESDA/JEDEC JS-001-2017)
Class II Level A
(per JESD78E)
Yes
Related products
Table 8
Product
Description
Gate Driver ICs
6EDL04I06 /
6EDL04N06
2EDL23I06 /
2EDL23N06
Power Switches
IKD04N60R / RF
IKD06N65ET6
IPD65R950CFD
IPN50R950CE
600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low RDS(ON) bootstrap
diodes with over-current protection (OCP), 240/420 mA source/sink current drive, Fault reporting,
and Enable for MOSFET or IGBT switches.
600 V, Half-bridge thin-film SOI level shift gate driver with integrated high speed, low
RDSON bootstrap diode, with over-current protection (OCP), 2.3/2.8 A source/sink current driver,
and one pin Enable/Fault function for MOSFET or IGBT switches.
600 V TRENCHSTOP™ IGBT with integrated diode in PG-TO252-3 package
650 V TRENCHSTOP™ IGBT with integrated diode in DPAK
650 V CoolMOS CFD2 with integrated fast body diode in DPAK
500 V CoolMOS CE Superjunction MOSFET in PG-SOT223 package
iMOTION™ Controllers
IRMCK099
iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented Control
(FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T
High performance Motor Control IC for variable speed drives based on field oriented control (FOC)
of permanent magnet synchronous motors (PMSM).
Qualification standards can be found at Infineon’s web site www.infineon.com
Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
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Package details
Figure 24
8 - Lead DSO (2ED210xS06F)
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Part marking information
Front Side
Back Side
2ED2103
Part number
XXX
Infineon logo
Lot code
H YYWW
Pin 1
identifier
Date code
XXXX
XXXX X
Assembly
site code
(may vary)
Figure 25
Marking information PG-DSO-8
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Additional documentation and resources
Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
Application Notes:
Understanding HVIC Datasheet Specifications
HV Floating MOS-Gate Driver ICs
Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs
Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
Design Tips:
Using Monolithic High Voltage Gate Drivers
Alleviating High Side Latch on Problem at Power Up
Keeping the Bootstrap Capacitor Charged in Buck Converters
Managing Transients in Control IC Driven Power Stages
Simple High Side Drive Provides Fast Switching and Continuous On-Time
10.1
Infineon online forum resources
The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum is where the
Infineon gate driver IC community comes to the assistance of our customers to provide technical guidance – how
to use gate drivers ICs, existing and new gate driver information, application information, availability of demo
boards, online training materials for over 500 gate driver ICs. The Gate Driver Forum also serves as a repository
of FAQs where the user can review solutions to common or specific issues faced in similar applications.
Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power switch in any given
power electronic application.
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Document
version
2.3
Revision history
Date of release
Description of changes
Dec 07, 2020
Final Datasheet
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Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2020-12-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
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