2ED24427N01FXUMA1

2ED24427N01F 10 A dual -channel low-side gate driver IC Features Product summary          VCC = 12.5 V to 24 V Io+pk / Io- pk(typ.) =+ 10 A/ - 10 A tON / tOFF (max.) = 40 ns/ 55 ns 10 A sink and 10 A source driver capability 11.5 V under voltage lockout 24 V maximum supply voltage Enable function CMOS Schmitt-triggered inputs Output in phase with input 3.3 V, 5 V and 15 V input logic compatible 2 kV ESD HBM RoHS compliant Package Potential applications Driving high current IGBTs, enhancement mode N-Channel MOSFETs directly or through a gate drive transformer in various power electronic applications in single or parallel combinations Typical Infineon recommendations are as below:        Power Pad DSO-8 Electric vehicle (EV) charging stations and battery management systems DC-DC converters Industrial Drives Industrial SMPS Motor control Industrial applications General purpose low-side gate driver Product validation Qualified for industrial applications according to the relevant tests of JEDEC JESD47/22 and J-STD-020. Ordering information Base part number 2ED24427N01F Package type Standard pack Form Quantity PG-DSO-8-900 Tape and Reel 2500 Orderable part number 2ED24427N01FXUMA1 Datasheet Please read the Important Notice and Warnings at the end of this document www.infineon.com/gdLowSide Page 1 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC Description The 2ED24427N01F is a low-voltage, power MOSFET and IGBT non-inverting gate driver. Proprietary latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output. The output driver features a current buffer stage. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays between two channels are matched. Internal circuitry on VCC pin provides an under voltage lockout protection that holds output low until Vcc supply voltage is within operating range. * This diagram shows electrical connections only. Please refer to our application notes and design tips for proper circuit board layout. Figure 1 Typical application block diagram Datasheet www.infineon.com/gdLowSide 2 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 1 Table of contents Product summary ........................................................................................................................................................ 1 Description……………. ............................................................................................................................................... 2 1 Table of contents ................................................................................................................... 3 2 Block diagram........................................................................................................................ 4 3 3.1 3.2 3.3 Pin configuration, functionality and logic truth-table ................................................................ 5 Pin configuration ..................................................................................................................................... 5 Pin functionality ...................................................................................................................................... 5 Input/output logic truth table ................................................................................................................ 5 4 4.1 4.2 4.3 4.4 Electrical parameters ............................................................................................................. 6 Absolute maximum ratings ..................................................................................................................... 6 Recommended operating conditions..................................................................................................... 6 Static electrical characteristics ............................................................................................................... 7 Dynamic electrical characteristics .......................................................................................................... 7 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Application information and additional details .......................................................................... 8 Gate driver ............................................................................................................................................... 8 Bridge tied gate transformer driver (BT-GTD) ........................................................................................ 8 Driving circuitry design: thermal considerations ................................................................................. 11 Bias and transient conditions ............................................................................................................... 11 System functionality with improved thermal behavior ....................................................................... 12 Square input pulse distortion ............................................................................................................... 12 Bypass capacitor ................................................................................................................................... 13 Additional Details .................................................................................................................................. 13 6 Qualification information....................................................................................................... 15 7 7.1 7.2 Package details ..................................................................................................................... 16 Tape and reel details: PG-DSO8-900 ..................................................................................................... 17 Part marking information ..................................................................................................................... 17 8 Related products................................................................................................................... 18 9 9.1 Additional documentation and resources................................................................................. 19 Infineon online forum resources .......................................................................................................... 19 10 Revision history .................................................................................................................... 20 Datasheet www.infineon.com/gdLowSide 3 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 2 Figure 2 Block diagram Block diagrams Datasheet www.infineon.com/gdLowSide 4 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 3 Pin configuration, functionality and logic truth-table 3.1 Pin configuration 1 EN 2 INA NC 8 OUTA 7 VCC 6 OUTB 5 3 COM 4 INB 8-Lead Power Pad DSO-8 (150 mil) 2ED24427N01F Figure 3 3.2 2ED24427N01Fpin assignments (top view) Pin functionality Table 1 Pin no. Symbol Description 1 EN Enable pin 2 INA Logic input for gate driver output (OUTA), in phase 3 COM Ground 4 INB Logic input for gate driver output (OUTB), in phase 5 OUTB 6 VCC 7 OUTA 8 NC Gate drive output B Supply voltage Gate drive output A No connection 3.3 Input/output logic truth table Table 2 Input/output logic truth table EN L L H H INA X X L H INB OUTA OUTB L H L L L H L L L H This table is held true in the voltages ranges defined in the recommended conditions section. Datasheet www.infineon.com/gdLowSide 5 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 4 Electrical parameters 4.1 Absolute maximum ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the ―Recommended Operating Conditions‖ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified. Table 3 Symbol VCC VO VIN VEN RthJC TJ TS TL 4.2 Absolute maximum ratings Definition Min Max Fixed supply voltage Output voltage Logic input voltage Logic enable voltage Thermal resistance, junction to case Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) – 0.3 – 0.3 – 0.3 – 0.3 — — – 55 — 24 24 5.5 5.5 4 150 150 300 Units V °C/W °C Recommended operating conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM. Table 4 Symbol VCC VO VIN VEN TA RG CBP Recommended operating conditions Definition Min Max Fixed supply voltage Output voltage Logic input voltage Logic enable voltage Ambient temperature External gate resistance VCC to COM bypass capacitance – X7R dielectric type 5 0 0 0 – 40 2.5 1 20 VCC 5 5 125 Datasheet www.infineon.com/gdLowSide 6 of 21 Units V °C Ω µF V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 4.3 Static electrical characteristics Unless otherwise specified, these specifications apply for an operating junction temperature range of Ta = 25°C and power supply VCC=15 V. The VIN and IIN parameters are referenced to COM and are applicable to input leads: INA and INB. The V O and IO parameters are referenced to COM and are applicable to the output leads: OUTA and OUTB. Table 5 Static electrical characteristics Symbol Definition VIL VIH VHYS-IH VENL VENH VHYS-EN ROH ROL VOH VOL IIN+ IINIQCC VCCUV+ VCCUVVCCUVH IO+ IO- 4.4 Min Typ Max Logic “0” input voltage Logic “1” input voltage Input voltage hysteresis Logic “0” enable voltage Logic “1” enable voltage Enable voltage hysteresis Source output resistance Sink output resistance Output high level voltage (VCC – VO) Output low level voltage VO Logic “1” input bias current Logic “0” input bias current — 2.5 0.8 — 2.5 0.8 — — — — — — — — — — — — — — — — 25 — 0.8 — — 0.8 — — 450 450 450 450 50 1 Quiescent supply current 0.5 1.2 2.4 Vcc supply undervoltage turn on threshold Vcc supply undervoltage turn off threshold Vcc supply undervoltage lockout hysteresis Output sourcing short circuit pulsed current Output sinking short circuit pulsed current 10.5 9.0 — — — 11.5 10.0 1.5 10 10 12.6 11.0 — — — Units Test Conditions V mΩ mV µA mA Ta = +25°C Ta = +25°C , IO = 100 mA VIN = 5 V, VCC = 15 V VIN = 0 V, VCC = 15 V VCC = 15 V, INA & INB not switching V A VCC = 15 V PW ≤ 10 µs Dynamic electrical characteristics Unless otherwise noted, these specifications apply for an operating junction temperature range of Ta = 25°C with bias conditions of VCC = 15 V, CL = 4700 pF. Refer to Figure T2 for switching time definition and to Figure T3 for switching time test circuit. Table 6 Dynamic electrical characteristics Symbol Definition ton toff ton-en toff-en tr tf Turn-on propagation delay Turn-off propagation delay Enable turn-on propagation delay Enable turn-off propagation delay Turn-on rise time Turn-off fall time Datasheet www.infineon.com/gdLowSide Min Typ Max Units Test Conditions — — — — — — — — — — — — 40 55 40 55 33 33 ns CBP = 10 µF 7 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 5 Application information and additional details Information regarding the following topics is included as subsections within this section of the datasheet. • • • • • • • • Gate driver Bridge tied gate transformer driver (BT-GTD) Driving circuitry design: thermal considerations Bias and transient conditions System functionality with improved thermal behavior Square input pulse distortion Bypass capacitor Additional information 5.1 Gate driver The 2ED24427N01F is a high current gate driver for single ended applications. Due to its very high output current and low thermal resistance vs. pcb, it is capable to drive Mosfets with very large input capacitance at frequencies up to fsw = 200 kHz or higher without the need of negative supply. The following Figure 4 shows the typical application schematic: Figure 4 Typical gate driver application Rg values have to be selected based on the requested tr and tf of the application and may vary between 2.5 Ω and 20 Ω, while the input capacitance of the fets can go up to 20 nF or more depending on the switching frequency. Since the very high peak output current, the bypass capacitor Cpb has to be mounted in the close proximityof the Vcc and COM pins and a ceramic type with low ESR has to be chosen. 5.2 Bridge tied gate transformer driver (BT-GTD) This is a popular configuration that allows driving high side fets using a low side gate driver, the Figure 5 shows the typical schematic for a single fet drive: Figure 5 Bridge tied gate driver configuration In this configuration the gate transformer parameters have a very important role, most manufacturers indicate the following in their datasheets: Datasheet www.infineon.com/gdLowSide 8 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC  V*µs ratings: this factor must be respected, in bipolar drive application (like the one shown in Figure 5) a maximum of up to twice that parameter is still acceptable for most manufacturers, this factor then must be chosen accordingly to the following formula: 𝑉 ∗ µ𝑠 𝑟𝑎𝑡𝑖𝑛𝑔 (∗ 2) ≥ 𝑉𝑝𝑟𝑖𝑚∗𝛿 (1) 𝑓𝑠𝑤 where Vprim is the voltage applied to the primary, δ is the duty cycle and fsw the switching frequency of the application.  N, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio between primary and secondary.  Lp, primary inductance: this value determines the magnetizing inductance as follows: (2) 𝐿𝑚 = 𝐿𝑝 ∗ 𝐾 where K is the coupling factor between primary and secondary windings.  LLK, leakage inductance: this parameter, usually indicated at primary, is equal to: (3) 𝐿𝐿𝐾 = 𝐿𝑝 ∗ (1 − 𝐾) The higher Lm is, the lower is the magnetizing current flowing into the transformer and consequent power losses into the driver. On the other hand the lower LLK is, the lower and shorter will be the ringing of the secondary LC network created by LLK, and Ciss of the fet, damped by Rgss and much lower overshot will appear on the Vgs across the Fet during transition. Then a too high Lm requires a very good mechanical construction of the gate transformer to achieve high K and consequent low LLK. In a gate driver application running in the range of 50 kHz-200 kHz and using the 2ED24427N01F, a good choice is usually a Lm between 300 µH and 2 mH and a LLK < 1µH. This translate for the formula (2) and (3) above in a coupling factor K between 0.9940 and 0.9995 For good operation and to reduce unneeded power losses into the 2ED24427N01F driver, the magnetizing current has to be kept ILM < 0.5 A, from this then derives a minimum Lm to be calculated as follows: 𝑉𝑔 𝛿 (4) 𝐿𝑚𝑚𝑖𝑛 = 0.5 ∗ 𝑓𝑠𝑤 Where Vg is the gate driving voltage of the Fet Figure 6 shows a good design waveform obtained with the following parameters: Vg =+/-15 V, Lm = 400 µH, LLK = 0.4 µH, N = 1, fsw = 100 kHz, CissFET = 10 nF, Rg,ps = 3Ω, Rg,ss = 4Ω, and Cdec = 1 µF Cdec is the AC coupling capacitor needed to reset the driver transformer flux, its value has to be calculated in a way that the voltage across it can be considered constant during normal operation. The higher the fsw the smaller will be Cdec. A ceramic capacitor is normally used. Datasheet www.infineon.com/gdLowSide 9 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC Figure 6 Bridge Tied Gate Driver waveforms The waveforms in Figure 6 show that:    The lower LLK is, the lower and shorter is the ringing on the Fets gate voltage, particular care must be paid to guarantee that the max Vgs voltage of the Fet is not exceeded during operation. The lower LLK is, the shorter the propagation delay is from the driver to the gate of the Fet and the higher the peak current is into its gate. The higher Lm is, the lower ILM is; at the primary side the gate peak current, summed to ILM, constitute the total current flowing out of the gate driver. Datasheet www.infineon.com/gdLowSide 10 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 5.3 Driving circuitry design: thermal considerations The following design example shows how to get a proper design of the gate driving circuitry considering the following target application data:  Switching frequency 150 kHz  Load capacitance range [10-100] nF  Supply voltage Vcc = 12 V The switching losses due to the charge/discharge of the capacitive load CL represent the main component of the IC power dissipation. These losses are proportionally shared between the IC output resistance and the external gate resistance Rg. As a consequence the thermal behavior of the IC, with the constraint of a maximum junction temperature equal to 150°C, is one of the key points in dimensioning the system parameters. 0 shows the power that is dissipated inside the IC as a function of load capacitance CL. The external resistance Rg has been chosen in order to keep the product RL*Cg as constant and equal to 300 ns (refer to Figure 4 for switching circuit schematic). For a given parameter sizing the value of Pow allows to calculate the junction temperature Tj as: (5) 𝑇𝐽 = 𝑇𝐴 + 𝑃𝑜𝑤 ∗ 𝑅𝑡ℎ−𝐽𝐴 Where TA is the ambient temperature and RthJA is the junction to ambient thermal resistance. Figure 7 5.4 Simulated IC power dissipation as a function of load capacitance. Bias and transient conditions The input pins of the IC are protected by ESD events with the circuitry shown into ―”Functional block diagram” section at par. Input/Output/Enable Pin Equivalent Circuit Diagrams. This shows that an ESD diode is placed in between each of these pins and Vcc. In case Vcc voltage will be lower than one of the voltage applied to these pins the diode will conduct. Because of its power dissipation the junction temperature will increase. In order to avoid dangerous working conditions it is recommended to keep the Vcc voltage always higher or equal to the INA/INB/Enable pin voltages; it is remind that input voltage must respect the defined absolute maximum rating limits. Datasheet www.infineon.com/gdLowSide 11 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 5.5 System functionality with improved thermal behavior The PG-DSO8-900 package is characterized by a metal thermal pad whose functionality is to reduce the junction to case thermal resistance. In order to better exploit this feature it is necessary to reduce as much as possible the thermal pad to PCB thermal resistance (RthTP-PCB in 0). Two possible ways are suggested: a. Foresee a footprint on layout that allows to solder the thermal pad to the PCB. b. Use thermal material filling the air gap in between the thermal pad and the PCB. Figure 8 5.6 Steady state equivalent thermal circuit Square input pulse distortion The following chapter provides a characterization of pulse width distortion. This is defined as the ratio between the output pulse width with respect to input pulse width. Characterization is done with no load on OUTA and OUTB and it is applicable to both INA, INB and EN input pulses. Figure 9 and Figure 10 show the output pulse length with respect to input pulse length. In particular, Figure 10 describes the pulse distortion in case of a short turn-on input pulse (e.g. low duty cycle condition); while Figure 11 shows the pulse distortion in case of a turn-off input pulse (e.g. high duty cycle condition). Figure 9 Output pulse distortion in case of a short turn-on input pulse Datasheet www.infineon.com/gdLowSide 12 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC Figure 10 5.7 Output pulse distortion in case of a short turn-off input pulse Bypass capacitor The bypass capacitor stores an electrical charge that is released to the power line whenever a transient voltage spike occurs. It provides a low-impedance supply source and it minimizes the noise generated by the switching of the outputs. It is recommended to place the bypass capacitor as close as possible to the gate driver in order to improve its effectiveness by reducing the effect of parasitic inductance of PCB lines. The value of bypass capacitor is related to: a. The current that the gate driver has to provide to the OUTA/B loads during turn-on switching condition; b. The speed at which the output pin is driven; c. The maximum allowed drop on power supply pins. For instance, if it considered that outputs OUTA and OUTB provide 6 A source current with 20 ns rise time and the maximum wished drop on VCC pin is 0.1 V, then the bypass capacitance can be calculated as: ∆𝑇 20 𝑛𝑠 𝐶 =𝑛∗𝐼 = 2∗6𝐴 = 2.4 µ𝐹 ∆𝑉 0.1 𝑉 (6) 5.8 Figure 11 Additional Details Input/output Timing Diagram Datasheet www.infineon.com/gdLowSide 13 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC Figure 12 Switching Time Waveform Definitions Figure 13 Switching time test circuit and test conditions Figure 14 Input/Output/Enable pin equivalent circuit diagrams Datasheet www.infineon.com/gdLowSide 14 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 6 Qualification information Qualification level Moisture sensitivity level Charged device model ESD Human body model IC latch-up test RoHS compliant 1) 2) Industrial 1) Comments: This family of ICs has passed JEDEC’s Industrial qualification. Consumer qualification level is granted by extension of the higher Industrial level. MSL3 2) 260°C (per JEDEC standard J-STD-020) 1000 V (Class C3) (per ANSI/ESDA/JEDEC standard JS-002) 2 kV (per ANSI/ESDA/JEDEC standard JS-001) Class II, Level A (per JESD78) Yes Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information. Datasheet www.infineon.com/gdLowSide 15 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 7 Figure 15 Package details 8 - Lead Power Pad DSO (2ED24427N01F) Datasheet www.infineon.com/gdLowSide 16 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 7.1 Tape and reel details: PG-DSO8-900 LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN Metric Imperial Code Min Max Min Max A 7.90 8.10 0.311 0.318 B 3.90 4.10 0.153 0.161 C 11.70 12.30 0.46 0.484 D 5.45 5.55 0.214 0.218 E 6.30 6.50 0.248 0.255 F 5.10 5.30 0.200 0.208 G 1.50 n/a 0.059 n/a H 1.50 1.60 0.059 0.062 F D B C A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 Figure 16 7.2 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 Tape and reel details Part marking information Front Side Part number 2ED24427 Infineon logo H YYWW Pin 1 identifier Date code (may vary) Figure 17 Marking information PG-DSO-900 (Power Pad-DSO-8) Datasheet www.infineon.com/gdLowSide 17 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 8 Related products Channels Typ. gate Part drive number (Io+/Io-) Max supply voltage UVLO (on/off) Typ. prop. Logic delay (on/off) V V ns 20 5 / 4.15 50 / 50 Single non-inverting channel Dual OUT pins SOT23-5L IRS44273L 25 10.2 / 9.2 50 / 50 Single non-inverting channel Dual OUT pins SOT23-5L IR44273L 20 5 / 4.15 50 / 50 Single non-inverting channel Dual OUT pins SOT23-5L IR44272L 20 5 / 4.15 50 / 50 Single non-inverting channel ENABLE SOT23-5L 1ED44176 25 11.9/11.4 50 / 50 Single non-inverting channel PG-DSO-8 OCP (+CS), fault out and ENABLE 1ED44175 25 11.9/11 50 / 50 Single non-inverting channel OCP, fault out and ENABLE PG-SOT23-6-2 1ED44173 25 8 / 7.3 34 / 34 Single non-inverting channel OCP, fault out and ENABLE PG-SOT23-6-2 50 / 50 Dual inverting channels SOIC-8L 50 / 50 Dual inverting channels SOIC-8L A 0.3 / 0.5 1.5 / 1.5 1 0.8 / 1.75 IR44252L 2.6 / 2.6 IRS4426S 25 IRS44262S 20 2 10.2 / 9.2 Package options 2.3 / 3.3 IRS4427S 25 50 / 50 Dual non-inverting channels SOIC-8L IRS4428S 25 50 / 50 Single inverting channel Single non-inverting channel SOIC-8L Datasheet www.infineon.com/gdLowSide 18 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 9 Additional documentation and resources Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search function and the document number to quickly locate them. Below is a short list of some of these documents. Application Notes: Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs 9.1 Infineon online forum resources The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum is where the Infineon gate driver IC community comes to the assistance of our customers to provide technical guidance – how to use gate drivers ICs, existing and new gate driver information, application information, availability of demo boards, online training materials for over 500 gate driver ICs. The Gate Driver Forum also serves as a repository of FAQs where the user can review solutions to common or specific issues faced in similar applications. Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power switch in any given power electronic application. Datasheet www.infineon.com/gdLowSide 19 of 21 V 2.0 2019-11-10 2ED24427N01F 10 A dual -channel low-side gate driver IC 10 Document version 2.00 Revision history Date of release Description of changes November 10, 2019 Final Datasheet Datasheet www.infineon.com/gdLowSide 20 of 21 V 2.0 2019-11-10 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-09-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2020 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.