BSZ021N04LS6

BSZ021N04LS6 MOSFET OptiMOSTM6Power-Transistor,40V TSDSON-8FL (enlarged source interconnection) Features •Optimizedforsynchronousapplication •Verylowon-resistanceRDS(on) •100%avalanchetested •Superiorthermalresistance •N-channel •QualifiedaccordingtoJEDEC1)fortargetapplications •Pb-freeleadplating;RoHScompliant •Halogen-freeaccordingtoIEC61249-2-21 •175°Crated Table1KeyPerformanceParameters Parameter Value Unit VDS 40 V RDS(on),max 2.1 mΩ ID 40 A Qoss 34 nC QG(0V..10V) 31 nC QG(0V..4.5V) 15 nC S1 8D S2 7D S3 6D G4 5D Type/OrderingCode Package Marking RelatedLinks BSZ021N04LS6 PG-TSDSON-8 FL 21N04L6 - 1) J-STD20 and JESD22 Final Data Sheet 1 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Unit Note/TestCondition 40 40 40 40 25 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=4.5V,TC=25°C VGS=4.5V,TC=100°C VGS=10V,TA=25°C, RTHJA=60°C/W1) - 160 A TC=25°C - - 189 mJ ID=20A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 83 2.5 W TC=25°C TA=25°C,RTHJA=60°C/W1) Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Continuous drain current Pulsed drain current2) 3) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case, bottom Values Min. Typ. Max. RthJC - - 1.8 °C/W - Thermal resistance, junction - case, top RthJC - - 20 °C/W - Device on PCB, 6 cm² cooling area RthJA - - 60 °C/W - 1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See Diagram 3 for more detailed information 3) See Diagram 13 for more detailed information Final Data Sheet 3 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 3Electricalcharacteristics atTj=25°C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA - 2.3 V VDS=VGS,ID=250µA - 0.1 10 1 100 µA VDS=40V,VGS=0V,Tj=25°C VDS=40V,VGS=0V,Tj=125°C IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 1.8 2.4 2.1 3.0 mΩ VGS=10V,ID=20A VGS=4.5V,ID=20A Gate resistance RG - 1.3 - Ω - Transconductance gfs - 110 - S |VDS|≥2|ID|RDS(on)max,ID=20A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 40 - Gate threshold voltage VGS(th) 1.3 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance1) Values Min. Typ. Max. Ciss - 2100 2700 pF VGS=0V,VDS=20V,f=1MHz Coss - 690 900 pF VGS=0V,VDS=20V,f=1MHz Reverse transfer capacitance Crss - 22 38 pF VGS=0V,VDS=20V,f=1MHz Turn-on delay time td(on) - 5 - ns VDD=20V,VGS=10V,ID=20A, RG,ext=1.6Ω Rise time tr - 1.6 - ns VDD=20V,VGS=10V,ID=20A, RG,ext=1.6Ω Turn-off delay time td(off) - 18 - ns VDD=20V,VGS=10V,ID=20A, RG,ext=1.6Ω Fall time tf - 4 - ns VDD=20V,VGS=10V,ID=20A, RG,ext=1.6Ω Unit Note/TestCondition Output capacitance1) 1) Table6Gatechargecharacteristics2) Parameter Symbol Gate to source charge Gate charge at threshold Values Min. Typ. Max. Qgs - 5.6 - nC VDD=20V,ID=20A,VGS=0to10V Qg(th) - 3.3 - nC VDD=20V,ID=20A,VGS=0to10V Gate to drain charge Qgd - 3.8 - nC VDD=20V,ID=20A,VGS=0to10V Switching charge Qsw - 6.0 - nC VDD=20V,ID=20A,VGS=0to10V Gate charge total Qg - 31 - nC VDD=20V,ID=20A,VGS=0to10V Gate plateau voltage Vplateau - 2.6 - V VDD=20V,ID=20A,VGS=0to10V Gate charge total Qg - 15 - nC VDD=20V,ID=20A,VGS=0to4.5V Gate charge total, sync. FET Qg(sync) - 12.8 - nC VDS=0.1V,VGS=0to4.5V Qoss - 34 - nC VDD=20V,VGS=0V 1) 1) 1) Output charge 1) 2) Defined by design. Not subject to production test. See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 Table7Reversediode Parameter Symbol Diode continuous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) Values Unit Note/TestCondition 40 A TC=25°C - 160 A TC=25°C - 0.79 1 V VGS=0V,IF=20A,Tj=25°C trr - 22 - ns VR=20V,IF=20A,diF/dt=400A/µs Qrr - 55 - nC VR=20V,IF=20A,diF/dt=400A/µs Min. Typ. Max. IS - - IS,pulse - VSD Defined by design. Not subject to production test. Final Data Sheet 5 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 100 200 package limit silicon limit 175 80 150 125 ID[A] Ptot[W] 60 40 100 75 50 20 25 0 0 25 50 75 100 125 150 175 0 200 0 25 50 75 TC[°C] 100 125 150 175 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 single pulse 0.01 0.02 0.05 0.1 0.2 0.5 1 µs 102 10 µs 10 ms 1 ms DC 100 µs 100 ID[A] ZthJC[K/W] 101 100 10-1 10-1 10-2 10-1 100 101 102 10-2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 160 6 3V 4V 3.5 V 140 5 5V 120 4.5 V 4 80 10 V 3V 60 RDS(on)[mΩ] ID[A] 100 3.5 V 3 4V 4.5 V 5V 2 40 10 V 2.8 V 1 20 0 0.0 0.5 1.0 1.5 2.0 2.5 0 3.0 0 10 20 30 VDS[V] 40 50 60 70 80 ID[A] ID=f(VDS),Tj=25°C;parameter:VGS RDS(on)=f(ID),Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.drain-sourceonresistance 160 6 140 5 120 4 RDS(on)[mΩ] ID[A] 100 80 60 175 °C 3 2 25 °C 40 1 20 175 °C 0 25 °C 0 1 2 3 4 5 VGS[V] 0 2 4 6 8 10 VGS[V] ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 0 RDS(on)=f(VGS),ID=20A;parameter:Tj 7 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 Diagram9:Normalizeddrain-sourceonresistance Diagram10:Typ.gatethresholdvoltage 2.0 2.4 2.0 1.6 1.2 VGS(th)[V] RDS(on)(normalizedto25°C) 1.6 0.8 1.2 2500 µA 250 µA 0.8 0.4 0.4 0.0 -80 -40 0 40 80 120 160 0.0 -80 200 -40 0 40 Tj[°C] 80 120 160 200 Tj[°C] RDS(on)=f(Tj),ID=20A,VGS=10V VGS(th=f(Tj),VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 25 °C, max 175 °C 175 °C, max Ciss Coss 102 IF[A] 102 C[pF] 103 101 Crss 101 0 5 10 15 20 25 30 35 40 100 0.00 0.25 VDS[V] 0.75 1.00 1.25 1.50 VSD[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 0.50 IF=f(VSD);parameter:Tj 8 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 10 8V 20 V 32 V 8 25 °C 101 100 °C VGS[V] IAV[A] 6 4 0 10 150 °C 2 10-1 100 101 102 103 tAV[µs] 0 0 4 8 12 16 20 24 28 32 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj,start VGS=f(Qgate),ID=20Apulsed,Tj=25°C;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 44 43 VBR(DSS)[V] 42 41 40 39 38 -80 -40 0 40 80 120 160 200 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 5PackageOutlines Figure1OutlinePG-TSDSON-8FL,dimensionsinmm/inches-IndustrialGrade Final Data Sheet 10 Rev.2.1,2018-08-10 OptiMOSTM6Power-Transistor,40V BSZ021N04LS6 RevisionHistory BSZ021N04LS6 Revision:2018-08-10,Rev.2.1 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2018-05-18 Release of final version 2.1 2018-08-10 Update continuous drain current Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. 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TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.1,2018-08-10