ESD102U405LE6327XTSA1

TVS Diodes Transient Voltage Suppressor Diodes ESD102-U4-05L Ultra-Low Capacitance ESD Protection Array for Flow-Through PCB Layout ESD102-U4-05L Data Sheet Revision 1.0, 2013-02-25 Final Power Management & Multimarket Edition 2013-02-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ESD102-U4-05L Revision History: Revision 0.9.1, 2012-11-28 Page or Item Subjects (major changes since previous revision) Revision 1.0, 2013-02-25 All Status change to Final 7 ESD Characteristics updated Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 Revision 1.0, 2013-02-25 ESD102-U4-05L Ultra-Low Capacitance ESD Protection Array for Flow-Through PCB Layout 1 Ultra-Low Capacitance ESD Protection Array for Flow-Through PCB Layout 1.1 Features • ESD / transient protection of high speed data lines exceeding: – IEC61000-4-2 (ESD): ±24 kV (air), ±20 kV (contact) – IEC61000-4-4 (EFT): ±60 A / ±3 kV (5/50ns) – IEC61000-4-5 (Surge): ±3.5 A (8/20μs) Maximum working voltage: VRWM = 3.3 V Ultra low capacitance: – CL = 0.2 pF I/O to I/O (typical) – CL = 0.4 pF I/O to GND (typical) Extremely low leakage voltage: 1 nA (typical) Very low clamping voltage: VCL = 8 V (typical) at IPP = 16 A Very low dynamic resistance: RDYN = 0.19 Ω (typical) TSLP-5-2 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout Pb-free and halogen free package (RoHS compliant) • • • • • • • 1.2 • • • Application Examples USB2.0 (D+, D-, ID), USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, Display Port Mobile HDMI Link, MDDI, MIPI, etc. 1.3 Product Description Pin 5 Pin 4 Pin 1 I/O Pin 3 I/O Pin 4 I/O Pin 5 I/O GND Pin 1 Pin 2 Pin 3 a) Pin configuration Pin 2 b) Schematic diagram c)Equivalent circuit per diode PG-TSLP-5_2_PinConf_and_SchematicDiagi.vsd Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package Configuration Marking code ESD102-U4-05L TSLP-5-2 4 lines, uni-directional A Final Data Sheet 4 Revision 1.0, 2013-02-25 ESD102-U4-05L Characteristics 2 Characteristics Table 2 Maximum Rating at TA = 25 °C, unless otherwise specified Parameter Symbol ESD discharge air contact 1) Values Unit Min. Typ. Max. -24 -20 – – 24 20 -3.5 – 3.5 – – – – 28 750 kV VESD Peak pulse current (tp = 8/20 μs)2) IPP Peak pulse power tp = 8/20 µs2) tp = 100 ns3) PPK Operating temperature TOP -40 – 125 °C Storage temperature 1) VESD according to IEC61000-4-2 2) IPP according to IEC61000-4-5 Tstg -65 – 150 °C A W 3) Please refer to AN210[2] 2.1 Electrical Characteristics at TA = 25 °C, unless otherwise specified    

 
   

      

   




     
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      !#$   " $  !#$         Definitions of electrical characteristics[1] Final Data Sheet 5 Revision 1.0, 2013-02-25 ESD102-U4-05L Characteristics Table 3 DC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VRWM – – 3.3 V I/O to GND Reverse current IR – 1 50 nA I/O to GND, VR = 3.3 V Breakdown voltage1) VBR – 6.2 – V I/O to GND Vt1 – 6.2 – V I/O to GND Vh 3.35 4 4.4 V I/O to GND, IR = 10 mA Reverse working voltage 1) 1) Reverse trigger voltage2) Reverse holding voltage 2) 1) Voltage forced 2) Current forced Table 4 RF Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol 1) Line capacitance CL Values Unit Note / Test Condition Min. Typ. Max. – 0.4 0.65 pF VR = 0 V, f = 1 MHz, I/O to GND – 0.2 0.35 pF VR = 0 V, f = 1 MHz, I/O to I/O Channel capacitance matching between I/O to GND ∆Ci/o-GND – 0.035 – pF VR = 0 V, f = 1 MHz, I/O to GND Channel capacitance matching between I/O to I/O ∆Ci/o-i/o – 0.017 – pF VR = 0 V, f = 1 MHz, I/O to I/O 1) Total capacitance line to ground Final Data Sheet 6 Revision 1.0, 2013-02-25 ESD102-U4-05L Characteristics Table 5 ESD Characteristics1) at TA = 25 °C, unless otherwise specified Parameter Symbol 2) Clamping voltage VCL Values Min. Typ. Max. – 4.8 5.6 – 6.2 7.4 Unit Note / Test Condition V IPP = 1 A, tp = 8/20µs from I/O to GND IPP = 3 A, tp = 8/20µs from I/O to GND 3) Clamping voltage Forward clamping voltage2) VCL VFC – 8 9.5 ITLP = 16 A, from I/O to GND – 11 13.2 ITLP = 30 A, from I/O to GND – 1.4 1.8 IPP = 1 A, tp = 8/20µs from GND to I/O Forward clamping voltage3) Dynamic resistance3) VFC RDYN – 2.3 2.9 IPP = 3 A, tp = 8/20µs from GND to I/O – 6 7.5 ITLP = 16 A, from GND to I/O – 9 11.5 ITLP = 30 A, from GND to I/O – 0.19 0.24 Ω I/O to GND – 0.23 0.28 Ω GND to any I/O 1) Not subject to production test - verified by design/ characterization 2) IPP according to IEC61000-4-5 3) Please refer to Application Note AN210. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between IPP1 = 10 A and IPP2 = 40 A.[2] Final Data Sheet 7 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified Typical Characteristics at TA = 25 °C, unless otherwise specified IR [A] 3 10 -7 10 -8 10 -9 10 -10 10 -11 10-12 Figure 3 0 1 2 VR [V] 3 4 Reverse current, IR = (VR) 10 -6 IR [A] 10-7 10-8 10 -9 25 50 75 100 125 150 TA [°C] Figure 4 Reverse current: IR = f(TA), VR = 3.3 V Final Data Sheet 8 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified 0.8 1MHz 1GHz 0.7 CL [pF] 0.6 0.5 0.4 0.3 0.2 Figure 5 0 0.5 1 1.5 2 VR [V] 2.5 3 3.5 Line capacitance: CL = f(VR), f = 1MHz, from I/O to GND 800 700 PPK [W] 600 500 400 300 200 100 0 10-7 Figure 6 10-6 tp [s] 10-5 Peak pulse power: PPK = f(tp) Final Data Sheet 9 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified 50 25 ESD102-U4-05L RDYN 40 20 30 15 20 10 10 5 0 0 -10 -5 -20 -10 Equivalent VIEC [kV] ITLP [A] RDYN = 0.19 Ω RDYN = 0.23 Ω -30 -15 -40 -20 -50 -20 -10 0 10 -25 20 VTLP [V] Figure 7 Clamping voltage VTLP = f(ITLP)[2] Note: TLP parameter: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between IPP1 = 10 A and IPP2 = 40 A. The equivalent stress level VIEC according IEC 61000-4-2 (R = 330 Ω, C = 150 pF) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kV Final Data Sheet 10 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified 5 ESD102-U4-05L RDYN 4 3 RDYN = 0.70 Ω 2 IPP [A] 1 0 -1 -2 RDYN = 0.44 Ω -3 -4 -5 -10 Figure 8 -8 -6 -4 -2 0 VCL [V] 2 4 6 8 10 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL) Final Data Sheet 11 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified 100 Scope: 6 GHz, 20 GS/s 80 VCL [V] 60 VCL-max-peak = 89 V 40 VCL-30ns-peak = 8 V 20 0 -20 Figure 9 0 100 200 300 tp [ns] 400 500 600 Clamping voltage at +8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF) 20 Scope: 6 GHz, 20 GS/s 0 VCL [V] -20 -40 VCL-max-peak = -86 V -60 VCL-30ns-peak = -6 V -80 -100 Figure 10 0 100 200 tp [ns] 300 400 Clamping voltage at -8 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF) Final Data Sheet 12 Revision 1.0, 2013-02-25 ESD102-U4-05L Typical Characteristics at TA = 25 °C, unless otherwise specified 150 Scope: 6 GHz, 20 GS/s 125 100 VCL [V] 75 VCL-max-peak = 124 V 50 VCL-30ns-peak = 12 V 25 0 -25 -50 Figure 11 0 100 200 tp [ns] 300 400 Clamping voltage at +15 kV discharge according IEC61000-4-2 (R = 330 Ohm, C = 150 pF) 50 Scope: 6 GHz, 20 GS/s 25 0 VCL [V] -25 -50 -75 VCL-max-peak = -121 V -100 VCL-30ns-peak = -9 V -125 -150 Figure 12 0 100 200 tp [ns] 300 400 Clamping voltage at -15 kV discharge according IEC61000-4-2 (R = 330 Ω, C = 150 pF) Final Data Sheet 13 Revision 1.0, 2013-02-25 ESD102-U4-05L Application hints Application hints TX+ TX+ RXTX- TXUSB3.0: SS-Hub e.g. PC SuperSpeed Data OUT + RX+ RX- USB2.0 HUB HS/FS/LS TX+ USB2.0 Data IN RX+ TX+ + connector SuperSpeed Data IN USB3.0 cable SuperSpeed Link RX+ TX+ RX- SuperSpeed Data IN + - TXRX- ESD102-U4-05L low cap. type USB2.0 Device HS/FS/LS D+ D- TX- USB3.0: SS-Device e.g. storage RX+ D+ + - SuperSpeed Data OUT + - TXconnector 4 USB2.0 Data OUT + RX - DTX+ USB2.0 Data OUT RX + - mated connector ID Vcc ID ID Vcc Vcc TX- + - USB2.0 Data IN ID Vcc ESD5V5S1B ESD 102-U4-05L_application.vsd Figure 13 Application High speed low voltage differential signaling (LVDS) is using a coupled line-pair, called ‘lane’ for data transmission. In this data transmission systems load and source impedance as well the characteristic differential line impedance is well defined in the range of 90... 100 Ω for USB2.0/ USB3.0, MIPI, HDMI Thunderbolt. The USB3.0 link provides a full duplex SuperSpeed link (dedicated TX and RX lanes, up to 5 Gb/s) and a USB2.0 link to maintain compatibility. In addition there is a ID pin for identification, the Vcc pin for 5 V supply. To protect from ESD damage, suited ESD protection diodes should be placed close to the connector. For the differential high-speed lines the TVS diodes must not have an impact to insertion loss even not for the third harmonic of the data signal. Signal integrity must not affected by the ESD diode capacitance, The use of ultra low capacitance ESD diode for the data line is mandatory. For the ID and the Vcc pin device capacitance is not critical. To handle the 5 V Vcc line, a 5 V (or even higher) ESD diode is required. Final Data Sheet 14 Revision 1.0, 2013-02-25 ESD102-U4-05L Application hints Insertion Loss in the application Networkanalysor 50 Ohm port1 Line3 Networkanalysor 50 Ohm port2 Line3 ESD102 -U4-05L pin3 ESD102-U4-05L_insertion_loss.vsd Figure 14 Insertion loss measured in 50 Ω environment, correlating to one line in the differential coupled LVDS line pair. 0 Insertion Loss [dB] -1 -2 -3 -4 ESD102-U4-05L pin 4 (inner) to pin 2 (GND) at 0V ESD102-U4-05L pin 4 (inner) to pin 2 (GND) at 3.3V ESD102-U4-05L pin 3 (outer) to pin2 (GND) at 0V ESD102-U4-05L pin 3 (outer) to pin 2 (GND) at 3.3V -5 0 1 2 3 4 5 6 7 8 9 10 Frequency [GHz] Figure 15 Insertion loss vs. frequency of ESD102-U5-05L in a 50 Ω system Final Data Sheet 15 Revision 1.0, 2013-02-25 ESD102-U4-05L Application hints 50 Ohm Networkanalysor 50 Ohm port1 Line1 Line1 Xtalk in the application pin1 vs. pin3 xtalk ESD102-U4-05L pin1 Line3 Networkanalysor 50 Ohm port2 Line3 ESD102 -U4-05L pin3 50 Ohm ESD 102-U4-05L_cross_talk.vsd Figure 16 Crosstalk (xtalk) between two ESD diodes (part of ESD102-U4-05L) measured in USB3.0 SuperSpeed environment (100 Ω differential impedance) -30 ESD102-U4-05L pin1 vs. pin3, x-talk in application X-talk pin1 vs. pin3 [dB] -40 -50 -60 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 9 10 Frequency [GHz] Figure 17 Xtalk vs. frequency of ESD102-U5-=5L in a 100 Ω system Final Data Sheet 16 Revision 1.0, 2013-02-25 ESD102-U4-05L Package Information 5 Package Information 5.1 TSLP-5-2 (mm) Bottom view 0.8 ±0.05 0.5 ±0.05 0.26 3 0.03 0.05 MAX. ±0.035 1) 1 4 2 5 0.46 ±0.05 Pin 1 marking 1) Dimension applies to plated terminals Figure 18 0.5 ±0.05 1.3 ±0.05 +0.01 0.39 -0.03 0.2 ±0.035 1) Top view TSLP-5-2-PO V01 TSLP-5-2: Package overview 0.5 0.5 0.46 0.46 0.26 0.2 0.26 0.2 0.5 0.5 Copper Stencil apertures Solder mask TSLP-5-2-FP V01 Figure 19 TSLP-5-2: Footprint 1.46 Pin 1 marking 8 0.5 2 1 TSLP-5-2: Packing 12 Figure 20 TSLP-5-2-TP V01 Date code Type code Pin 1 marking TSLP-5-2-MK V02 Figure 21 TSLP-5-2: Marking Final Data Sheet 17 Revision 1.0, 2013-02-25 ESD102-U4-05L References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity. Final Data Sheet 18 Revision 1.0, 2013-02-25 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG