IR1161LTRPBF

SMPS IC SmartRectifier IR1161LPBF SmartRectifier Control IC Product Summary Features • • • • • • • • • • • • Secondary side synchronous rectification controller DCM, CrCM Flyback and resonant half-bridge topologies Direct sensing of MOSFET drain voltage up to 200V Max 500kHz switching frequency Anti-bounce logic and UVLO protection Micropower start-up & ultra-low quiescent current 50ns turn-off propagation delay Programmable Minimum On Time Vcc Operating voltage range 4.75V to 18V Cycle by Cycle MOT Check Circuit Lead-free Compatible with 0.3W Standby, Energy Star, CECP, etc. Topology Flyback, Resonant Half-bridge VD 200V VCC 4.75V ~ 18V Io+ & I o- +1A & -2.5A Turn on Propagation Delay Turn off Propagation Delay 50ns (typical) 50ns (typical) Package Options Applications • Charger, AC-DC adapters 5-Pin SOT-23 Application Diagram + LOAD Primary Controller GATE 5 MOT 3 IR1161 VD 4 2 GND 1 VCC Ordering Information Base Part Number IR1161LPBF 1 Package Type 5L-SOT-23 Standard Pack Form Quantity Tape and Reel 3000 Complete Part Number IR1161LTRPBF 2016-07-01 IR1161LPBF Table of Contents Page Ordering Information 1 Description 3 Absolute Maximum Ratings 4 Electrical Characteristics 5 Functional Block Diagram 7 Input/Output Pin Equivalent Circuit Diagram 8 Pin Definitions 9 Pin Assignments 9 Application Information and Additional Details 10 Package Details 21 Tape and Reel Details 22 Part Marking Information 24 Qualification Information 25 2 2016-07-01 IR1161LPBF Description The IR1161 is a synchronous rectification control IC designed to drive an N-Channel power MOSFET in a secondary output rectifier circuit. The MOSFET gate is switched on and off to bypass its body diode during the of the conduction period to minimize power dissipation, remaining off during the blocking period. The drain to source voltage is accurately sensed to determine the direction and magnitude of the current allowing the IR1161 to turn the MOSFET on and off at close to zero current. An integrated cycle-by-cycle minimum on time (MOT) protection circuit automatically detects a no load condition and turns off the gate driver output preventing negative current from flowing through the MOSFET. Ruggedness and noise immunity are accomplished using an advanced blanking scheme and double-pulse suppression, which allows reliable operation in all operating modes. 3 2016-07-01 IR1161LPBF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND, all currents are defined positive into any pin. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VCC VD VD VMOT VGATE TJ TS RθJA PD Definition Supply Voltage Cont. Drain Sense Voltage Pulse Drain Sense Voltage MOT Voltage Gate Voltage Operating Junction Temperature Storage Temperature Thermal Resistance Package Power Dissipation Min. -0.3 -1 -3 -0.3 -0.3 -40 -55 — — Max. 20 200 200 3.5 VCC+0.3 150 150 † 212 † 590 Units Remarks V VCC=18V, Gate off °C °C/W mW TAMB=25°C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VCC VD TJ Fsw †† Definition Supply voltage Drain Sense Voltage Junction Temperature Switching Frequency Min. 4.75 Units -3 -40 — Max. 18 200 125 500 Min. 5 1 Max. 100 — Units kΩ µF †† V °C kHz VD -3V negative spike width ≤100ns Recommended Component Values Symbol RMOT CVCC 4 Component MOT pin resistor value VCC decoupling capacitor value 2016-07-01 IR1161LPBF Electrical Characteristics VCC=12V and TA=25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to GND pin. Symbol Definition Min. Typ. Max. Units Supply Voltage Operating Range VCC Turn On Threshold 4.75 4.25 — 4.5 18 4.75 VCC UVLO VCC Turn Off Threshold (Under Voltage Lock Out) 4.15 4.4 4.65 VCC HYST VCC Turn On/Off Hysteresis — 0.1 — ICC Operating Current — 5.0 8.0 IQCC Quiescent Current Start-up Current — — 0.65 10 1.1 50 -8 -263 — -4 -230 230 0 -197 — mV -10 — -7.5 7 — 30 µA 8 1.06 — 24 1.31 — — 13 1.18 400 70 80 400 0.8 100 500 1 Remarks Supply Section VCC VCC ON ICC START Comparator Section VTH1 Turn-off Threshold VTH2 Turn-on Threshold VHYST Hysteresis IIBIAS1 Input Bias Current IIBIAS2 Input Bias Current One-Shot Section tBLANK Blanking Pulse Duration VTH3 Reset Threshold tBRST Blanking Time of Reset VHYST3 Hysteresis V mA µA CLOAD=1nF, fSW =300kHz RMOT=50k VCC= VCC ON - 0.1V VCC=5V to 15V VD=-50mV VD=200V — µs V ns mV GBD 120 600 1.2 ns ns µs RMOT=5k RMOT=24k RMOT=50k Minimum On Time Section TONmin 5 Minimum On Time 2016-07-01 IR1161LPBF Electrical Characteristics VCC=12V and TA=25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to GND pin. Symbol Gate Driver Section Definition VGLO Gate Low Voltage VGTH Gate High Voltage tr tf Rise Time Fall Time Min. Typ. Max. — 0.2 0.4 11.5 4.5 — — 11.9 4.9 20 13 VCC VCC — — V ns tDon Turn on Propagation Delay — 60 90 tDoff Turn off Propagation Delay — 50 60 rup Pull up Resistance Pull down Resistance — 9 2 — rdown IO source IO sink Output Peak Current (source) Output Peak Current (sink) — — — 1 2.5 — — — Units Ω A Remarks IGATE=100mA, VCC=12V VCC=12V, IGATE=5mA VCC=5V, IGATE=5mA CLOAD=1nF, VCC=12V CLOAD=1nF, VCC=12V VDS to VGATE – VDS goes down from 6V to -1V VDS to VGATE – VDS goes up from -1V to 6V IGATE=100mA IGATE=-100mA GBD GBD GBD – parameter is guaranteed by design and is not tested. 6 2016-07-01 IR1161LPBF Functional Block Diagram VCC MOT UVLO Cycle by Cycle MOT Check Circuit VCC VD VTH2 S Q R Q Min ON Time RESET DRIVER VTH1 VGATE GND Arming Logic & Blanking SET VTH3 7 2016-07-01 IR1161LPBF I/O Pin Equivalent Circuit Diagram VCC VCC ESD Diode ESD Diode MOT GATE ESD Diode ESD Diode GND GND VD ESD Diode RESD 200V Diode GND 8 2016-07-01 IR1161LPBF Pin Definitions PIN# 1 2 3 4 5 Symbol VCC GND MOT VD GATE Description Supply Voltage Ground Minimum On Time Program Input FET Drain Sensing Gate Drive Output Pin Assignments 5 GATE VCC 1 MOT 3 IR1161 GND 2 4 VD Detailed Pin Description VCC: Power Supply The supply voltage pin is monitored by the under voltage lockout circuit. It is possible to turn off the IC entering UVLO mode by pulling this pin below the minimum turn off threshold voltage for micro power consumption. To avoid noise problems a bypass ceramic capacitor connected to Vcc and GND is needed, which should be placed as close as possible to the IC. A low value series resistor to Vcc may also be added if extra filtering is required. This pin is internally clamped to 20V. GND: Ground This is the IC ground reference connected to the SR MOSFET source. MOT: Minimum On Time The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed for the first time, the gate signal will transition high and turn on the power MOSFET. Spurious ringing and oscillations can falsely trigger the input comparator to switch the output off. The MOT prevents this by blanking the input comparator to keep the SR MOSFET on for a minimum time. The MOT is typically programmed between 500ns and 2us by using an external resistor referenced to GND. VD: Drain Voltage Sense VD is the voltage sense pin for the SR MOSFET drain. This is a high voltage pin therefore particular care must be taken in properly routing the connection. An additional RC filter can be placed at this input to improve noise immunity, however only small values (e.g. 100Ω + 100pF) may be used to avoid introducing significant delay to the control input. GATE: Gate Drive Output The gate drive output provides 1A source and 2.5A sink current capability. Although this output may be directly connected to the power MOSFET gate the use of a minimal gate resistor is recommended, especially when using multiple MOSFETs in parallel. Care must be taken to keep the gate loop as short and as small as possible in order to minimize inductance and achieve optimal switching performance. 9 2016-07-01 IR1161LPBF Application Information and Additional Details State Diagram POWER ON Gate Inactive UVLO MODE VCC < VCC on ICC < ICC start Gate Inactive VCC > VCCon, & VDS>VTH3 VCC < VCCuvlo NORMAL Gate Active Gate PW ≥ MOT Cycle by Cycle MOT Check Enabled VDS>VTH1 @ MOT VDSVTH1 at the end of MOT Disable the next gate output Figure 7: MOT Protection Mode 14 2016-07-01 IR1161LPBF Synchronized Enable Function This function guarantees that the GATE drive always switches high at the beginning of a switching cycle. This is essential since mid-cycle switch on with the MOT function would force the MOSFET to remain on past the conduction period leading to reverse conduction. This function works in both Flyback and resonant half-bridge topologies. Figure 8 is an example in resonant halfbridge converter. VGATE VDS UVLO Idrain Vth3 IC activated in the middle of a conduction cycle, VGATE stays low. The first GATE pulse is blanked. Enable MOT protection. VD exceeds Vth3 for 2 cycles Vgate has output from the 4th cycle Figure 8: Synchronized Enable Function (resonant half-bridge) Driving a Logic Level MOSFET An external gate drive pull down circuit is recommended when driving a logic level MOSFET. This is because during power up and power down the drain may be switching while the IR1161 remains in UVLO. SR MOSFET drain to gate capacitance causes voltage pulses to appear at the gate that could have sufficient amplitude to reach the turn on threshold because the IR1161 gate sink capability is limited when VCC < 2V. The following circuit ensures that the gate voltage remains below 1V under all conditions: GATE VCC GND 2 MOT 3 Dg Rg 5 IR1161 CVcc 1 SR MOSFET VD 4 Qsink RMOT Rb Figure 9: Gate drive circuit for logic level SR MOSFET 15 2016-07-01 IR1161LPBF Vcc Clamping Circuit The IR1161 can be directly biased by the converter output voltage VOUT if this falls within the recommended range of Vcc although a low value series resistor may be required for optimal noise filtering. For higher system output voltages a clamping circuit is recommended to limit Vcc. This also lowers the gate drive voltage and reduces losses if VOUT is above 15V. Many clamping circuits are available from simple zener diode clamping to bipolar linear regulators. Figure 10 is one example; in this circuit the Vcc voltage will be clamped to a voltage of VOUT - VZD1 - VBE. The circuit also provides turn-on delay to the IR1161, which will activate only when the output voltage exceeds VCCON + VZD1 + VBE. R1 and R2 are optional for more precise control of the Vcc clamping voltage. Vout Optional R1 ZD1 GATE VCC R3 CVcc GND 2 MOT 3 5 IR1161 R2 1 VD 4 Figure 10: Vcc clamping circuit Shutdown Circuit The IR1161 can be disabled by pulling VCC below the VCC UVLO threshold. Vout R1 ZD1 GATE VCC Shutdown GND 2 MOT 3 5 IR1161 R3 CVcc 1 VD 4 Figure 11: IR1161 Enable/Disable circuit 16 2016-07-01 IR1161LPBF General Timing Waveform VTH1 VDS VTH2 t Don t Doff VGate 90% 10% t rise tfall Figure 12: Timing waveform 17 2016-07-01 IR1161LPBF IQCC 4.7 4.6 4.5 4.4 VCC ON VCC UVLO 4.3 -50 °C 0 °C 50 °C 100 °C Temperature Icc @300KHz, CLOAD=1nF 0.50 -50 °C 0 °C 50 °C 100 °C 150 °C Figure 14: Icc Quiescent Current vs. Temperature ICC START 12.0 ICC Startup Current (uA) ICC Supply Current (mA) 0.55 13.0 5.4 11.0 5.3 5.2 10.0 5.1 5.0 4.9 4.8 4.7 0 °C 50 °C 100 °C 150 °C Temperature Figure 15: Icc Supply Current @1nF Load vs. Temperature 18 0.60 Temperature 5.5 4.6 -50 °C 0.65 150 °C Figure 13: Undervoltage Lockout vs. Temperature 5.6 IQCC Quiescent Current (mA) VCC UVLO Thresholds (V) 0.70 9.0 8.0 7.0 6.0 -50 °C 0 °C 50 °C 100 °C 150 °C Temperature Figure 16: Icc Startup Current vs. Temperature 2016-07-01 IR1161LPBF -2.0 -200.0 -210.0 VTH2 Thresholds (mV) VTH1 Threshold (mV) -3.0 -4.0 -5.0 -220.0 -230.0 -240.0 -250.0 -6.0 -50 °C -260.0 -50 °C 0 °C 50 °C 100 °C Temperature 0 °C 150 °C 50 °C 100 °C 150 °C Temperature Figure 17: VTH1 vs. Temperature Figure 18: VTH2 vs. Temperature 3 1.20 RMOT=100k RMOT=50k RMOT=24k Minimum On Time (us) VTH3 Thresholds (V) 1.18 1.16 1.14 2 1 1.12 1.10 -50 °C 0 °C 50 °C 100 °C Temperature Figure 19: VTH3 vs. Temperature 19 150 °C 0 -50 °C 0 °C 50 °C 100 °C Temperature 150 °C Figure 20: MOT Time vs. Temperature 2016-07-01 IR1161LPBF 13.5 30 ns Tr and Tf time at 1nF load Blanking Time (us) 25 ns 13.0 12.5 12.0 -50 °C 0 °C 50 °C 100 °C Temperature 20 ns 15 ns 10 ns 0 ns -50 °C 150 °C 0 °C Tf 50 °C 100 °C 150 °C Temperature Figure 22: Tr and Tf vs. Temperature Figure 21: Blanking Time vs. Temperature 75 ns 14 70 ns 12 65 ns Resistance (Ω) Propagation Delay Tr 5 ns 60 ns 55 ns 50 ns 10 8 6 Rup Rdown 4 45 ns Turn-on Propagation Delay 40 ns 2 Turn-off Propagation Delay 35 ns -50 °C 0 °C 50 °C 100 °C 150 °C Temperature Figure 23: TDON and TDOFF vs. Temperature 20 0 -50 °C 0 °C 50 °C 100 °C Temperature 150 °C Figure 24: RUP and RDOWN vs. Temperature 2016-07-01 IR1161LPBF Package Details: 5 Lead SOT23 21 2016-07-01 IR1161LPBF Tape and Reel Details: 5 Lead SOT23 22 2016-07-01 IR1161LPBF Tape and Reel Details: 5 Lead SOT23 23 2016-07-01 IR1161LPBF Part Marking Information: 5 Lead SOT23 Top Marking YW LC Lot Code Date Code Bottom Marking G IR Logo Part no. 24 2016-07-01 IR1161LPBF Qualification Information† †† Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial Comments: This family of ICs has passed JEDEC’s Industrial qualification. Infineon’s Consumer qualification level is granted by extension of the higher Industrial level. ††† MSL1 SOT-23 5L (per IPC/JEDEC J-STD-020) Class A (per JEDEC standard JESD22-A115) Class 1A (per EIA/JEDEC standard EIA/JESD22-A114) Class I, Level A (per JESD78) Yes † †† Qualification standards can be found at Infineon’s web site www.infineon.com Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for further information. 25 2016-07-01 IR1161LPBF Revision History Major changes since the last revision Date Description of change June 1, 2015 First release May 24, 2016 Changed MSL to level 1. July 1, 2016 Changed format template with Infineon logo Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2015 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 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