IR21364SPBF

IR21364(S&J)PBF 3-PHASE BRIDGE DRIVER Features              Product Summary Floating channel designed for bootstrap operation Tolerant to negative transient voltage – dV/dt immune Gate drive supply range from 11.5 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent 3 half-bridge drivers Matched propagation delay for all channels Cross-conduction prevention logic Low side and High side outputs in phase with inputs. 3.3 V logic compatible Lower di/dt gate drive for better noise immunity Externally programmable delay for automatic fault clear RoHS Compliant Typical Applications     Topology ≤ 600 V VOFFSET 11.5 V – 20V VOUT IO+ & IO(typical) tON & tOFF (typical) 200 mA & 350 mA 500 ns & 530 ns Package Options Motor Control Air Conditioners/ Washing Machines General Purpose Inverters Micro/Mini Inverter Drives 28-Lead SOIC www.irf.com 3 phase bridge driver 1 44-Lead PLCC w/o 12 Leads May 31, 2016 IR21364(S&J)PBF Description The IR21364(S&J)PBF is a high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels for 3-phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive Nchannel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. † Qualification Information †† Industrial Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. Qualification Level ††† SOIC28W MSL3 , 260C (per IPC/JEDEC J-STD-020) PLCC44 MSL3 , 245C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level ††† Class 2 (per JEDEC standard JESD22-A114) Human Body Model ESD Class B (per EIA/JEDEC standard EIA/JESD22-A115) Machine Model Class I, Level A (per JESD78) Yes IC Latch-Up Test RoHS Compliant † †† ††† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com 2 May 31, 2016 IR21364(S&J)PBF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VS High side offset voltage Max VB High side floating supply voltage High side floating output voltage VCC Low side and logic fixed supply voltage VSS Logic ground -0.3 625 VS1,2,3 - 0.3 VB 1,2,3 + 0.3 Low side output voltage -0.3 25 VCC - 25 VCC + 0.3 -0.3 VCC + 0.3 lower of VCC + 0.3 or Vss+15 VCC + 0.3 VIN Input voltage LIN, HIN, ITRIP, EN, RCIN VSS -0.3 VFLT FAULT output voltage VSS -0.3 dV/dt Allowable offset voltage slew rate PD RthJA Units VB 1,2,3 - 25 VB 1,2,3 + 0.3 VHO VLO1,2,3 Min — 50 Package power dissipation @ TA ≤ +25 °C (28 lead SOIC) — 1.6 (44 lead PLCC) — 2.0 Thermal resistance, junction to ambient (28 lead SOIC) — 78 (44 lead PLCC) — 63 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The V S & VSS offset rating are tested with all supplies biased at a 15 V differential. Symbol Definition VB1,2,3 VS 1,2,3 VCC VHO 1,2,3 High side floating supply voltage High side floating supply voltage Low side supply voltage High side output voltage VLO1,2,3 IR21364 IR21364 Min. Max. VS1,2,3 +11.5 Note 1 11.5 VS1,2,3 VS1,2,3 + 20 600 20 VB1,2,3 Low side output voltage 0 VCC VSS Logic ground -5 5 VFLT FAULT output voltage VSS VCC VRCIN RCIN input voltage VSS VCC Units V VITRIP VIN TA ITRIP input voltage VSS VSS + 5 Logic input voltage LIN, HIN, EN VSS VSS + 5 -40 Ambient temperature 125 °C Note 1: Logic operational for VS of COM -5 V to COM + 600 V. Logic state held for VS of COM -5 to COM – VBS. (Please refer to the Design Tip DT97 -3 for more details). www.irf.com 3 May 31, 2016 IR21364(S&J)PBF Static Electrical Characteristics VBIAS (VCC, VBS 1,2,3) = 15 V, TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V O and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. Symbol Definition Min Typ Max Units VIH Logic “0” input voltage — — VIL 0.8 Logic “1” input voltage 2.5 — — VEN,TH+ Enable positive going threshold — — 2.5 VEN,TH- Enable negative going threshold 0.8 — — VIT,TH+ ITRIP positive going threshold 0.37 0.46 0.55 VIT,HYS ITRIP hysteresis — 0.07 — VRCIN, TH+ RCIN positive going threshold — 8 — VRCIN, HYS RCIN hysteresis — 3 — VOH High level output voltage, VBIAS - VO — 0.9 1.4 VOL Low level output voltage, VO — 0.4 0.6 IR21364 9.6 10.4 11.2 IR21364 8.6 9.4 10.2 IR21364 — 1 — IR21364 9.6 10.4 11.2 IR21364 8.6 9.4 10.2 IR21364 — 1 — — — 50 VCCUV+ VCCUVVCCUVHY VBSUV+ VBSUVVBSUVHY llk VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage hysteresis Offset supply leakage current Quiescent VBS supply current — 70 120 IQCC ILIN+ ILINIHIN+ IHINIITRIP+ IITRIPIEN+ IEN- Quiescent VCC supply current Input bias current (LOUT = HI) Input bias current (LOUT = LO) Input bias current (HOUT = HI) Input bias current (HOUT = LO) “High” ITRIP input bias current “Low” ITRIP input bias current “High” ENABLE input bias current “Low” ENABLE input bias current — — -1 — -1 — -1 — -1 0.6 100 — 100 — 3.3 — 100 — 1.3 195 — 195 — 6 — — — IRCIN RCIN input bias current — — 1 Io+ Output high short circuit pulsed current 120 200 — Io- Output low short circuit pulsed current 250 350 — — — 50 50 100 100 IQBS Ron_RCIN Ron_FAULT www.irf.com RCIN low on resistance FAULT low on resistance 4 Test Conditions V µA mA µA Io = 20 mA VB = VS = 600 V VB1,2,3 = VS1,2,3 = 600 V VIN = 0 V or 5 V VLIN = 3.3 V VLIN = 0 V VHIN = 3.3 V VHIN = 0 V VITRIP = 3.3 V VITRIP = 0 V VEN = 3.3 V VEN = 0 V Vrcin = 0 V or 15 V mA Vo = 0 V, PW ≤ 10 µs Vo = 15 V, PW ≤ 10 µs Ω I = 1.5 mA May 31, 2016 IR21364(S&J)PBF Dynamic Electrical Characteristics Dynamic Electrical Characteristics VCC = VBS = VBIAS = 15 V, VS1,2,3 = VSS = COM, TA = 25°C and CL = 1000 pF unless otherwise specified. Symbol t on t off t r t f Definition Min Typ Max Units Turn-on propagation delay 350 500 650 Turn-off propagation delay Turn-on rise time 375 — 530 125 685 190 Test Conditions VIN = 0 V & 5 V Turn-off fall time ENABLE low to output shutdown propagation delay ITRIP to output shutdown propagation delay — 50 75 300 450 600 VIN, VEN = 0 V or 5 V 500 750 1000 VITRIP = 5 V ITRIP blanking time 100 150 — tFLT ITRIP to FAULT propagation delay 400 600 800 tFILIN Input filter time (HIN, LIN) 100 200 — tfilterEn Enable input filter time 100 200 — Deadtime Ton, off matching time (on all six channels) 220 — 290 — 360 75 DT matching (Hi->Lo & Lo->Hi on all channels) pulse width distortion (pwin-pwout) — — — — 70 75 FAULT clear time RCIN: R = 2 MΩ, C = 1 nF 1.3 1.65 2 tEN tITRIP tbl DT MT MDT PM tFLTCLR www.irf.com 5 ns VIN = 0 V or 5 V VITRIP = 5 V VIN = 0 V & 5 V External dead time >450 nsec ms PW input =10 µs VIN = 0 V or 5 V VITRIP = 0 V May 31, 2016 IR21364(S&J)PBF HIN1,2,3 LIN1,2,3 EN ITRIP FAULT RCIN HO1,2,3 LO1,2,3 Fig. 1. Input/Output Timing Diagram LIN1,2,3 HIN1,2, 3 50% 50% 50% EN PWIN ten HO1,2,3 LO1,2,3 ton t r PW 90% HO1,2,3 LO1,2,3 50 % tof f t f 90% OUT 10% 10% Fig. 2. Switching Time Waveforms www.irf.com 90% Fig. 3. Output Enable Timing Waveform 6 May 31, 2016 IR21364(S&J)PBF HIN1,2,3 50% LIN1,2,3 50% 50% 50% LO1,2,3 DT HO1,2,3 50% Fig. 4. Internal Deadtime Timing Waveforms RCIN 50% 50% ITRIP FAULT 50% tflt 50% 90% Any Ouput tfltclr titrip Fig. 5. ITRIP/RCIN Timing Waveforms tin,fi tin,fi l l on HIN/LI N off off on on off high lo w Fig. 6. Input Filter Function www.irf.com 7 May 31, 2016 IR21364(S&J)PBF Lead Definitions Symbol Description VCC Low side supply voltage VSS Logic ground HIN1,2,3 Logic inputs for high side gate driver outputs (HO1,2,3), in phase LIN1,2,3 Logic input for low side gate driver outputs (LO1,2,3), in phase Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-drain output Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions When ENABLE is high. No effect on FAULT and not latched Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time T FLTCLR, then automatically becomes inactive (open-drain high impedance). External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C. When RCIN > 8 V, the FAULT pin goes back into open-drain high-impedance Low side gate drivers return High side floating supply FAULT EN ITRIP RCIN COM VB1,2,3 HO1,2,3 High side gate driver outputs VS1,2,3 High voltage floating supply return HIN1 HO1 27 3 HIN2 VS1 26 4 HIN3 25 LIN1 VB2 24 VS1 2 HO1 28 VB1 VB1 VCC VCC HIN1 1 HIN2 Low side gate driver outputs HIN3 LO1,2,3 6 5 4 3 43 42 41 7 5 6 LIN2 HO2 23 7 LIN3 VS2 22 8 FAULT 9 ITRIP VB3 20 EN HO3 19 LIN1 8 LIN2 9 37 VB2 LIN3 10 36 HO2 11 35 VS2 15 31 VB3 EN 16 30 HO3 RCIN 17 29 VS3 21 FAULT 12 13 12 VSS 13 COM LO1 16 14 LO3 LO2 15 VS3 18 17 19 VSS 18 20 21 22 23 24 25 LO1 RCIN LO2 11 14 LO3 ITRIP COM 10 28 Lead SOIC (wide body) 44 Lead PLCC w/o 12 leads IR21364S IR21364J www.irf.com 8 May 31, 2016 IR21364(S&J)PBF Functional Block Diagram IR21364 INPUT NOISE FILTER HIN1 DEADTIME & SHOOT- THROUGH PREVENTION INPUT NOISE FILTER LIN1 VB1 VSS/COM LEVEL SHIFTER HV LEVEL SHIFTER SET LATCH RESET UV DETECT DRIVER HO1 VS1 VB2 HIN2 INPUT NOISE FILTER LIN2 INPUT NOISE FILTER HIN3 INPUT NOISE FILTER DEADTIME & SHOOT- THROUGH PREVENTION VSS/COM LEVEL SHIFTER HV LEVEL SHIFTER SET RESET LATCH UV DETECT DRIVER HO2 VS2 VB3 DEADTIME & SHOOT- THROUGH PREVENTION INPUT NOISE FILTER LIN3 VSS/COM LEVEL SHIFTER HV LEVEL SHIFTER SET RESET LATCH UV DETECT DRIVER VSS HO3 VS3 VCC INPUT NOISE FILTER EN UV DETECT VSS/COM LEVEL SHIFTER INPUT NOISE FILTER ITRIP 0.5 V S R SET DOMINANT LATCH DELAY DRIVER LO1 DELAY DRIVER LO2 DELAY DRIVER LO3 Q VSS/COM LEVEL SHIFTER RCIN VSS/COM LEVEL SHIFTER FAULT COM VCC VBS ITRIP ENAB LE FAULT LO1,2,3 HO1,2,3 UVCC, FAULT return to high impedance. Note 3: When ITRIP