IR3500
DATA SHEET
XPHASE3TM VR11.0 & AMD PVID CONTROL IC
DESCRIPTION
TM
The IR3500 Control IC combined with an xPHASE3 Phase IC provides a full featured and flexible way to
implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system
control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a
TM
multiphase converter. The XPhase3
architecture implements a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
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1 to X phase operation with matching Phase IC
VID Select pin configures AMD 5 or 6 bit PVID, Intel VR11 with/out startup to 1.1V Boot voltage
0.5% overall system set point accuracy
Programmable 250kHz to 9MHz Daisy-chain digital phase timing clock oscillator frequency provides a
per phase switching frequency of 250kHz to 1.5MHz without external components
Programmable Dynamic VID Slew Rate
Programmable VID Offset or No Offset
Programmable Load Line Output Impedance
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us
Programmable converter current limit during soft start, hiccup with delay during normal operation
Central over voltage detection with programmable threshold and communication to phase ICs
Over voltage signal output to system with overvoltage detection during powerup and normal operation
Detection and protection of open remote sense line and open control loop
IC bias linear regulator control with programmable output voltage and UVLO
Programmable VRHOT function monitors temperature of power stage through a NTC thermistor
Remote sense amplifier with true converter voltage sensing and less than 50uA bias current
Simplified VR Ready output provides indication of proper operation and avoids false triggering
Small thermally enhanced 32L 5mm x 5mm MLPQ package
Optional
To Converter
FUSE
Q1
12V
VCCL
RVCCLFB1
RVCCLFB2
RVCCLDRV
CVCCL
4.7uF
ROVP1
Q3
SCR
Q2
ROVP2
VR READY
CLKOUT
26
25
27
PHSIN
29
31
30
28
VCCL
PHSOUT
OCSET
VSETPT
EAOUT
VDRP
24
23
22
21
20
19
ROSC
CSS/DEL
RVDAC
CVDAC
6 Wire
Bus to
Phase
ICs
ROCSET
RVSETPT
VDAC
CDRP
RCP
18
17
16
ENABLE
FB
IIN
15
VID0
VO
VID1
14
8
VCCLFB
7
VID0
VDAC
VID2
VOSEN+
VID1
VID3
VOSEN-
6
IR3500
CONTROL
IC
VID4
13
VID2
SS/DEL
12
5
VCCLDRV
VID3
VID5
HOTSET
4
VRRDY
VID4
ROSC / OVP
VRHOT
3
LGND
VID6
ENABLE
VID5
VID7
9
2
11
1
VID6
10
VID7
VIDSEL
32
VIDSEL
VRHOT
RFB1
RTHERMISTOR2
CFB
RHOTSET2
RFB
RDRP
CCP
CCP1
RTHERMISTOR1
VCC SENSE +
To Load
RHOTSET1
Close to
Power Stage
VSS SENSE VCCL
RFB2
Figure 1 – Application Circuit
Page 1 of 47
May 18, 2009
IR3500
ORDERING INFORMATION
Device
Package
Order Quantity
IR3500MTRPBF
32 Lead MLPQ
3000 per reel
(5 x 5 mm body)
* IR3500MPBF
32 Lead MLPQ
*Samples only
(5 x 5 mm body)
100 piece strips
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed below may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
o
o
Operating Junction Temperature…………….. 0 C to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VID7-0
ENABLE
VRHOT
HOTSET
VOSENVOSEN+
VO
FB
EAOUT
VDRP
IIN
VSETPT
OCSET
VDAC
SS/DEL
ROSC/OVP
7.5V
3.5V
7.5V
7.5V
1.0V
7.5V
7.5V
7.5V
7.5V
7.5V
7.5V
3.5V
7.5V
3.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
1mA
1mA
1mA
1mA
5mA
5mA
5mA
1mA
25mA
35mA
100mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
50mA
1mA
1mA
1mA
25mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
1mA
1mA
24
LGND
n/a
n/a
20mA
1mA
25
26
27
CLKOUT
PHSOUT
PHSIN
7.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
100mA
10mA
1mA
100mA
10mA
1mA
28
VCCL
7.5V
-0.3V
1mA
20mA
29
VCCLFB
3.5V
-0.3V
1mA
1mA
30
VCCLDRV
10V
-0.3V
1mA
50mA
31
VRRDY
VCCL + 0.3V
-0.3V
1mA
20mA
32
VIDSEL
7.5V
-0.3V
5mA
1mA
Page 2 of 47
May 18, 2009
IR3500
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
o
o
4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ
ELECTRICAL SPECIFICATIONS
The electrical characteristics involve the spread of values guaranteed within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C. CSS/DEL = 0.1µF +/-10%.
PARAMETER
VDAC Reference
System Set-Point Accuracy
(Deviation from Tables 2 & 4
per test circuit in Fig.3 and
Table 3 per test circuit in Fig.2)
Source & Sink Currents
VR11 VIDx Input Threshold
AMD VIDx Input Threshold
VR11 VIDx Input Bias Current
AMD 6-bit VIDx Pull-down
Resistance
VIDx OFF State Blanking Delay
VIDSEL Threshold between
AMD 5-bit VID and AMD 6-bit
VID
VIDSEL Threshold between
AMD 6-bit VID and VR11 with
Boot Voltage
VIDSEL Threshold between
VR11 with/out Boot Voltage
VIDSEL Float Voltage
VIDSEL Pull-up Resistance
Oscillator
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
PHSOUT Frequency
PHSOUT Frequency
PHSOUT Frequency
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
Page 3 of 47
TEST CONDITION
MIN
TYP
MAX
UNIT
%
mV
mV
mV
µA
mV
V
VID ≥ 1V
0.8V ≤ VID < 1V
0.5V ≤ VID < 0.8V
0.3V ≤ VID < 0.5V
Include OCSET and VSETPT currents
Float VIDSEL or tie VIDSEL to VCCL
R(VIDSEL) = 6.49kΩ or connect
VIDSEL to LGND.
Float VIDSEL, or connect VIDSEL to
VCCL or LGND. 0V≤V(VIDx)≤2.5V.
R(VIDSEL) = 6.49kΩ
-0.5
-5
-8
-8
30
500
0.85
44
600
1.00
0.5
5
8
8
58
700
1.15
-1
0
1
µA
100
175
250
kΩ
Measure time till VRRDY drives low
Note 3.
0.5
0.48
1.3
0.6
2.1
0.75
µs
V
84
87
90
%
2.97
3.30
3.63
V
77
83
89
%
2.5
3.5
4.5
KΩ
0.570
0.595
0.620
1
V
V
225
450
1.35
250
500
1.50
1
275
550
1.65
1
V
kHz
kHz
MHz
V
1
70
V
%
Relative to VIDSEL float voltage.
Note 3.
Note 3.
Relative to VIDSEL Threshold between
VR11 with/out Boot Voltage
I(CLKOUT)= -10 mA, measure V(VCCL)
– V(CLKOUT).
I(CLKOUT)= 10 mA
ROSC = 50.0 KΩ
ROSC = 24.5 KΩ
ROSC = 7.75 KΩ
I(PHSOUT)= -1 mA, measure V(VCCL)
– V(PHSOUT)
I(PHSOUT)= 1 mA
Compare to V(VCCL)
30
50
May 18, 2009
IR3500
PARAMETER
Soft Start and Delay
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
VRRDY Delay (TD4 + TD5)
OC Delay Time
SS/DEL to FB Input Offset
Voltage
Charge Current
Discharge Current
Charge/Discharge Current Ratio
Charge Voltage
Delay Comparator Threshold
Delay Comparator Threshold
TEST CONDITION
To reach 1.1V
V(IIN) – V(OCSET) = 500 mV
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Relative to Charge Voltage, SS/DEL
rising
Relative to Charge Voltage, SS/DEL
falling
Delay Comparator Hysteresis
VID Sample Delay Comparator
Threshold
Discharge Comp. Threshold
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Source Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Slew Rate
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Note1
VOSEN+ Bias Current
0.5 V < V(VOSEN+) < 1.6V
VOSEN- Bias Current
-0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes
VOSEN+ Input Voltage Range
V(VCCL)=7V
High Voltage
V(VCCL) – V(VO)
Low Voltage
V(VCCL)=7V
Error Amplifier
Input Offset Voltage
Measure V(FB) – V(VSETPT). Note 2
FB Bias Current
VSETPT Bias Current
ROSC= 24.5 KΩ
DC Gain
Note 1
Bandwidth
Note 1
Slew Rate
Note 1
Sink Current
Source Current
Page 4 of 47
MIN
TYP
MAX
UNIT
1.0
0.8
0.3
0.5
75
0.7
2.9
2.2
1.2
1.2
125
1.4
3.5
3.25
3.0
2.3
300
1.9
ms
ms
ms
ms
us
V
35.0
2.5
10
3.6
50
52.5
4.5
12
4.0
80
70.0
6.5
16
4.2
125
µA
µA
µA/µA
V
mV
85
120
160
mV
10
2.8
30
3.0
60
3.2
mV
V
150
200
250
mV
3.0
-3
0.5
2
2
6.4
0
1.0
12
4
9.0
3
1.7
18
8
MHz
mV
mA
mA
V/us
30
30
50
50
5.5
1
250
uA
uA
V
V
mV
1
1
25.50
120
40
20
1.00
12
mV
0.5
-1
-1
23.00
100
20
7
0.40
5
0
0
24.25
110
30
12
0.85
8
May 18, 2009
µA
µA
dB
MHz
V/µs
mA
mA
IR3500
PARAMETER
Minimum Voltage
Maximum Voltage
Open Voltage Loop Detection
Threshold
Open Voltage Loop Detection
Delay
Enable Input
VR 11 Threshold Voltage
VR 11 Threshold Voltage
VR 11 Hysteresis
AMD Threshold Voltage
AMD Threshold Voltage
AMD Hysteresis
Bias Current
Blanking Time
TEST CONDITION
MIN
Measure V(VCCL) – V(EAOUT)
Measure V(VCCL) - V(EAOUT),
Relative to Error Amplifier maximum
voltage.
Measure PHSOUT pulse numbers from
V(EAOUT) = V(VCCL) to VRRDY = low.
500
125
ENABLE rising
ENABLE falling
825
775
25
1.1
1.05
30
-5
75
850
800
50
1.2
1.14
50
0
250
875
825
75
1.3
1.23
80
5
400
mV
mV
mV
V
V
mV
-30
23.25
-13
24.50
4096
2048
1024
0
25.75
mV
-10
0.50
35
0.75
0
1.00
55
2.00
10
1.75
75
3.00
ENABLE rising
ENABLE falling
0V ≤ V(ENABLE) ≤ 3.3V
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
Over-Current Comparator
Input Offset Voltage
1V ≤ V(OCSET) ≤ 3.3V
OCSET Bias Current
ROSC= 24.5 KΩ
Over-Current Delay Counter
ROSC = 7.75 KΩ (PHSOUT=1.5MHz)
Over-Current Delay Counter
ROSC = 15.0 KΩ (PHSOUT=800kHZ)
Over-Current Delay Counter
ROSC = 50.0 KΩ (PHSOUT=250kHz)
Over-Current Limit Amplifier
Input Offset Voltage
Transconductance
Note 1
Sink Current
Unity Gain Bandwidth
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
Threshold during Normal
Compare to V(VDAC)
Operation
OVP Release Voltage during
Compare to V(VDAC)
Normal Operation
Threshold during Dynamic VID
down
Dynamic VID Detect
Comparator Threshold
Propagation Delay to IIN
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(IIN) transition to
> 0.9 * V(VCCL).
IIN Pull-up Resistance
Propagation Delay to OVP
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(ROSC/OVP)
transition to >1V.
OVP High Voltage
Measure V(VCCL)-V(ROSC/OVP)
OVP Power-up High Voltage
V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP)
Page 5 of 47
TYP
120
780
300
MAX
250
950
600
8
UNIT
mV
mV
mV
Pulses
µA
ns
µA
Cycle
Cycle
Cycle
mV
mA/V
uA
kHz
1.60
105
1.73
125
1.83
145
V
mV
-13
3
20
mV
1.70
1.73
1.75
V
25
50
75
mV
90
180
ns
5
90
0
0
15
300
Ω
ns
1.2
0.2
V
V
May 18, 2009
IR3500
PARAMETER
VDRP Buffer Amplifier
Input Offset Voltage
Source Current
Sink Current
Unity Gain Bandwidth
Slew Rate
IIN Bias Current
VRRDY Output
Output Voltage
Leakage Current
Open Sense Line Detection
Sense Line Detection Active
Comparator Threshold Voltage
Sense Line Detection Active
Comparator Offset Voltage
VOSEN+ Open Sense Line
Comparator Threshold
VOSEN- Open Sense Line
Comparator Threshold
Sense Line Detection Source
Currents
VRHOT Comparator
Threshold Voltage
HOTSET Bias Current
Hysteresis
Output Voltage
VRHOT Leakage Current
VCCL Regulator Amplifier
Reference Feedback Voltage
VCCLFB Bias Current
VCCLDRV Sink Current
UVLO Start Threshold
UVLO Stop Threshold
Hysteresis
General
VCCL Supply Current
TEST CONDITION
V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V
0.5V ≤ V(IIN) ≤ 3.3V
0.5V ≤ V(IIN) ≤ 3.3V
Note 1
Note 1
MIN
TYP
MAX
UNIT
-7
2
0.2
0
7
30
0.6
mV
mA
mA
MHz
V/µs
µA
-1
I(VRRDY) = 4mA
V(VRRDY) = 5.5V
V(VO) < [V(VOSEN+) – V(LGND)] / 2
Compare to V(VCCL)
V(VO) = 100mV
1
150
0
300
10
150
200
250
mV
35
60
85
mV
87.5
90.0
92.5
%
0.36
0.40
0.44
V
200
500
700
uA
1.584
-1
75
1.600
0
100
150
0
1.616
1
125
400
10
V
µA
mV
mV
1.15
-1
10
90
82
7
1.19
0
30
94
86
8.25
1.23
1
98
90
9.5
V
uA
mA
%
%
%
3.0
6.5
10.0
mA
I(VRHOT) = 30mA
V(VRHOT) = 5.5V
Compare to V(VCCL)
Compare to V(VCCL)
Compare to V(VCCL)
0.4
8
4.7
0
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors
Note 3: See VIDSEL Functionality Table
Page 6 of 47
May 18, 2009
mV
µA
µA
IR3500
SYSTEM SET POINT TEST
IR3500
ERROR
AMPLIFIER
VDAC
BUFFER
AMPLIFIER
EAOUT
1k
+
-
FB
+
VSETPT
ISOURCE
FAST
VDAC
RVDAC
VDAC
ISINK
OCSET ROCSET
-
IVDAC
IOCSET
IVSETPT
IROSC
IROSC
ROSC BUFFER
AMPLIFIER
0.6V
LGND
+
CURRENT
SOURCE
GENERATOR
CVDAC
IROSC
ROSC
ROSC
VO
EAOUT
SYSTEM
SET POINT
VOSNSVOLTAGE
REMOTE SENSE
AMPLIFIER
VOSEN+
+
VOSEN-
-
Figure 2 - System Set Point Test Circuit for VR11 VID
IR3500
ERROR
AMPLIFIER
VDAC
BUFFER
AMPLIFIER
EAOUT
+
-
FB
+
VSETPT RVSETPT
ISOURCE
FAST
VDAC
1k
VDAC
RVDAC
OCSET
ISINK
ROCSET
-
IVDAC
IOCSET
IVSETPT
IROSC
CVDAC
ROSC BUFFER
AMPLIFIER
0.6V
LGND
+
IROSC
CURRENT
SOURCE
GENERATOR
IROSC
ROSC
ROSC
VO
EAOUT
SYSTEM
SET POINT
VOSNSVOLTAGE
REMOTE SENSE
AMPLIFIER
VOSEN+
VOSEN-
+
-
Figure 3 - System Set Point Test Circuit for AMD VIDs (VDAC shifted +50 mV)
Page 7 of 47
May 18, 2009
IR3500
PIN DESCRIPTION
PIN#
1-8
9
PIN SYMBOL
VID7-0
ENABLE
10
VRHOT
11
HOTSET
12
13
14
15
16
17
VOSENVOSEN+
VO
FB
EAOUT
VDRP
18
IIN
19
VSETPT
20
OCSET
21
VDAC
22
SS/DEL
23
ROSC/OVP
24
25
LGND
CLKOUT
26
PHSOUT
27
28
PHSIN
VCCL
29
VCCLFB
Page 8 of 47
PIN DESCRIPTION
Inputs to VID D to A Converter.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float
this pin as the logic state will be undefined.
Open collector output of the VRHOT comparator which drives low if HOTSET pin
voltage is lower than 1.6V. Connect external pull-up.
A resistor divider including thermistor senses the temperature, which is used for
VRHOT comparator.
Remote sense amplifier input. Connect to ground at the load.
Remote sense amplifier input. Connect to output at the load.
Remote sense amplifier output.
Inverting input to the error amplifier.
Output of the error amplifier.
Buffered IIN signal. Connect an external RC network to FB to program converter
output impedance.
Average current input from the phase IC(s). This pin is also used to communicate
over voltage condition to phase ICs.
Error amplifier non-inverting input. Converter output voltage can be decreased from
the VDAC voltage with an external resistor connected between VDAC and this pin
(there is an internal sink current at this pin).
Programs the constant converter output current limit and hiccup over-current
thresholds through an external resistor tied to VDAC and an internal current source
from this pin. Over-current protection can be disabled by connecting a resistor from
this pin to VDAC to program the threshold higher than the possible signal into the IIN
pin from the phase ICs but no greater than VCCL – 2V (do not float this pin as
improper operation will occur).
Regulated voltage programmed by the VID inputs. Connect an external RC network
to LGND to program dynamic VID slew rate and provide compensation for the
internal buffer amplifier.
Programs converter startup and over current protection delay timing. It is also used
to compensate the constant output current loop during soft start. Connect an
external capacitor to LGND to program.
Connect a resistor to LGND to program oscillator frequency and OCSET, VSETPT
and VDAC bias currents. Oscillator frequency equals switching frequency per phase.
The pin voltage is 0.6V during normal operation and higher than 1.6V if over-voltage
condition is detected.
Local Ground for internal circuitry and IC substrate connection.
Clock output at switching frequency multiplied by phase number. Connect to CLKIN
pins of phase ICs.
Phase clock output at switching frequency per phase. Connect to PHSIN pin of the
first phase IC.
Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.
Output of the voltage regulator, and power input for clock oscillator circuitry. Connect
a decoupling capacitor to LGND.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by the resistor divider connected to VCCL.
May 18, 2009
IR3500
30
VCCLDRV
31
VRRDY
32
VIDSEL
Output of the VCCL regulator error amplifier to control external transistor. The pin
senses 12V power supply through a resistor.
Open collector output that drives low during startup and under any external fault
condition. Connect external pull-up.
The pin configures VIDs for AMD 6-bit, Intel VR11 8-bit with 1.1V Boot voltage, Intel
VR11 8-bit without 1.1V Boot voltage or AMD 5-bit Opteron.
SYSTEM THEORY OF OPERATION
PWM Control Method
TM
The PWM block diagram of the XPhase3 architecture is shown in Figure 4. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
GATE DRIVE
VOLTAGE
CONTROL IC
VIN
PHSOUT
PHASE IC
CLOCK GENERATOR
CLKOUT
VCC
CLKIN
CLK Q
VCCH
D
PHSOUT
1
PHSIN
1
PWM
COMPARATOR
CBST
SW
5
CLK Q
VOUT
COUT
-
EAIN
VCCL
+
GND
PWM LATCH
GATEL
ENABLE
+
REMOTE SENSE
AMPLIFIER
+
VID6
BODY
BRAKING
COMPARATOR
PGND
VOSNS-
-
-
-
LDO AMPLIFIER
+
RAMP
DISCHARGE
CLAMP
VO
VDAC
SHARE ADJUST
ERROR AMPLIFIER
EAOUT
ISHARE
-
CURRENT
SENSE
AMPLIFIER
VID6
VID6
-
+
+
-
3K
RCOMP
VID6
VID6 +
RFB1
RFB
+
CCOMP
FB
RVSETPT
IVSETPT
IROSC
VDRP
AMP
CSIN+
+
CCOMP1
CFB
RCS
CSIN-
DACIN
RDRP1
PHSOUT
PHASE IC
RDRP
VSETPT
CCS
-
VDAC
+
+
-
LGND
ERROR
AMPLIFIER
CDRP
VDRP
VCC
CLK Q
CLKIN
+
-
D
IIN
1
VCCH
RESET
DOMINANT
2
PHSIN
1
Q
CLK Q
GATEH
4
CBST
5
SW
R
2
D
3
PWM
COMPARATOR
EAIN
+
VCCL
PWM LATCH
ENABLE
+
VID6
-
RAMP
DISCHARGE
CLAMP
GATEL
BODY
BRAKING
COMPARATOR
PGND
-
+
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
VID6
VID6
+
CSIN+
VID6
VID6 +
+
DACIN
CCS
RCS
-
-
3K
+
ISHARE
CSIN-
Figure 4 - PWM Block Diagram
Page 9 of 47
VOSNS+
4
Q
R
2
D
3
PHSIN
GATEH
RESET
DOMINANT
2
May 18, 2009
IR3500
Frequency and Phase Timing Control
The oscillator and system clock frequency is programmable from 250kHz to 9MHZ by an external resistor (ROSC).
The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the
phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the
phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the
second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During
power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at
PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 5 shows the phase
timing for a four phase converter. The switching frequency is set by the resistor ROSC as shown in Figure 23. The
clock frequency equals the number of phase times the switching frequency.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 5 - Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is
set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is then
turned on after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage the
PWM latch is reset. This turns off the high side driver, then turns on the low side driver after the non-overlap time,
and activates the ramp discharge clamp. The ramp discharge clamp quickly discharges the PWM ramp capacitor to
the output voltage of the share adjust amplifier in the phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
Page 10 of 47
May 18, 2009
IR3500
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
An additional advantage of the architecture is that differences in ground or input voltage at the phases have no
effect on operation since the PWM ramps are referenced to VDAC. Figure 6 depicts PWM operating waveforms
under various conditions.
The error amplifier is a high speed amplifier with 110 dB of open loop gain. It is not unity gain stable.
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, OCP, VID FAULT)
STEADY-STATE
OPERATION
Figure 6 - PWM Operating Waveforms
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate
can be increased significantly. This patented method is referred to as “body braking” and is accomplished through
the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output
voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is,
Page 11 of 47
May 18, 2009
IR3500
vC ( s ) = vL ( s )
1
RL + sL
= iL ( s )
1 + sRCS CCS
1 + sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
c
vCS
CSOUT
Figure 7 - Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is
nominally 32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback
path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and
other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are
tied together and the voltage on the share bus represents the average current through all the inductors and is used
by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to
+/- 1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw / 896 in a multiphase architecture.
Page 12 of 47
May 18, 2009
IR3500
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current,
the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty
cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of
the current share loop is much slower than that of the voltage loop and the two loops do not interact.
IR3500 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3500 is shown in Figure 8, and specific features are discussed in the following sections.
VID Control
The AMD 6-bit VID, VR11 8-bit VID, and AMD Opteron 5-bit VID are shown in Tables 2 to 4 respectively, and are
selected by different connections of VIDSEL pin shown in Table 1. The VID pins require an external bias voltage
and should not be floated. The VID input comparators monitor the VID pins and control the Digital-to-Analog
Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC
pin. The VDAC voltage, input offsets of error amplifier and remote sense differential amplifier are post-package
trimmed to provide 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system
accuracy, which has a wider tolerance. VIDs of less than 0.5V are not supported.
The IR3500 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power
dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 9. The output
voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference voltage
can be programmed to have a constant DC offset bellow the VDAC by connecting RSETPT between VDAC and
VSETPT. The IVSETPT is controlled by the ROSC as shown in Figure 24.
The voltage at the VDRP pin is a buffered version of the share bus IIN and represents the sum of the DAC voltage
and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor
RDRP. Since the error amplifier will force the loop to maintain FB to be equal to the VSETPT, an additional current
will flow into the FB pin equal to (VDRP-VSETPT) / RDRP. When the load current increases, the adaptive positioning
voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage
lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the
droop impedance produces the desired converter output impedance. The offset and slope of the converter output
impedance are referenced to and therefore independent of the VDAC voltage.
Inductor DCR Temperature Compensation
A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation.
The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as
shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor.
Page 13 of 47
May 18, 2009
ENABLE
COMPARATOR
250nS
BLANKING
DELAY
COMPARATOR
POWER OK
LATCH
+
DISCHARGE
COMPARATOR
4.0V
-
-
0.94
1.19V
0.86
OC DELAY
RESET
R
SS RESET
+
VCCL OUTPUT
COMPARATOR
0.2V
8-Pulse
Delay
+
OPEN SENSE LINE
OPEN DAISY CHAIN
OPEN VOLTAGE LOOP
+
AMD 5-BIT
VID3
VID2
VID2
VID3
-
VID4
VID4
+
VID5
VID1
VID1AMD 1.0V
VID0
VID0
CLKOUT
VID0
3.2V
IDCHG
4.5uA
REMOTE SENSE
AMPLIFIER
DYNAMIC VID DETECT
COMPARATOR
25k
-
-
ISINK
-
25k
+
-
VDAC
VO
IVOSEN+
VOSENIVOSENIVOSEN-
DETECTION
VCCL
PULSE
RESET
VCCL
OPEN SENSE
LINE DETECT
COMPARATORS
VCCL*0.9
-
+
ROSC/OVP
VOSEN+
25k
VIDSEL
-
CURRENT
SOURCE
GENERATOR
OPEN SENSE
LINE DETECT
COMPARATORS
+
+
ROSC BUFFER
AMPLIFIER
ISOURCE
OV@START
+
25k
VO
+
200mV
OPEN SENSE LINE
OV FAULT
R
-
60mV
Q
ENABLE 0.4V
+
IR3500
May 18, 2009
IROSC
VDAC BUFFER
AMPLIFIER
S
SET
DOMINANT
POWER-UP OV
1.73V COMPARATOR
+
IROSC
OV@OPERATION
OV@START
OV@OPERATION
VCCL UVLO
1.6V
PHSOUT
PHSIN
VCCLDRV
OV FAULT
LATCH
Q
50mV
0.6V
ISETPT
+
PHSIN
LGND
VSETPT
IROSC
PULSE
OPEN DAISY
CHAIN
VCCL-1.2V
EAOUT
FB
R
VDRP
DISABLE
OVER
130mV VOLTAGE
3mV
COMPARATOR DETECTION
S
FAULT
PHSOUT
SAMPLE DELAY
OV FAULT
FAST VDAC
VCCL UVLO
CLKOUT
VID SAMPLE
DELAY
FAULT LATCH1
COMPARATOR
VDAC
VID2
VID0
SOFT
START 1.4V
CLAMP
DIS
VID1
INTEL 0.6V
ERROR
AMPLIFIER
S
VR11 NoBOOT
R
VDRP AMPLIFIER
IOCSET
-
VID6
VID7
VID INPUT
VID6
COMPARATORS
VID5
(1/8 SHOWN)
IROSC
+
VID7
1.3uS
VID
BLANKING
FAULT
DIGITAL
VID7
VIDSEL VBOOT
TO ANALOG
LATCH
VID6
VID5
CONVERTER VBOOT
Q
S
VIDSEL(1.1V) SET
VID4
VBOOT
DOMINANT
VID3
INTERNAL DVID
OV@OPERATION
-
VIDSEL
R
VCCL
OV@START
OCSET
OC LIMIT
AMPLIFIER
+
3.5k
VR11 BOOT
1.6V
1.5V
Q
SET
DOMINANT
IIN
R
Q
SET
DOMINANT
AMD 6-BIT
+
+
VIDSEL
VIDSEL
VIDSEL
COMPARATORS
3.3V
VIDSEL
VIDSEL
VID FAULT
LATCH
LATCH
VCCL UVLO
OC LIMIT
COMPARATOR
-
EAOUT
-
Figure 8 - Block Diagram
0.86
S
-
-
0.6V
HOTSET
VRHOT
UV CLEARED
FAULT LATCH2
OC
1.08V
VCCL
VCCL UVLO
OC DELAY PHSOUT
COUNTER
SS/DEL
Float
Voltage
VRHOT COMPARATOR
R
IROSC
SAM PLE DELAY
+
VCCLFB
-
80mV
120mV
VCCL REGULATOR
AMPLIFIER
FAULT LATCH2
OV FAULT
SET
DOMINANT
SS RESET
S
Q
RESET
DOMINANT
Q
+
VCCLDRV
S
VID FAULT LATCH
VCCL UVLO
OC before VRRDY
+
AMD 1.2V
1.14V
VRRDY
POWER NOT OK
FAULT LATCH1
+
+
+
INTEL
850mV
800mV
SS CLEARED
FAULT LATCH1
OC after VRRDY
DISABLE
VID FAULT
-
-
-
VBIAS
+
Page 14 of 47
VCCL
ENABLE
IR3500
TABLE 1 - VIDSEL FUNCTIONALITY
VIDSEL
Connection
LGND ( 1.73V
Page 25 of 47
May 18, 2009
IR3500
12V
VCC
VCCL+0.7V
VCCL+0.7V
VCCLDRV
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VID + 0.13V
VCCL UVLO
VCCL - 1V
ROSC/OVP
0.6V
3.92V (4V-0.08V)
SS/DEL
Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V
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