IRLR8503

PD-93839C IRLR8503 IRLR8503 • • • • N-Channel Application-Specific MOSFET Ideal for CPU Core DC-DC Converters Low Conduction Losses Minimizes Parallel MOSFETs for high current applications HEXFET® MOSFET for DC-DC Converters D • 100% RG Tested Description This new device employs advanced HEXFET Power MOSFET technology to achieve very low on-resistance. The reduced conduction losses makes it ideal for high efficiency DC-DC converters that power the latest generation of microprocessors. G S D-Pak DEVICE RATINGS (MAX. Values) The IRLR8503 has been optimized and is 100% tested for all parameters that are critical in synchronous buck converters including RDS(on), gate charge and Cdv/dtinduced turn-on immunity. The IRLR8503 offers an extremely low combination of Qsw & RDS(on) for reduced losses in control FET applications. IRLR8503 The package is designed for vapor phase, infra-red, convection, or wave soldering techniques. Power dissipation of greater than 2W is possible in a typical PCB mount application. VDS RDS(on) QG QSW 30V 18 mΩ QOSS 29.5 nC 20 nC 8 nC Absolute Maximum Ratings Symbol IRLR8503 Drain-Source Voltage Parameter VDS 30 Gate-Source Voltage VGS ±20 Continuous Drain or Source Current TC = 25°C TC = 90°C c T Power Dissipation g T C = 25°C C = 90°C 62 PD TJ , TSTG Continuous Source Current (Body Diode) IS 15 Pulsed Source Current ISM 196 c A 32 196 30 -55 to 150 Junction & Storage Temperature Range V 44 ID IDM Pulsed Drain Current Units W °C A Thermal Resistance Parameter Maximum Junction-to-Ambient Maximum Junction-to-Lead www.irf.com h eh Symbol Typ Max RθJA ––– 50 RθJL ––– 2.0 Units °C/W 1 5/26/05 IRLR8503 Electrical Characteristics Parameter Symbol Drain-to-Source Breadown Voltage* V(BR)DSS Static Drain-Source On-Resistance* RDS(on) Gate Threshold Voltage* VGS(th) Drain-Source Leakage Current IDSS Gate-Source Leakage Current* Total Gate Charge, Control FET* Conditions Min Typ Max Units 30 ––– ––– ––– 11 16 ––– 1.0 13 ––– 18 3.0 ––– ––– 1.0 ––– ––– 150 IGSS ––– ––– ±100 Qg ––– 15 Total Gate Charge, Synch FET* Qg ––– Pre-Vth Gate-to-Source Charge Qgs1 ––– Post-Vth Gate-to-Source Charge Qgs2 ––– 1.3 ––– Gate-to-Drain Charge Qgd ––– 4.1 ––– Switch Charge* (Qgs2 + Qgd) QSW ––– 5.4 8 Output Charge* QOSS ––– 23 29.5 Gate Resistance RG 0.4 ––– 1.1 Turn-On Delay Time td(on) ––– 10 ––– Drain Voltage Rise Time trV ––– 18 ––– Turn-Off Delay Time td(off) ––– 11 ––– Drain Voltage Fall Time tfV ––– 3 ––– Input Capacitance Ciss ––– 1650 ––– Output Capacitance Coss ––– 650 ––– Reverse Transfer Capacitance Crss ––– 58 ––– V VGS = 0V, ID = 250µA mΩ VGS = 10V, ID = 15A VGS = 4.5V, 1D = 15A V VDS = VGS, ID = 250µA µA nA d VDS = 30V, VGS = 0 VDS = 24V, VGS = 0, TJ = 100°C VGS = ± 20V 20 VGS = 5V, ID = 15A, VDS = 16V 13 17 VGS = 5V, VDS < 100mV 3.7 ––– nC VDS = 16V, ID = 15A VDS = 16V, VGS = 0 Ω VDD = 16V, ID = 15A ns VGS = 5.0V Clamped Inductive Load See Test Diagram Fig. 14 VDS = 25V pF VGS = 0 Source-Drain Rating & Characteristics Parameter Diode Forward Voltage* Reverse Recovery Charge Reverse Recovery Charge (with Parallel Schottsky) f f Symbol Min Typ Max Units VSD ––– ––– 1.0 Qrr ––– 76 ––– Qrr(s) ––– 67 ––– V d Conditions IS = 15A , VGS = 0V di/dt = 700A/µs VDD = 16V, VGS = 0V, IS = 15A nC di/dt = 700A/µs (with 10BQ040) VDD = 16V, VGS = 0V, IS = 15A Notes:  ‚ ƒ „ Repetitive rating; pulse width limited by max. junction temperature. … Calculated continuous current based on maximum allowable Pulse width ≤ 300 µs; duty cycle ≤ 2%. Junction temperature; switching and other losses will When mounted on 1 inch square copper board, t < 10 sec. decrease RMS current capability; package limitation current = 20A. Typ = measured - Q oss † Rθ is measured at TJ approximately at 90°C *Devices are 100% tested to these parameters. 2 www.irf.com IRLR8503 Power MOSFET Optimization for DC-DC Converters While the IRLR8103V and IRLR8503 can and are being used in a variety of applications, they were designed and optimized for low voltage DC-DC conversion in a synchronous buck converter topology, specifically, microprocessor power applications. The IRLR8503 (Figure 1) was optimized for the control FET socket, while the IRLR8103V was optimized for the synchronous FET function. IRLR8503 (Cont FET) Table 2 – New Charge Parameters New Charge Parameter Description QGS1 Pre-Threshold Gate Charge Waveform QGS2 Post-Threshold Gate Charge Q GCONT Control FET Total QG Figure 3 QSWITCH Charge during control FET switching Combines QGS2 and QGD Q OSS Output charge Charge supplied to COSS during the QGD period of control FET switching Figure 5 Figure 6 QGSYNC Synchronous FET Total QG (VDS ≤ 0) Figure 4 Drain Voltage CGD Drain Voltage CGS IRLR8103V (Sync FET) QSwitch QGD Figure 2 – Inter-electrode Capacitance Because of the inter-electrode capacitance (Figure 2) of the Power MOSFET, specifying the RDSON of the device is not enough to ensure good performance. An optimization between RDSON and charge must be performed to insure the best performing MOSFET for a given application. Both die size and device architecture must be varied to achieve the minimum possible in-circuit losses. This is independently true for both control FET and synchronous FET. Unfortunately, the capacitances of a FET are non-linear and voltage dependent. Therefore, it is inconvenient to specify and use them effectively in switching power supply power loss estimations. This was well understood years ago and resulted in changing the emphasis from capacitance to gate charge on Power MOSFET data sheets. Table 1 – Traditional Charge Parameters Device Capacitance Corresponding Charge Parameter C GS QGS CGS + CGD QG CGD QGD International Rectifier has recently taken the industry a step further by specifying new charge parameters that are even more specific to DC-DC converter design (Table 2). In order to understand these parameters, it is best to start with the in-circuit waveforms in Figure 3 & Figure 4. 0V Gate Voltage QGS1 QGS2 VGTH Figure 1 – Application Topology www.irf.com QG (Control FET) CDS Dead Time Gate Voltage VGTH QG (Sync FET) 0A Drain Current Figure 3 – Control FET Waveform Body Diode Current Drain Current Figure 4 – Sync FET Waveform The waveforms are broken into segments corresponding to charge parameters. These, in turn, correspond to discrete time segments of the switching waveform. VIN g1 N1 Cont FET Coss1 2n SN g2 N2 Sync FET Coss2 2n Figure 5 – QOSS Equivalent Circuit Switch node voltage (VSN) N1 Gate Voltage N1 Current N1 Coss Discharge + N2 Coss Charge Figure 6 – QOSS Waveforms Losses may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss. The following simplified power loss equation is true for both MOSFETs in a synchronous buck converter: PLOSS = PCONDUCTION + PGATE DRIVE + PSWITCH + POUTPUT For the synchronous FET, the PSWITCH term becomes virtually zero and is ignored. 3 IRLR8503 Table 3 and Table 4 describes the event during the various charge segments and shows an approximation of losses during that period. Table 3 – Control FET Losses Description Segment Losses 2 Conduction Losses associated with MOSFET on time. IRMS is a function of load P COND = I RMS × R DS (on ) current and duty cycle. Loss Gate Drive Losses associated with charging and discharging the gate of the PIN = VG × QG × ƒ MOSFET every cycle. Use the control FET QG. Loss Switching Losses during the drain voltage and drain current transitions for every full cycle. Q GS 2 ׃ Losses occur during the QGS2 and QGD time period and can be simplified by using PQGS 2 ≈ VIN × IL × Loss IG Qswitch. Q PQGD ≈ VIN × IL × GD × ƒ IG PSWITCH ≈ VIN × IL Output Loss Q SW ׃ IG Losses associated with the QOSS of the device every cycle when the control Q FET turns on. Losses are caused by both FETs, but are dissipated by the control POUTPUT = OSS × VIN × F 2 FET. Table 4 – Synchronous FET Losses Conduction Loss Gate Drive Loss Switching Loss Output Loss Description Losses associated with MOSFET on time. IRMS is a function of load current and duty cycle. Losses associated with charging and discharging the gate of the MOSFET every cycle. Use the Sync FET QG. Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. Segment Losses 2 PCOND = IRMS × RDSon PIN = VG × QG × ƒ PSWITCH ≈ 0 Losses associated with the QOSS of the device every cycle when the control FET Q turns on. They are caused by the synchronous FET, but are dissipated in the control POUTPUT = OSS × VIN × ƒ 2 FET. Typical PC Application The IRLR8103V and the IRLR8503 are suitable for Synchronous Buck DC-DC Converters, and are optimized for use in next generation CPU applications. The IRLR8103V is primarily optimized for use as the low side synchronous FET (Q2) with low RDS(on) and high CdV/dt immunity.The IRLR8503 is primarily optimized for use as the high side control FET (Q2) with low cobmined Qsw and RDS(on) , but can also be used as a synchronous FET. The IRLR8503 is also tested for Cdv/dt immunity, critical for the low side socket. The typical configuration in which these devices may be used in shown in Figure 7. IRLR8503 Control FET (Q1) 1 x IRLR8103Vor or 2 x IRLR8503 Synchronous FET (Q2) Figure 7. 2 & 3-FET solution for Synchronous Buck Topology. 4 www.irf.com IRLR8503 Typical Characteristics IRLR8503 6.0 ID = 15A ID = 15A VGS, Gate-to-Source Voltage (V) VGS = 4.5V 2.0 (Normalized) RDS(on) , Drain-to-Source On Resistance 2.5 1.5 1.0 VDS = 20V 4.0 2.0 0.0 0.5 -60 -40 -20 0 20 40 60 0 80 100 120 140 160 4 12 16 Figure 9. Gate-to-Source Voltage vs. Typical Gate Charge Figure 8. Normalized On-Resistance vs. Temperature 0.015 2500 0.014 VGS Ciss Crss Coss 2000 C, Capacitance (pF) RDS(on) , Drain-to -Source On Resistance (Ω) 8 QG, Total Gate Charge (nC) T J , Junction Temperature ( °C ) 0.013 0.012 ID = 15A = = = = 0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd Ciss 1500 1000 0.011 Coss 500 0.010 0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 Crss 1 VGS, Gate -to -Source Voltage (V) 100 Figure 11. Typical Capacitance vs. Drain-to-Source Voltage Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage 1000.0 ID, Drain-to-Source Current (Α) 100 10 V DS , Drain-to-Source Voltage (V) 100.0 T J = 150°C 10.0 T J = 25°C VDS = 15V 20µs PULSE WIDTH 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VGS, Gate-to-Source Voltage (V) Figure 12. Typical Transfer Characteristics www.irf.com 5 IRLR8503 Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 0.02 0.01 0.01 0.00001 t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x ZthJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Inductive Load Circuit Figure 15. Switching waveform Figure 14. Clamped Inductive Load test diagram 6 www.irf.com IRLR8503 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 10.42 (.410) 9.40 (.370) 3 LEAD ASSIGNMENTS 1 - GATE 0.51 (.020) MIN. -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2 - DRAIN 3 - SOURCE 4 - DRAIN 0.58 (.023) 0.46 (.018) M A M B NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2.28 (.090) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4.57 (.180) 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" N ote: "P" in as sembly line pos ition indicates "Lead-Free" OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRFR120 12 AS S EMBLY LOT CODE INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A PART NUMBER IRFR120 12 www.irf.com 916A 34 P916A 34 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE 7 IRLR8503 Tape & Reel Information TO-252AA TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the commercial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 5/05 8 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/