PTMA180402ELV1XWSA1

PTMA180402EL PTMA180402FL Wideband RF LDMOS Integrated Power Amplifier 40 W, 1800 – 2000 MHz Description PTMA180402EL Package H-33265-8 pr od uc t PTMA180402FL Package H-34265-8 s The PTMA180402EL and PTMA180402FL are matched, wideband 40-watt, 2-stage, LDMOS integrated amplifiers intended for use in all typical modulation formats from 1800 to 2000 MHz. These devices are offered in thermally-enhanced ceramic packages for cool and reliable operation. Features • Designed for wide RF and modulation bandwidths and low memory effects Broadband Performance VDD = 28 V, IDQ1 = 110 mA, IDQ1 = 330 mA 35 0 25 -10 tin 20 Return Loss 15 10 1800 1900 2000 2100 -15 -20 Return Loss (dB) ue -5 sc on Gain (dB) d Gain 30 5 1700 • On-chip matching, integrated input DC block, 50‑ohm input and > 5-ohm output -25 -30 2200 Frequency (MHz) • Typical single-carrier CDMA performance at 1960 MHz, 28 V - Average output power = 4 W - Linear gain = 30 dB - Efficiency = 14% - Adjacent channel power = –53 dBc • Typical 2-tone performance, 1960 MHz, 28 V - Output power (PEP) = 50 W at IM3 = –30 dBc - Efficiency = 33% • Capable of handling 10:1 VSWR @ 28 V, 40 W (CW) output power • Integrated ESD protection. Meets HBM Class 1B (minimum), per JESD22-A114F di • High-performance, thermally-enhanced packages, Pb-free and RoHS compliant, with solder-friendly plating All published data at TCASE = 25°C unless otherwise indicated *See Infineon distributor for future availability. ESD: Electrostatic discharge sensitive device—observe handling precautions! Data Sheet 1 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL RF Characteristics CDMA Measurements (tested in Infineon test fixture) VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 335 mA, POUT = 4 W average, ƒ = 1960 MHz Symbol Min Typ Max Unit Gain Gps 28.5 30 — dB Drain Efficiency η D 13 14 — % Adjacent Channel Power Ratio ACPR — –53 –50 dBc Symbol Min Typ Max Unit Stage 1 Characteristics Conditions Drain Leakage Current VDS = 28 V, VGS = 0 V VDS = 63 V, VGS = 0 V Gate Leakage Current VGS = 10 V, VDS = 0 V On-state Resistance VGS = 10 V, VDS = 0.1 V Operating Gate Voltage VDS = 28 V, IDQ = 160 mA Stage 2 Characteristics Conditions Drain-source Breakdown Voltage Drain Leakage Current Gate Leakage Current On-state Resistance — — 1.0 µA IDSS — — 10.0 µA IGSS — — 1.0 µA RDS(on) — 1.6 — Ω VGS 2.0 2.5 3.0 V Symbol Min Typ Max Unit VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V VDS = 28 V, VGS = 0 V IDSS — — 1.0 µA VDS = 63 V, VGS = 0 V IDSS — — 10.0 µA VGS = 10 V, VDS = 0 V IGSS — — 1.0 µA RDS(on) — 0.21 — Ω VGS 2.0 2.5 3.0 V tin ue d IDSS sc on pr od DC Characteristics VGS = 10 V, VDS = 0.1 V VDS = 28 V, IDQ = 330 mA di Operating Gate Voltage uc t Characteristic s   Data Sheet 2 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL Maximum Ratings Symbol Value Unit Drain-Source Voltage VDSS 65 V Gate-Source Voltage VGS –0.5 to +12 V Operating Voltage VDD 24 to 28 V TJ 200 °C Storage Temperature Range TSTG –40 to +150 °C Overall Thermal Resistance (TCASE = 70°C) 1st Stage RθJC 5.0 °C/W 2nd Stage RθJC 1.1 °C/W pr od POUT = 40 W, IDQ1 = 160 mA, IDQ2 = 330 mA uc t Junction Temperature s Parameter Ordering Information Package Type Package Description Shipping PTMA180402EL V1 H-33265-8 Themally-enhanced, slotted flange Tray PTMA180402EL V1 R50 H-33265-8 Themally-enhanced, slotted flange Tape PTMA180402FL V1 H-34265-8 Themally-enhanced, earless flange PTMA180402FL V1 R50 H-34265-8 d Type and Version ue Tray Themally-enhanced, earless flange Tape sc on tin Typical Performance (data taken in a production test fixture) Two-tone at Selected Frequencies CW Performance Efficiency 40 Gain 30 30 29 20 ƒ = 1930 MHz ƒ = 1960 MHz ƒ = 1990 MHz 28 27 30 35 40 45 10 50 PAE (%) Gain (dB) 31 50 Power Added Efficiency (%) di 32 -20 35 -25 30 -30 25 -35 Efficiency 20 -40 IMD3 15 10 0 0 -45 -50 ƒ = 1930 MHz ƒ = 1960 MHz ƒ = 1990 MHz 5 Output Power (dBm) Data Sheet 40 30 35 40 IMD3 (dBc) VDD = 28 V, IDQ1 = 130 mA, IDQ2 = 330 mA VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 330 mA -55 45 -60 Output Power, avg. (dBm) 3 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL Typical Performance (cont.) IS-95 at Selected Temperatures IS-95 at Selected Frequencies -45 15 -50 10 -55 ACPR -60 -65 0 2 4 6 8 5 10 0 25 15 -45 -50 PAE -55 ACPR 5 -5 Output Power (W) +25ºC –25ºC +90ºC -40 0 2 4 6 8 -60 10 Adj. Ch. Power Ratio (dBc) 20 Gain uc t Efficiency 35 pr od ACPR (dBc) -40 Gain (dB), Power Added Efficiency (%) 25 ƒ = 1930 MHz ƒ = 1960 MHz ƒ = 1990 MHz Power Added Efficiency (%) -35 s VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA, ƒ = 1960 MHz VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA -65 tin ue d Output Power, avg. (W) WCDMA Performance Gate – Source Voltage vs. Temperature VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA, Test Mode 1 w/64 DPCH, PAR = 7.5 dB 1.05 1.00 Slope = –1.3 mV/°C 0.95 Data Sheet 20 Efficiency -40 15 10 -45 5 -50 0.90 0.85 ƒ = 1930 MHz ƒ = 1960 MHz ƒ = 1990 MHz -35 ACPR (dBc) 1.10 25 -30 di Normalized Gate – Source Voltage (threshold), V 1.15 ACPR -30 -10 10 30 50 70 -55 90 Temperature (°C) 1 3 5 7 9 11 0 Power Added Efficiency (%) sc on VDD = 28 V, IDQ1 = 110 mA, IDQ2 = 335 mA Output Power (W) 4 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL  Typical Performance (cont.) EDGE EVM Performance EDGE Modulation Spectrum Performance VDD = 28 V, IDQ1 = 160 mA, IDQ2 = 330 mA, ƒ = 1960 MHz VDD = 28 V, IDQ! = 160 mA, IDQ2 = 330 mA, ƒ = 1960 MHz 15 EVM 10 1 5 0 30 32 34 36 38 40 42 44 s 2 -55 -65 -85 Output Power (dBm) 24 400 kHz -75 0 32 Efficiency uc t 20 -45 pr od Efficiency ACPR (dB) . Drain Efficiency (%) 25 40 -35 30 32 34 16 8 600 kHz 36 38 40 42 Efficiency (%) 3 EVM RMS (average %) . 30 44 0 tin ue d Output Power (dBm) Six-carrier TD-SCDMA Drive-up sc on VDD = 28 V, IDQ1 = 230 mA, IDQ2 = 335 mA, ƒ = 2017.5 MHz -30 25 Adj Lower Adj Upper 20 Alt Upper -40 15 Effciency di ACPR (dBc) Alt Lower -45 10 5 -50 -55 Efficiency (%) -35 31 32 33 34 35 36 37 38 39 0 Output Power (dBm) Data Sheet 5 of 12 Rev. 10, 2015-01-14 di d ue tin sc on s uc t pr od PTMA180402EL PTMA180402EL PTMA180402FL PTMA180402FL Confidential, Limited Internal Distribution Reference Circuit Circuit Reference VD1 VD2 C1 100µF 50V C2 10µF C3 1µF C4 0.1µF C19 12pF C5 12pF C22 10µF C21 1µF C20 0.1µF 8 C23 100µF 50V DUT 1 2 3 s PTMA18040 4 1 8 2 3 5 6 7 C6 10µF C7 1µF C8 0.1µF C9 12pF C14 12pF C15 0.1µF C12 0.1µF C13 12pF C17 10µF C18 100µF 50V d C11 1µF 6 7 C27 10µF C28 100µF 50V J2 C24 12pF C25 0.1µF C26 1µF ue C10 10µF 5 C30 2.7pF 9 C16 1µF VG2 4 pr od VG1 C29 2.2pF uc t J1 C31 12pF tin Reference circuit schematic for ƒ = 1930 – 1990 MHz Reference circuit schematic for ƒ = 1930 – 1990 MHz sc on Circuit Assembly Assembly Specifications Specifications Circuit DUT PTMA180402EL or PTMA180402FL LDMOS Integrated Power Amplifier DUT PTMA180402EL or PTMA180402FL LDMOS Integrated Power Amplifier Test Fixture Part No. LTN/PTMA180402EFL Test Fixture Part No. LTN/PTMA180402EFL PCB Rogers 4350, 0.76 mm [.030"] thick, 1 oz. copper, ε = 3.48 PCB Rogers 4350, 0.76 mm [.030"] thick, 1 oz. copper, εrr = 3.48 Find Gerber files for this test fixture on the Infineon Web site at http://www.infineon.com/rfpower Find Gerber files for this test fixture on the Infineon Web site at http://www.infineon.com/rfpower 11 22 33 44 55 66 77 8,8, 99 Data Sheet Data Sheet Electrical Characteristics Characteristics at at 1960 1960 MHz MHz Electrical di Microstrip Microstrip 0.224 λ, 49.8 Ω 0.224 λ, 49.8 Ω 0.022 λ, 10.4 Ω 0.022 λ, 10.4 Ω 0.027 λ, 10.4 Ω 0.027 λ, 10.4 Ω 0.035 λ, 34.1 Ω 0.035 λ, 34.1 Ω 0.048 λ, 34.1 Ω 0.048 λ, 34.1 Ω 0.153 λ, 44.5 Ω 0.153 λ, 44.5 Ω 0.046 λ, 49.8 Ω 0.046 λ, 49.8 Ω 0.136 λ, 61.1 Ω 0.136 λ, 61.1 Ω Dimensions: LL xx W W (mm) (mm) Dimensions: Dimensions: LL xx W W (in.) (in.) Dimensions: 7 of 12 7 of 12 20.75 x 1.70 20.75 x 1.70 1.85 x 13.00 1.85 x 13.00 2.26 x` 13.00 2.26 x` 13.00 3.18 x 3.00 3.18 x 3.00 4.29 x 3.00 4.29 x 3.00 14.07 x 2.03 14.07 x 2.03 4.27 x 1.70 4.27 x 1.70 12.83 x 1.19 12.83 x 1.19 0.817 x 0.067 0.817 x 0.067 0.073 x 0.512 0.073 x 0.512 0.089 x 0.512 0.089 x 0.512 0.125 x 0.118 0.125 x 0.118 0.169 x 0.118 0.169 x 0.118 0.554 x 0.080 0.554 x 0.080 0.168 x 0.067 0.168 x 0.067 0.505 x 0.047 0.505 x 0.047 Rev. 10, 2015-01-14 Rev. 09, 2011-12-13 di d ue tin sc on s uc t pr od PTMA180402EL PTMA180402FL Package Specifications Package H-33265-8 Outline 15.24 [.600] 7.11 [.280] (45° X 2.03 [.08]) 4X R 0.13 [.05] MAX C L 2.54±0.51 [.100±.020] 10.16 [.400] uc t s 8 (2.73 [.107]) 1 2 3 4 6X 0.406 [.016] 0.76 [.030] 9.55 [.376] REF sc on tin SPH 1.57 [.062] C L 4X R1.52 [R.060] 10.16 [.400] 1.02 [.040] S H-33265-8_po_02_08-02-2013 20.32 [.800] 6. di 3.68±.38 [.145±.015] 2X R1.59 [R.063] d 2X 3.48 [.137] ue 2X 2.21 [.087] 15.24±0.51 [.600±.020] 5 6 7 4X R 0.63 [.025] MAX 2X 4.57 [.180] 9.78 [.385] pr od C L CL CL Data Sheet Diagram Notes—unless otherwise specified: 1. Interpret dimensions and tolerances per ASME Y14.5M-1994. 2. Primary dimensions are mm. Alternate dimensions are inches. 3. All tolerances ± 0.127 [.005] unless specified otherwise. 4. Pins: S – source; see Pinout Diagram for complete list. 5. Lead thickness: 0.127±0.025 [.005±0.001] 6. Exposed metal plane on bottom of ceramic insulator. 7. Gold plating thickness: 0.25 micron [10 microinch] max. 9 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL Package Specifications (cont.) Package H-34265-8 Outline (45° X 2.03 [.08]) 7.11 [.280] C L 2.54±0.51 4X R 0.13 [.05] MAX 8 10.16 [.400] 0.76 [.030] 2X 3.48 [.137] 9.55 [.376] REF sc on tin SPH 1.57 [.062] 3.68±.38 [.145±.015] 6X 0.406 [.016] d 2X 2.21 [.087] ue 2X 4.57 [.180] 10.16 [.400] 1.02 [.040] H-34265-8_po_03_08-02-2013 C L 10.16 [.400] S Diagram Notes—unless otherwise specified: 1. Interpret dimensions and tolerances per ASME Y14.5M-1994. 2. Primary dimensions are mm. Alternate dimensions are inches. 3. All tolerances ± 0.127 [.005] unless specified otherwise. 4. Pins: S – source; see Pinout Diagram for complete list. 5. Lead thickness: 0.127±0.025 [.005±0.001] 6. Gold plating thickness: 0.25 micron [10 microinch] max. di 5 6 7 pr od 4 4X R 0.63 [.025] MAX 15.24±0.51 [.600±.020] C L 1 2 3 uc t s [.100±.020] Data Sheet 10 of 12 Rev. 10, 2015-01-14 PTMA180402EL PTMA180402FL Pinout Diagram Pin Diagram for PTMA180402EL and PTMA180402FL Packages H-33265-8 and H-34265-8 Thermal FET 1 Pin # 3 S (flange, see Package Outlines) Source 1 Drain 1 3 4 5 5 6 6 7 NC 1st uc t 2 8 2nd 7 8 Function FET_D pr od 4 s 2 FET_G RF In Gate 1 Gate 2 NC RF Out/D2 ue d a180402ef l PD pi nout 2007 12 12 di sc on tin Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/rfpower Data Sheet 11 of 12 Rev. 10, 2015-01-14 PTMA180402EFL V1 2015-01-14 2013-07-30, Data Sheet Data Sheet Page All Subjects (major changes since last revision) Products Discontinued. Please see PD Notes : PD_215-14 We Listen to Your Comments uc t Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: s Revision History: Previous Version: highpowerRF@infineon.com sc on Edition 2015-01-14 Published by Infineon Technologies AG 81726 Munich, Germany tin ue d pr od To request other information, contact us at: +1 877 465 3667 (1-877-GO-LDMOS) USA or +1 408 776 0600 International © 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer di The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com/rfpower). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet 12 of 12 Rev. 10, 2015-01-14