SPD50P03LGBTMA1

SPD50P03L G OptiMOS -P Power-Transistor ® Product Summary Features V DS • P-Channel -30 R DS(on),max • Enhancement mode V 7 ID mΩ -50 A • Logic level • 175°C operating temperature • Avalanche rated PG-TO252-5 • dv /dt rated • High current rating • Pb-free lead-plating, RoHS compliant Type Package Marking Tape and reel information Lead Free SPD50P03L G PG-TO252-5 50P03L 1000 pcs / reel Yes Packing Non dry Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID T C=25 °C1) -50 T C=100 °C1) -50 Pulsed drain current I D,pulse T C=25 °C -200 Avalanche energy, single pulse E AS I D=-50 A, R GS=25 Ω 256 Reverse diode dv /dt dv /dt I D=-50 A, V DS=24 V, di /dt =-200 A/µs, T j,max=175 °C -6 Gate source voltage V GS Power dissipation P tot Operating and storage temperature T j, T stg T C=25 °C Unit A mJ kV/µs ±20 V 150 W -55…+175 °C ESD class HBM 1C Soldering temperature 260 55/175/56 IEC climatic category; DIN IEC 68-1 Rev. 1.9 Value page 1 2012-09-13 SPD50P03L G Parameter Values Symbol Conditions Unit min. typ. max. - - 1 minimal footprint - - 75 6 cm2 cooling area2) - - 50 Thermal characteristics Thermal resistance, junction - case R thJC Thermal resistance, junction - ambient R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=-250 µA -30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=-250 µA -1 -1.5 -2 Zero gate voltage drain current I DSS V DS=-30 V, V GS=0 V, T j=25 °C - -0.1 -1 V DS=-30 V, V GS=0 V, T j=175 °C - -10 -100 V µA Gate-source leakage current I GSS V GS=-20 V, V DS=0 V - -10 -100 nA Drain-source on-state resistance R DS(on) V GS=-4.5 V, I D=-30 A - 8.5 12.5 mΩ Drain-source on-state resistance R DS(on) V GS=-10 V, I D=-50 A - 5.7 7.0 Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=-50 A 47 94 - 1) S Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 123 A. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.9 page 2 2012-09-13 SPD50P03L G Parameter Values Symbol Conditions Unit min. typ. max. - 4590 6880 - 1220 1830 Dynamic characteristics Input capacitance C iss V GS=0 V, V DS=-25 V, f =1 MHz Output capacitance C oss Reverse transfer capacitance C rss - 1000 1500 Turn-on delay time t d(on) - 14.8 22 Rise time tr - 21.7 32 Turn-off delay time t d(off) - 139 208 Fall time tf - 104 156 - -14 -19 - -35 -53 V DD=-15 V, V GS=-10 V, I D=-1 A, R G=6 Ω pF ns Gate Charge Characteristics 3) Gate to source charge Q gs Gate to drain charge Q gd Gate charge total Qg VDD=-24 V, ID=-50 A, VGS=0 to -10 V - -95 -126 Gate plateau voltage V plateau VDD=-24 V, ID=-50 A - -3.0 - V - - -50 A - - -200 V DD=-24 V, I D=-50 A nC Reverse Diode Diode continous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=50 A, T j=25 °C - -1 -1.65 V Reverse recovery time t rr V R=-15 V, I F=|I S|, di F/dt =100 A/µs - 38 47 ns Reverse recovery charge Q rr - 46 57 nC 3) Rev. 1.9 T C=25 °C See figure 16 for gate charge parameter definition page 3 2012-09-13 SPD50P03L G 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); |V GS|≥10 V 160 55 50 140 45 120 40 35 -I D [A] P tot [W] 100 80 60 30 25 20 15 40 10 20 5 0 0 0 40 80 120 160 200 0 40 T C [°C] 80 120 160 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 103 101 limited by on-state resistance 1 µs 10 µs 100 100 µs Z thJC [K/W] 10 ms -I D [A] 10 2 DC 1 ms 0.5 101 10-1 0.2 0.1 0.05 0.02 0.01 single pulse 100 10 10-2 -1 10 0 10 1 10 2 -V DS [V] Rev. 1.9 10-5 10-4 10-3 10-2 10-1 t p [s] page 4 2012-09-13 SPD50P03L G 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 15 200 -10 V -5 V 180 -4.5 V 160 -4 V 140 10 R DS(on) [mΩ] -I D [A] 120 100 -4.5 V -3.5 V 80 -5.5 V 5 60 V 6- -3 V -6.5 V -7 V -10 V 40 -2.5 V 20 0 0 0 2 4 6 8 0 10 40 80 -V DS [V] 120 160 200 -I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 80 100 C °25 70 60 80 C °175 g fs [S] -I D [A] 50 40 30 60 40 20 20 10 0 0 0 1 2 3 4 Rev. 1.9 0 20 40 60 -I D [A] -V GS [V] page 5 2012-09-13 SPD50P03L G 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=-50 A; V GS=-10 V V GS(th)=f(T j); V GS=V DS; I D=-250 µA 2.5 11 2 98%. 9 -V GS(th) [V] R DS(on) [mΩ] 98 % 7 typ. 1.5 typ. 1 2% 5 0.5 0 3 -60 -20 20 60 100 140 -60 180 -20 20 60 T j [°C] 100 140 180 T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 104 1000 10000 Ciss 100 103 I F [A] C [pF] Coss Crss 1000 10 25 °C, typ 175 °C, typ 25 °C, 98% 175 °C, 98% 102 1 100 0 5 10 15 20 25 Rev. 1.9 0 0.5 1 1.5 2 2.5 -V SD [V] -V DS [V] page 6 2012-09-13 SPD50P03L G 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=-50 A pulsed parameter: T j(start) parameter: V DD 100 12 V 6- C °25 V 15- V 24- 10 C °100 8 -V GS [V] -I AV [A] C °150 10 6 4 2 1 0 1 10 100 1000 0 20 40 60 80 100 120 -Q gate [nC] t AV [µs] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=-250 µA 36 V GS 35 Qg 34 -V BR(DSS) [V] 33 32 31 V g s(th) 30 29 Q g(th) 28 Q sw Q gs 27 -60 -20 20 60 100 140 Q g ate Q gd 180 T j [°C] Rev. 1.9 page 7 2012-09-13 SPD50P03L G Package Outline PG-TO252-5: Outline Footprint Packaging Tape Dimensions in mm Rev. 1.9 page 8 2012-09-13 SPD50P03L SPD50P03LG Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.9 page 9 2012-09-13