TLD55012QVXUMA1

TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Infineon LITIX™ Power Flex 1 Package PG-VQFN-48 Marking TLD55012QV Sales Name TLD5501-2QV Overview Features • Dual-Channel synchronous DC/DC Controller for HIGH POWER LED drivers • Wide LED forward voltage Range (2 V up to 50 V) • Wide VIN Range (IC 4.5 V to 40 V, Power 4.5 V to 55 V) • Switching Frequency Range from 200 kHz to 700 kHz • SPI for diagnostics and control • Maximum Efficiency in every condition (up to 96%) • Constant Current (LED) and Constant Voltage Regulation • Limp Home Function (Fail Safe Mode) • EMC optimized device: Features an auto Spread Spectrum • LED current sense with dedicated monitor Output • Advanced protection features for device and load • Enhanced Dimming features: Analog and PWM dimming • LED current accuracy +/- 3% • Available in a small thermally enhanced PG-VQFN-48 package • Automotive AEC Q100 Grade 1 (-40°C to 125°C) qualified CIVCC CIN1 COMP1 SET1 Analog Dimming CH1 SPI RFREQ L1 Channel LSGD1 1 SWCS1 SGND1 EN LHI VDD CSN SI SO SCLK SYNC VFB1 FBH1 FBL1 PGND1 FREQ BST2 M2 R SWCS1 IVCC_ext C OUT11 COUT12 RFB1 C OUT13 RVFBH1 SWN1 IOUTMON1 µC SYNC signal M1 HSGD1 SOFT_START1 Output Current Monitoring CH1 Device Enable Fail Safe Activation Digital Supply (+5V) CIN2 CBST1 C Soft_Start1 C COMP1 VPOW BST1 PWM I1 Digital dimminig CH1 RCOMP1 D1 RVFBL1 VIN IVCC_ext IVCC Vbat VPOW CIN3 D2 C BST2 Channel LSGD2 SWCS2 2 C Soft_Start2 SGND2 CCOMP2 IOUTMON2 VSS Figure 1 Datasheet M4 RSWCS2 COUT21 C OUT22 RFB2 C OUT23 VFB2 FBH2 FBL2 PGND2 SET2 Analog Dimming CH2 Output Current Monitoring CH2 L2 SWN2 RVFBH2 RCOMP2 SOFT_START2 M3 HSGD2 COMP2 RVFBL2 PWM I2 Digital dimminig CH2 AGND Application Drawing - TLD5501-2QV as current regulator www.infineon.com 1 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Overview Description The TLD5501-2QV is a synchronous DUAL Channel DC/DC buck controller with built in protection features and SPI interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and minimum number of external components. The TLD5501-2QV offers both analog and digital (PWM) dimming. The switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external clock source. A built in programmable Spread Spectrum switching frequency modulation and the forced continuous current regulation mode improve the overall EMC behavior. Furthermore the current mode regulation scheme provides a stable regulation loop maintained by small external compensation components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up. The TLD5501-2QV is suitable for use in the harsh automotive environment. Table 1 Product Summary Power Stage input voltage range VPOW 4.5 V … 55 V Device Input supply voltage range VVIN 4.5 V … 40 V Maximum output voltage (depending by the application conditions) VOUT(max) 50 V Switching Frequency range fSW 200 kHz ... 700 kHz Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Up) RDS(ON_PU) 2.3 Ω Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Down) RDS(ON_PD) 1.2 Ω SPI clock frequency fSCLK(MAX) 5 MHz Protective Functions • Over load protection of external MOSFETs • Shorted load, output overvoltage and overcurrent protection • Input undervoltage protection • Thermal shutdown of device with autorestart behavior • Electrostatic discharge protection (ESD) Diagnostic Functions • Latched diagnostic information via SPI • Open load detection in ON-state • Device Overtemperature shutdown and Temperature Prewarning • Smart monitoring and advanced functions provide ILED information Limp Home Function • Limp Home activation via LHI pin Applications • Especially designed for driving high power LEDs in automotive applications • Automotive Exterior Lighting: full LED headlamp assemblies (Low Beam, High Beam, Matrix Beam, Pixel Light) • General purpose current/voltage controlled DC/DC buck LED driver Datasheet 2 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Block Diagram 2 Block Diagram IVCC VIN LDO Power On Reset IVCC_EXT Internal Supply EN/INUVLO GATE DRIVER SYNC BST1 Oscillator FREQ HSGD1 Auto-Spread Spectrum Generator SWN1 LOGIC Channel 1 Slope Comp. IVCC_EXT Thermal Protection + Prewarning LSGD1 PWM Generator Diagnosis Open Load + Short to GND for CH1+CH2 SOFT_START1 PGND1 IVCC_EXT Soft Start for CH1 +CH2 LSGD2 SOFT_START2 PWMI1 PGND2 Limp Home Mode LHI LOGIC Channel 2 BST2 Digital Dimming CH1+CH2 HSGD2 PWMI2 SET1 SET2 Analog Dimming Pin CH1+CH2 SWN2 SWCS1 Output current accuracy calibration Switch Current Error Amplifier SGND2 VDD Voltage Loop Feedback 88Bit BitDAC DAC Analog Analog Dimming Dimming SPI CSN Figure 2 Datasheet FBH2 FBL2 COMP2 AGND VFB2 FBL1 COMP1 VSS Feedback Error Amplifier IOUTMON2 SO LED LED Current Current Monitor Monitor IOUTMON1 Input/diagnosis register VFB1 FBH1 SCLK SI SWCS2 SGND1 Block Diagram - TLD5501-2QV 3 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Pin Configuration Pin Configuration 3.1 Pin Assignment 36 EN/INUVLO 35 n.c. 34 n.c. 33 PWMI2 32 PWMI1 31 VDD 30 SI 29 SCLK 28 CSN 27 SO 26 VSS 25 FREQ 3 VIN LHI IVCC SOFT_START1 SET1 VFB1 COMP1 IOUTMON1 IVCC_EXT SWCS1 SGND1 FBL1 37 38 39 40 41 42 43 44 45 46 47 48 EP 24 SYNC 23 TEST2 22 AGND 21 SOFT_START2 20 SET2 19 VFB2 18 COMP2 17 IOUTMON2 16 n.c 15 SWCS2 14 SGND2 13 FBL2 12 11 10 9 8 7 6 5 4 3 2 1 FBH2 HSGD2 BST2 SWN2 PGND2 LSGD2 LSGD1 PGND1 SWN1 BST1 HSGD1 FBH1 Figure 3 Datasheet Pin Configuration - TLD5501-2QV 4 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Pin Configuration 3.2 Pin Definitions and Functions Table 2 Pin Definitions and Functions Pin Symbol I/O 1) Function Power Supply 16,34, 35 n.c. - Not connected tie to AGND on the layout 37 VIN - Power Supply Voltage Supply for internal biasing 31 VDD - Digital GPIO Supply Voltage Connect to reverse voltage protected 5 V or 3.3 V supply 45 IVCC_EXT I PD External LDO input Input to alternatively supply internal Gate Drivers via an external LDO. Connect to IVCC pin to use internal LDO to supply gate drivers. Must not be left open 5, 8 PGND1, 2 - Power Ground Ground for power potential. Connect externally close to the chip 26 VSS - Digital GPIO Ground Ground for GPIO pins 22 AGND - Analog Ground Ground Reference - EP - Exposed Pad Connect to external heatspreading Cu area (e.g. inner GND layer of multilayer PCB with thermal vias) Gate Driver Stages 2 HSGD1 O Highside Gate Driver Output 1 Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN1. Connect to gate of external switching MOSFET 11 HSGD2 O Highside Gate Driver Output 2 Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN2. Connect to gate of external switching MOSFET 6 LSGD1 O Lowside Gate Driver Output 1 Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET 7 LSGD2 O Lowside Gate Driver Output 2 Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET 4 SWN1 IO Switch Node 1 9 SWN2 IO Switch Node 2 39 IVCC O Internal LDO output Used for internal biasing and gate driver supply. Bypass with external capacitor close to the pin. Pin must not be left open Datasheet 5 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Pin Configuration Table 2 Pin Pin Definitions and Functions Symbol I/O 1) PD Limp Home Input Pin Used to enter in Limp Home state during Fail Safe condition. Function Inputs and Outputs 38 LHI I 23 TEST2 - 36 EN/INUVLO I 25 FREQ I 24 SYNC I PD Synchronization Input Apply external clock signal for synchronization 32 PWMI1 I PD Control Input CH1 Digital input 5 V or 3.3 V 33 PWMI2 I PD Control Input CH2 Digital input 5 V or 3.3 V 1 FBH1 I Output current Feedback Positive for CH1 Non inverting Input (+) CH1 12 FBH2 I Output current Feedback Positive for CH2 Non inverting Input (+) CH2 48 FBL1 I Output current Feedback Negative for CH1 Inverting Input (-) CH1 13 FBL2 I Output current Feedback Negative for CH2 Inverting Input (-) CH2 3 BST1 IO Bootstrap capacitor Used for internal biasing and to drive the Highside Switch HSGD1. Bypass to SWN1 with external capacitor close to the pin. Pin must not be left open 10 BST2 IO Bootstrap capacitor Used for internal biasing and to drive the Highside Switch HSGD2. Bypass to SWN2 with external capacitor close to the pin. Pin must not be left open 46 SWCS1 I Current Sense Input for CH1 Inductor current sense CH1 - Non Inverting Input (+) 15 SWCS2 I Current Sense Input for CH2 Inductor current sense CH2 - Non Inverting Input (+) 47 SGND1 I Current Sense Ground for CH1 Inductor current sense CH1 - Inverting Input (-). Route as Differential net with SWCS1 on the Layout 14 SGND2 I Current Sense Ground for CH2 Inductor current sense CH2 - Inverting Input (-). Route as Differential net with SWCS2 on the Layout Datasheet Test Pin Used for Infineon end of line test, connect to GND in application PD Enable/Input Under Voltage Lock Out Used to put the device in a low current consumption mode, with additional capability to fix an undervoltage threshold via external components. Pin must not be left open Frequency Select Input Connect external resistor to GND to set frequency 6 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Pin Configuration Table 2 Pin Definitions and Functions 1) Pin Symbol I/O 43 COMP1 O Compensation Network Pin for CH1 Connect R and C network to pin for stability phase margin adjustment for CH1 18 COMP2 O Compensation Network Pin for CH2 Connect R and C network to pin for stability phase margin adjustment for CH2 40 SOFT_START1 O Softstart configuration Pin for CH1 Connect a capacitor CSOFT_START1 to GND to fix a soft start ramp default time 21 SOFT_START2 O Softstart configuration Pin for CH2 Connect a capacitor CSOFT_START2 to GND to fix a soft start ramp default time 42 VFB1 I Voltage Feedback Pin for CH1 VFB is intended to set output protection functions for CH1 19 VFB2 I Voltage Feedback Pin for CH2 VFB is intended to set output protection functions for CH2 41 SET1 I Analog current sense adjustment Pin for CH1 20 SET2 I Analog current sense adjustment Pin for CH2 44 IOUTMON1 O PD Output current monitor output 1 Monitor pin that produces a linear function of IOUT as a voltage. 17 IOUTMON2 O PD Output current monitor output 2 Monitor pin that produces a linear function of IOUT as a voltage. 30 SI I PD Serial data in; Digital input 5 V or 3.3 V 29 SCLK I PD Serial clock; Digital input 5 V or 3.3 V 28 CSN I PU SPI chip select; Digital input 5 V or 3.3 V. Active LOW 27 SO O Serial data out; Digital output, referenced to VDD Function SPI 1) O: Output, I: Input, PD: pull-down circuit integrated, PU: pull-up circuit integrated Datasheet 7 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 3 Absolute Maximum Ratings1) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply Voltages VIN Supply Input VVIN -0.3 – 60 V – P_4.1.1 VDD Digital supply voltage VVDD -0.3 – 6 V – P_4.1.2 IVCC Internal Linear Voltage Regulator Output voltage VIVCC -0.3 – 6 V – P_4.1.3 IVCC_EXT External Linear Voltage Regulator Input voltage VIVCC_EXT -0.3 – 6 V – P_4.1.4 VLSGD1,2- -0.3 – 5.5 V – P_4.1.54 HSGD1,2 - SWN1,2 Highside Gatedriver voltage VHSGD1,2-SWN1,2 -0.3 – 5.5 V Differential signal P_4.1.55 (not referred to GND) SWN1, SWN2 switching node voltage VSWN1, 2 -1 – 60 V – (BST1-SWN1), (BST2-SWN2) Boostrap voltage VBST1,2-SWN1,2 -0.3 – 6 V Differential signal P_4.1.7 (not referred to GND) BST1, BST2 Boostrap voltage related to GND VBST1, 2 -0.3 – 65 V – P_4.1.8 SWCS1,2 Switch Current Sense Input voltages VSWCS1,2 -0.3 – 0.3 V – P_4.1.42 SGND1,2 VSGND1,2 Switch Current Sense GND voltages -0.3 – 0.3 V – P_4.1.43 SWCS1,2-SGND1,2 Switch Current Sense differential voltages -0.5 – 0.5 V – P_4.1.44 -0.3 – 0.3 V – P_4.1.28 Gate Driver Stages LSGD1,2 - PGND1,2 Lowside Gatedriver voltage PGND1,2 Power GND voltage Datasheet PGND1,2 VSWCS1,2- P_4.1.6 SGND1,2 VPGND1,2 8 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface General Product Characteristics Table 3 Absolute Maximum Ratings1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number P_4.1.45 High voltage Pins FBH1,2; FBL1,2 Feedback Error Amplifier voltages VFBH1,2; FBL1,2 -0.3 – 60 V – FBH1,2-FBL1,2 Feedback Error Amplifier differential voltages VFBH1,2-FBL1,2 -0.5 – 0.5 V Differential signal P_4.1.47 (not referred to GND) EN/INUVLO Device enable/input undervoltage lockout VEN/INUVLO -0.3 – 60 V – P_4.1.16 PWMI1,2 Digital Input voltages VPWMI1,2 -0.3 – 5.5 V – P_4.1.49 CSN Voltage at Chip Select pin VCSN -0.3 – 5.5 V – P_4.1.18 SCLK Voltage at Serial Clock pin VSCLK -0.3 – 5.5 V – P_4.1.19 SI Voltage at Serial Input pin VSI -0.3 – 5.5 V – P_4.1.20 SO Voltage at Serial Output pin VSO -0.3 – 5.5 V – P_4.1.21 SYNC Synchronization Input voltage VSYNC -0.3 – 5.5 V – P_4.1.22 LHI Limp Home Input Voltage VLHI -0.3 – 5.5 V – P_4.1.58 LHI Limp Home Input Current ILHI -5 – – mA – P_4.1.60 VFB1,2 Loop Input voltages VVFB1,2 -0.3 – 5.5 V – P_4.1.50 SET1,2 Analog dimming Input voltage VSET1,2 -0.3 – 5.5 V – P_4.1.56 COMP1,2 Compensation Input voltages VCOMP1,2 -0.3 – 3.6 V – P_4.1.52 SOFT_START1,2 Softstart Voltages VSOFT_START1,2 -0.3 – 3.6 V – P_4.1.53 FREQ Voltage at frequency selection pin VFREQ -0.3 – 3.6 V – P_4.1.32 IOUTMON1,2 Voltages at output monitor pins VIOUTMON1,2 -0.3 – 5.5 V – P_4.1.59 Digital (I/O) Pins Analog Pins Datasheet 9 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface General Product Characteristics Table 3 Absolute Maximum Ratings1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.35 Storage Temperature Tstg -55 – 150 °C – P_4.1.36 ESD Resistivity of all Pins VESD,HBM -2 – 2 kV HBM2) P_4.1.37 ESD Resistivity to GND VESD,CDM -500 – 500 V CDM3) P_4.1.38 V 3) P_4.1.39 ESD Susceptibility VESD,CDM_corner -750 ESD Resistivity of corner Pins to GND – 750 CDM 1) Not subject to production test, specified by design. 2) ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002 3) ESD susceptibility, Charged Device Model “CDM” AECQ100-011 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Table 4 Functional Range Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Device Extended Supply Voltage VVIN Range 4.5 – V Device Nominal Supply Voltage VVIN Range 8 – 36 V – P_4.2.2 Power Stage Voltage Range VPOW 4.5 – 55 V 1) P_4.2.5 Digital Supply Voltage VDD 3 – 5.5 V – P_4.2.3 Junction Temperature Tj -40 – 150 °C – P_4.2.4 40 1) Number P_4.2.1 (parameter deviations possible) 1) Not subject to production test, specified by design. Note: Datasheet Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table 10 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface General Product Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 5 Parameter Junction to Case Junction to Ambient Symbol RthJC RthJA Values Min. Typ. Max. – 0.9 – – 25 – Unit Note or Test Condition Number K/W 1) 2) P_4.3.1 K/W 1) 3) 2s2p P_4.3.2 1) Not subject to production test, specified by design. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed to ambient temperature). Ta = 25°C; The IC is dissipating 1 W. 3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has 2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and 25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W. Datasheet 11 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply 5 Power Supply The TLD5501-2QV is supplied by the following pins: • VIN (main supply voltage) • VDD (digital supply voltage) • IVCC_EXT (supply for internal gate driver stages) The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and digital blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption may be observed at the VDD pin. The SPI and IO interfaces are supplied by the VDD pin. IVCC_EXT is the supply for the low side driver stages. This supply is used also to charge, through external Schottky diodes, the bootstrap capacitors which provide supply voltages to the high side driver stages. If no external voltage is available this pin must be shorted to IVCC, which is the output of an internal 5 V LDO. The supply pins VIN, VDD and IVCC_EXT have undervoltage detections. Undervoltage on VDD supply voltage prevents the activation of the gate driver stages and any SPI communication (the SPI registers are reset). Undervoltage on IVCC_EXT or IVCC voltages forces a deactivation of the driver stages, thus stopping the switching activity, but has no effect on the SPI register settings. Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a resistor divider from VIN to GND . If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator, stop switching, stop communications and reset all the registers. Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and IVCC/IVCC_EXT. VIN VREG (5V) R1 EN/INUVLO IVCC Internal pre-regulated voltage Supply Undervoltage detection R2 IVCC_EXT VREG digital VREG analog LS - Drivers PGND Undervoltage detection BSTx Bandgap Reference VDD Figure 4 Datasheet SPI & I/O Register Banks HS - Drivers LOGIC SWNx Power Supply Concept Drawing 12 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply Usage of EN/INUVLO pin in different applications The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption mode. An undervoltage threshold is fixed by placing an external resistor divider (A) in order to avoid low voltage operating conditions. This pin can be driven by a µC-port as shown in (B) (C). A Vin VIN Datasheet D Vin VIN VIN R1 EN/INUVLO Figure 5 Vin VIN R1 R2 C B Vin GND µC Port EN/INUVLO µC Port R2 GND EN/INUVLO EN/INUVLO GND GND Usage of EN/INUVLO pin in different applications 13 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply 5.1 Different Power States TLD5501-2QV has the following power states: • SLEEP state • IDLE state • LIMP HOME state • ACTIVE state The transition between the power states is determined according to these variables after a filter time of max. 3 clock cycles: • VIN level • EN/INUVLO level • IVCC level • IVCC_EXT level • VDD level • LHI level • DVCCTRL.IDLE bit state The state diagram including the possible transitions is shown in Figure 6. The Power-up condition is entered when the supply voltage VVIN exceed its minimum supply voltage threshold VVIN(ON). SLEEP When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset, independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption is low. Refer to parameters: IVDD(SLEEP), and IVIN(SLEEP). The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE. IDLE In IDLE state, the current consumption of the device can reach the limits given by parameter IVDD (P_5.3.4). The internal voltage regulator is working. Not all diagnosis functions are available (refer to Chapter 10 for additional informations). In this state there is no switching activity, independently from the supply voltages VIN, VDD, IVCC and IVCC_EXT. When VDD is available, the SPI registers are working and SPI communication is possible. Limp Home The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to maintain a defined current/voltage level on the output via a backup control circuitry. The backup control circuitry turns on required loads during a malfunction of the µC. For detailed info, refer to Chapter 8. When Limp Home state is entered, SPI registers are reset to their default values. In order to regulate the output current/voltage, it is necessary that VIN and IVCC_EXT are present and above their undervoltage threshold. If also VDD is above its undervoltage threshold, SPI communication is possible but only in read mode. ACTIVE In active state the device will start switching activity to provide power at the output only when PWMI1,2 = HIGH or LOOPCTRL_CH1,2.PWM_1,2 = HIGH. To start the Highside gate drivers HSGD1,2 the voltage level VBST1,2 - VSWN1,2 needs to be above the threshold VBST1,2 - VSWN1,2_UVth. In order to recharge the bootstrap capacitor, sporadic switching activity could also be observed when PWMI1,2 = LOW and LOOPCTRL_CH1,2.PWM_1,2 = Datasheet 14 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply LOW. In ACTIVE state the device current consumption via VIN and VDD is dependent on the external MOSFET used and the switching frequency fSW. Power-up LHI = LOW & EN/INUVLO = HIGH EN/INUVLO = LOW SLEEP EN/INUVLO = LOW LHI = HIGH & EN/INUVLO = HIGH EN/INUVLO = LOW LHI = HIGH IDLE VIN = HIGH & IVCC = HIGH & IVCC_EXT = HIGH & VDD = HIGH & DVCCTRL.IDLE = LOW VIN = LOW or IVCC = LOW or IVCC_EXT = LOW or VDD = LOW or DVCCTRL.IDLE = HIGH LIMP HOME EN/INUVLO = LOW LHI = LOW ACTIVE LHI = HIGH Figure 6 Simplified State Diagram 5.2 Different Possibilities to RESET the device There are several reset triggers implemented in the device. After any kind of reset, the Transmission Error Flag (TER) is set to HIGH. Under Voltage Reset: EN/INUVLO: When EN/INUVLO is below VEN/INUVLOth (P_5.3.7), the SPI interface is not working and all the registers are reset to their default values. In addition, the device enters SLEEP mode and the current consumption is minimized. VDD: When VVDD is below VVDD(UV) (P_5.3.6), the SPI interface is not working and all the registers are reset to their default values. Reset via SPI command: There is a command (DVCCTRL.SWRST = HIGH) available to RESET all writeable registers to their default values. Note that the result coming from the Calibration routine, which is readable by the SPI when LOOPCTRL_CH1,2.ENCAL_CH1,2 = HIGH, is not reset by the SWRST. Reset via Limp Home: When Limp Home state is detected the registers are reset to the default values. Datasheet 15 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply 5.3 Electrical Characteristics Table 6 EC Power Supply VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Power Supply VIN Input Voltage Startup VVIN(ON) – – 4.7 V VIN increasing; VEN/INUVLO = HIGH; VDD = 5 V; IVCC = IVCC_EXT = 10 mA P_5.3.1 Input Undervoltage switch OFF VVIN(OFF) – – 4.5 V VIN decreasing; VEN/INUVLO = HIGH; VDD = 5 V; IVCC = IVCC_EXT = 10 mA P_5.3.14 Device operating current IVIN(ACTIVE) – 6.2 9 mA 1) ACTIVE mode; VPWMI1,2 = 0 V P_5.3.2 VIN Sleep mode supply current IVIN(SLEEP) – – 1.5 µA VEN/INUVLO = 0 V; VCSN = VDD = 5 V; VIN = 13.5 V; VIVCC = VIVCC_EXT= 0 V P_5.3.3 Digital supply current IVDD – – 0.5 mA VIN = 13.5 V; fSCLK = 0 Hz; VPWMI1,2 = 0 V; VEN =VCSN = VDD = 5 V P_5.3.4 Digital Supply Sleep mode current IVDD(SLEEP) – – 1.5 µA VEN/INUVLO = 0 V; VCSN = VDD = 5 V; VIN = 13.5 V; VIVCC = VIVCC_EXT = 0 V P_5.3.5 Undervoltage shutdown threshold voltage VVDD(UV) 1 – 3 V VCSN = VDD; P_5.3.6 VSI = VSCLK = 0 V; SO from LOW to HIGH impedance 1.64 1.75 1.86 V – P_5.3.7 EN/INUVLO Rising Hysteresis VEN/INUVLO(hyst) – 90 – mV 1) P_5.3.8 EN/INUVLO input Current LOW IEN/INUVLO(LOW) 0.45 0.89 1.34 µA VEN/INUVLO = 0.8 V P_5.3.9 EN/INUVLO input Current HIGH IEN/INUVLO(HIGH) 1.1 2.2 3.3 µA VEN/INUVLO = 2 V P_5.3.10 Digital Power Supply VDD EN/INUVLO Pin characteristics Input Undervoltage falling Threshold Datasheet VEN/INUVLOth 16 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Power Supply Table 6 EC Power Supply (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number LHI Pin characteristics LOW level VLHI(L) 0 - 0.8 V – P_5.3.16 HIGH level VLHI(H) 2.0 - 5.5 V – P_5.3.17 L-Input pull-down current ILHI(L) 6 12 18 μA VLHI = 0.8 V P_5.3.18 H-Input pull-down current ILHI(H) 15 30 45 μA VLHI = 2.0 V P_5.3.19 tACTIVE – – 0.7 ms 1) P_5.3.11 Timings SLEEP mode to ACTIVE time VIVCC = VIVCC_EXT; CIVCC = 10 µF; VIN = 13.5 V; VDD = 5 V 1) Not subject to production test, specified by design Datasheet 17 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description 6 Regulator Description The TLD5501-2QV includes all of the functions necessary to provide constant current to the output as usually required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.5). In deep buck applications, due to duty cycle limitations (DBUCK_MIN) the device will enter pulse skipping mode in order to keep regulating the average output current, the ouptut ripple may increase. The minimum duty cycle is dependent by the fsw. 6.1 Regulator Diagram Description An analog current control loop (A5, A4 with complessive gain = IFBxgm) connected to the sensing pins FBL1,2, FBH1,2 regulates the output current. The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error in the output current loop is used to determine the appropriate duty cycle to get a constant output current. An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application boundary conditions. The inductor current for the current mode loop is sensed by the RSWCS resistor. RSWCS is used also to limit the maximum external switches / inductor current. If the Voltage across RSWCS exceeds its overcurrent threshold (VSWCS1,2_buck) the device reduces the duty cycle in order to bring the switches current below the imposed limit. The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations. The control loop logic block (LOGIC_CHx) provides a PWM signal to two internal gate drivers. The gate drivers (HSGD1,2 and LSGD1,2) are used to drive external MOSFETs. Once VSOFT_START1,2 exceeds VSoft_start1,2_LOFF or V(FBH1,2-FBL1,2) exceeds V(FBH1,2-FBL1,2)_VALID thresholds, TLD5501-2QV forces CCM regulation mode. The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage across RFB sets the output current. The output current is fixed via the SPI parameter (LEDCURRADIM_CH1,2.ADIMVAL_CH1,2 = 11110000B = default at 100%) plus an offset trimming (LEDCURRCAL_CH1,2.CALIBVAL_CH1,2 = 0000B = default in the middle of the range). Refer to Chapter 8.1 for more details. Datasheet 18 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description IINx VINx IOUTx RFBx CHx_Mode Buck Regulator COUT VOUTx ISWCSx FBHx FBLx - + + A1 A7 - SWCSx + A5 HSGDx - RSWCSx LOGIC CHx + SGNDx + A6 LSGDx - - A2 - CLK 1 A4 ISoft_Start_PU + SETx DAC_OUT 0 1k DAC_OFF_CHx LHI COMPx SOFT START LOGIC ISoft_Start_PD SOFT STARTx ICOMPx RCOMPx VSST VCOMPx CSOFT_START CCOMPx Figure 7 Datasheet Regulator Block Diagram (similar for both Channels) - TLD5501-2QV 19 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description 6.2 Adjustable Soft Start Ramp The soft start routine has two functionalities: • Fault management: fault mask and wait-before-retry time, on rising and falling edge of SOFT_START1,2 respectively (Figure 8 and Chapter 10.2) • To limit the current through the inductor and the external MOSFET switches during initialization to minimize potential overshoots at the output. The soft start routine is applied: • At startup (first PWM rise after IDLE to ACTIVE transition) • After Output Short to GND detection • After channel stop via low analog dimming value (See Chapter 8) The soft start timing is defined by a capacitor placed at the SOFT_START pin and the pull-up and pull-down current sources (ISoft_Start1,2_PU, ISoft_Start1,2_PD). Minimum value for soft start capacitor has to be designed such that, at startup, the output voltage exceeds the short to ground threshold before the soft start voltage reaches VSOFT_START1,2_LOFF. Minimum temperature and minimum input voltage shall be considered as worst case condition for previously mentioned dimensioning. Soft Start rising edge time is approximately: _ , =  _ , _ ∙ (6.1)  _ ,  _ , _ The Soft Start routine limits the inrush current by clamping the COMP pin through a buffer as in Figure 7. Therefore, this functionality is effective only when soft start capacitor is sufficiently larger than the COMP capacitor. If a short on the output is detected, a pull-down current source ISOFT_START1,2_PD (P_6.4.59) is activated. This current brings down the VSOFT_START1,2 until VSOFT_START1,2_RESET (P_6.4.61) is reached, then the pull-up current source ISOFT_START1,2_PU (P_6.4.58) turns on again, if PWMI1,2 is high, see Figure 8. If the fault condition hasn’t been removed until VSOFT_START1,2_LOFF (P_6.4.60) is reached, the pull-down current source turns back on again, initiating a new cycle. This will continue until the fault is removed. During rising edge of soft start, the internal PWM is extended until one of the 2 following conditions is reached: • Until VSOFT_START1,2 exceeds VSoft_Start1,2_LOFF (P_6.4.60) • Until VFBH1,2-FBL1,2 exceeds V(FBH1,2-FBL1,2)_VALID (P_6.6.1) Datasheet 20 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description Short to GND protection 8 clock cycles VFBx VVFB_S2G1 PWMIx SWNx SHORT DETECTION ISOFT_STARTx SOFT_STARTx Vsoft_Start1,2_LOFF Vsoft_Start1,2_RESET Application Status Normal Operation Vout shorted to GND Event Vout short to GND applied Normal Operation Event Vout short to GND removed Figure 8 Soft Start timing diagram on a short to ground detected by the VFBx pin 6.3 Switching Frequency setup The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency with an external resistor according to the graph in Figure 9 or the following approximate formulas. f SW [ kHz ] = 5375 * ( R FREQ [ k Ω ]) − 0 .8 (6.2) RFREQ [kΩ] = 46023 * ( f SW [ kHz ]) −1.25 (6.3) Figure 9 Datasheet Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ 21 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description 6.4 Flexible current sense The flexible current sense implementation enables highside and lowside current sensing. The Figure 10 displays the application examples for the highside and lowside current sense concept. VIN VIN DCDC Channel1,2 Highside Sensing DCDC Channel1,2 Lowside Sensing FBH1,2 FBL1,2 Figure 10 Datasheet FBH1,2 FBL1,2 Highside and lowside current sensing - TLD5501-2QV 22 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description 6.5 Programming Output Voltage (Constant Voltage Regulation) For a voltage regulator, the output voltage can be set by selecting the values RFBx1, RFBx2 and RFBx3 according to the following Equation (6.4):   V  V VOUT1,2 =  I FBH1,2 + FBH1,2−FBL1,2  ⋅ RFB11,2 +  FBH1,2−FBL1,2 − I FBL1,2  ⋅ RFB31,2 + VFBH1,2−FBL1,2 RFB21,2    RFB21,2  (6.4) After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits ADIMVAL_CH1,2. If Analog dimming is performed, due to the variations on the IFBL (IFBL1,2_HSS (P_6.4.52) and IFBL1,2_LSS (P_6.4.54)) or IFBH (IFBH1,2_HSS (P_6.4.51) and IFBH1,2_LSS (P_6.4.53)) current on the entire voltage spanning, a non linearity on the output voltage may be observed. To minimize this effect RFBx resistors should be properly dimensioned. VOUT1 VOUT2 RFB12 RFB22 RFB32 IFBH2 FBH1 IFBH1 FBL1 IFBL1 FBH2 IFBL2 FBL2 RFB11 RFB21 RFB31 Figure 11 Programming Output Voltage (Constant Voltage Regulation) Note: In case of no load condition, if the voltage on the output is above V(FBH1,2-FBL1,2)_VALID threshold, the output capacitor may be discharged during the soft-start sequence. Proper sizing of external components (e.g. increasing the output capacitor or decreasing the inductor values) is recommended to avoid negative output voltage. Alternatively it is recommended to add a clamping diode on the output as shown in Figure 38. Datasheet 23 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description 6.6 Electrical Characteristics Table 7 EC Regulator VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 145.5 150 154.5 mV ADIM.ADIMVAL_CH P_6.4.43 1,2 = 11110000B; Differential signal (not referred to GND 12 15 18 mV ADIM.ADIMVAL_CH P_6.4.47 1,2 = 00011000B; Differential signal (not referred to GND) Calibration Procedure not performed 110 120 130 mV VSET = 1.4 V or P_6.6.1 ADIM.ADIMVAL_CH1,2 = 11110000B Regulator: V(FBH1,2-FBL1,2) thresholds V(FBH1,2FBL1,2) V(FBH1,2-FBL1,2) thresholds @ analog dimming 10% V(FBH1,2FBL1,2)_10 V(FBH-FBL) valid range threshold V(FBH1,2- FBH1,2 Bias currents @ highside sensing setup IFBH1,2_HSS 65 100 156 µA VFBL1,2 = 7 V; P_6.4.51 VFBH1,2 - FBL1,2 = 150 mV FBL1,2 Bias currents @ highside sensing setup IFBL1,2_HSS 17 30 45 µA VFBL1,2 = 7 V; P_6.4.52 VFBH1,2 - FBL1,2 = 150 mV FBH1,2 Bias currents @ lowside sensing setup IFBH1,2_LSS -7.5 -4 -2.5 µA VFBL1,2 = 0 V; P_6.4.53 VFBH1,2 - FBL1,2 = 150 mV FBL1,2 Bias currents @ lowside sensing setup IFBL1,2_LSS -45 -30 -20 µA VFBL1,2 = 0 V; P_6.4.54 VFBH1,2 - FBL1,2 = 150 mV FBH-FBL High Side sensing VFBH_HSS_inc 1.9 entry threshold 2 2.1 V 1) VFBH1,2 increasing P_6.9.1 FBH-FBL High Side sensing VFBH_HSS_dec 1.65 exit threshold 1.75 1.85 V 1) VFBH1,2 decreasing P_6.9.2 FBL1,2)_VALID OUT Current sense Amplifier gm IFBxgm – 890 – µS 1) P_6.4.10 Output Monitor Voltages VIOUTMON1,2 1.33 1.4 1.47 V P_6.5.1 Minimum BUCK Duty Cycle DBUCK_MIN – 4 5.5 % Maximum BUCK Duty Cycle DBUCK_MAX 90.5 92 94 % VSWCS1,2_buck -60 -50 -40 mV VFBH1,2 - FBL1,2 = 150 mV 1) fsw = 300 kHz 1) fsw = 300 kHz 1) ISoft_Start1,2_P 21 27 34 µA VSoft_Start1,2 = 1 V Switch Peak Over Current Thresholds - BUCK P_6.8.2 P_6.5.2 P_10.8.25 Soft Start Soft Start1,2 pull up currents Datasheet P_6.4.58 U 24 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description Table 7 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Soft Start1,2 pull down currents ISoft_Start1,2_P 2.1 Typ. Max. Unit Note or Test Condition Number 2.7 3.4 µA VSoft_Start1,2 = 1 V P_6.4.59 1.75 1.85 V – P_6.4.60 0.2 0.3 V – P_6.4.61 2 2.1 V 1) D Soft Start1,2 Latch-OFF Thresholds VSoft_Start1,2_ 1.65 Soft Start1,2 Reset Thresholds VSoft_Start1,2_ 0.1 LOFF RESET Soft Start1,2 Voltage during VSoft_Start1,2_ 1.9 regulation reg No Faults P_6.9.3 Oscillator Switching Frequency fSW 285 300 315 kHz Tj = 25°C; RFREQ= 37.4 kΩ; ENSPREAD = LOW P_6.4.23 SYNC Frequency fSYNC 200 – 700 kHz – P_6.4.24 SYNC Turn On Threshold VSYNC,ON 2 – – V – P_6.4.25 SYNC Turn Off Threshold VSYNC,OFF – – 0.8 V – P_6.4.26 SYNC High Input Current ISYNC,H 15 30 45 µA VSYNC = 2.0 V; P_6.4.62 SYNC Low Input Current ISYNC,L 6 12 18 µA VSYNC = 0.8 V; P_6.4.63 Gate Driver for external Switch Gate Driver undervoltage threshold VBST1,2VSWN1,2_UVth 3.4 VBST1,2VSWN1,2_UVth – 4 V VBST1,2 - VSWN1,2 P_6.4.64 decreasing; Differential signal (not referred to GND) HSGD1,2 NMOS driver onstate resistance (Gate Pull Up) RDS(ON_PU)HS 1.4 2.3 3.7 Ω VBST1,2 - VSWN1,2 = 5 V; Isource = 100 mA P_6.4.28 HSGD1,2 NMOS driver onstate resistance (Gate Pull Down) RDS(ON_PD) HS 0.6 1.2 2.2 Ω VBST1,2 - VSWN1,2 = 5 V; Isink = 100 mA P_6.4.29 LSGD1,2 NMOS driver onstate resistance (Gate Pull Up) RDS(ON_PU)LS 1.4 2.3 3.7 Ω VIVCC_EXT = 5 V; Isource = 100 mA P_6.4.30 LSGD1,2 NMOS driver onstate resistance (Gate Pull Down) RDS(ON_PD)LS 0.4 1.2 1.8 Ω VIVCC_EXT = 5 V; Isink = 100 mA P_6.4.31 Datasheet 25 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Regulator Description Table 7 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – – mA 1) Number HSGD1,2 Gate Driver peak sourcing current IHSGD1,2_SRC 380 HSGD1,2 Gate Driver peak sinking current IHSGD1,2_SNK 410 LSGD1,2 Gate Driver peak sourcing current ILSGD1,2_SRC 370 LSGD1,2 Gate Driver peak sinking current ILSGD1,2_SNK 550 LSGD1,2 OFF to HSGD1,2 ON delay tLSOFF- 15 30 40 ns 1) P_6.4.36 35 65 95 ns 1) P_6.4.37 HSGD1,2 OFF to LSGD1,2 ON delay P_6.4.32 VHSGD1,2 - VSWN1,2 = 1 V to 4 V; VBST1,2 - VSWN1,2 = 5 V – – mA 1) P_6.4.33 VHSGD1,2 - VSWN1,2 = 4 V to 1 V; VBST1,2 - VSWN1,2 = 5 V – – mA 1) P_6.4.34 VLSGD1,2 = 1 V to 4 V; VIVCC_EXT = 5 V – – mA 1) P_6.4.35 VLSGD1,2 = 4 V to 1 V; VIVCC_EXT = 5 V HSON_delay tHSOFFLSON_delay 1) Not subject to production test, specified by design Datasheet 26 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Digital Dimming Function 7 Digital Dimming Function PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string. 7.1 Description A PWM signal can be transmitted to the TLD5501-2QV in two manners, as described below. An HIGH PWM value, communicated in either of the two ways, always overrides a possible LOW from the other with a resulting enable of the gate drivers. PWM via direct interface The PWMI1,2 pin can be fed with a pulse width modulated (PWM) signals, this enables when HIGH and disables when LOW the gate drivers of the main switches. PWM via SPI A pulse width modulated (PWM) signal can be sent via SPI interface by changing the value of the LOOPCTRL_CH1,2.PWM_1,2 bit. LOOPCTRL_CH1,2.PWM_1,2=HIGH/LOW respectively enables/disables the gate drivers of the main switches. µC Digital dimming 1 PWM1 PWMI1 PWM2 Digital dimming 2 PWMI2 +3.3V or +5V SPI Interface Figure 12 VDD CSN SI SO SCLK VSS AGND Digital Dimming Overview To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state should not be used to suspend the output current for long time intervals. To stop a single channel in a safe manner see Chapter 8. To stop both channels DVCCTRL.IDLE=HIGH or EN/INUVLO=LOW can be used. Datasheet 27 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Digital Dimming Function VEN/INUVLO t ACTIVE VEN/INUVLOth t VIVCC_EXT_RTH,d +VIVCCX_HYST t t PWMI,H TPWMI VPWMI VPWMI,ON VPWMI,OFF t Switching activity t ILED t VIOUTMON 200mV t Softstart Power ON Figure 13 Datasheet Normal Dim Normal Dim Normal Dim Gate ON Gate OFF Gate ON Gate OFF Gate ON Gate OFF Diagnosis ON Diag OFF Diag ON Diag OFF Diag ON Diag OFF Timing Diagram LED Dimming and Start up behavior example ( VVDD and VVIN stable in the functional range and not during startup) 28 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Digital Dimming Function 7.2 Electrical Characteristics Table 8 EC Digital Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number PWMI Input: PWMI1,2 Turn On Thresholds VPWMI1,2,ON 2 – – V – P_7.2.6 PWMI1,2 Turn Off Thresholds VPWMI1,2,OFF – – 0.8 V – P_7.2.7 PWMI1,2 High Input Currents IPWMI1,2,H 15 30 45 µA VPWMI1,2 = 2.0 V P_7.2.9 PWMI1,2 Low Input Currents IPWMI1,2,L 6 12 18 µA VPWMI1,2 = 0.8 V P_7.2.10 Datasheet 29 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Analog Dimming 8 Analog Dimming The analog dimming feature allows further control of the output current. This approach is used to: • Reduce the default current in a narrow range to adjust to different binning classes of the used LEDs. • Adjust the load current to enable the usage of one hardware for several LED types where different current levels are required. • Reduce the current at high temperatures (protect LEDs from overtemperature). 8.1 Description The analog dimming feature is adjusting the average load current level via the control of the feedback error Amplifier voltage (VFBH1,2-FBL1,2). The LEDCURRCAL_CH1,2.DAC_OFF_CH1,2 bit-field is used to switch the error amplifier reference from the internal DAC circuitry to the SET1,2 pin during the active state (refer to Figure 7). This provides customers higher dimming resolution via the µC and the SET1,2 pin (refer to picture 1 displayed in Figure 17). When LEDCURRCAL_CH1,2.DAC_OFF_CH1,2 = LOW ,the current adjustment is done via a 8BIT SPI parameter (LEDCURRADIM_CH1,2.ADIMVAL_CH1,2). Refer to Figure 14. If LEDCURRADIM_CH1,2.ADIMVAL_CH1,2 is set to 00000000B the channel stops the switching activity and will restart with a soft start routine as soon as a different value is programmed. VFBH1,2 - FBL1,2 150mV b´11110000 Bitcode 8-bit SPI adjustment Figure 14 Analog Dimming Overview Analog dimming adjustment during Limp Home state: To enter in Limp Home state the LHI pin must be HIGH. Note: If the PWMI1,2 and the EN/INUVLO are not set to HIGH, it is not possible to enable switching during Limp Home state. In Limp Home state the analog dimming control is done via the SET1,2 pins. A Resistor divider between IVCC/IVCC_EXT, SET1,2 and GND is used to fix a default load current/voltage value (refer to Figure 15 below). Datasheet 30 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Analog Dimming VPOW CIN1 FAIL SAFE Circuit Set HIGH to activate Channel1 IVCC_ext IVCC PWMI1_LH VIN EN C IVCC PWMI1 POWER STAGE Channel 1 RFB 1 SWCS1 IVCC SGND1 R CS1 COUT1 Channel 1 R2 RVFBL1 VFB1 FBH1 SET1 FB L1 R1 default output current/voltage adjustment SPI Writing disabled during SPI Limp Home state R VFBH1 PGND1 CSN SI SO SCLK VPOW LIMPHOME FAIL SAFE Circuit HIGH LHI PWMI2_LH FAIL SAFE Circuit Set HIGH to activate Channel2 POWER STAGE Channel 2 PWMI2 RFB 2 SWCS2 Channel 2 IVCC COUT2 R VFBH2 RVFBL2 R4 SET2 FB L2 PGND2 VSS Figure 15 RCS2 VFB2 FBH2 R3 default output current/voltage adjustment SGND2 AGND Limp Home state schematic overview Using the SET1,2 pins to adjust the output currents: For the calculation of the output current IOUT the following Equation (8.1) is used: I OUT 1, 2 = V FBH 1, 2 − V FBL 1, 2 R FB 1, 2 (8.1) A decrease of the average output current can be achieved by controlling the voltage at the SET1,2 pin (VSET1,2) between 0.2 V and 1.4 V. The mathematical relation is given in the Equation (8.2) below: I OUT 1 , 2 = V SET 1 , 2 − 200 mV R FB 1 , 2 ⋅ 8 (8.2) If VSET1,2 is 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators. To assure the switching activity is stopped and IOUT = 0, VSET1,2 has to be < 100 mV, see Figure 16. The channel is then ready to restart with the soft start routine when VSET1,2 is pulled above 200 mV. Datasheet 31 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Analog Dimming VFBH1,2 - FBL1,2 150mV 100mV 0mV 200mV 1.4V Analog Dimming Disabled Analog Dimming Enabled Analog Dimming Overview 2 D/A-Output2 SET2 VSET1 VSET2 VSET1 µC GND 3 Cfilter2 CREF SET1 RSET2 Cfilter1 Rfilter GND SET2 VSET2 RSET1 VSET1 SET2 GND SET2 VSET1,2 ~ IVCC Cfilter GND µC_supply PWM1 PWM output1 PWM output2 µC (e.g. XC2000) Datasheet SET1 IVCC Rthermistor2 Rthermistor1 IVCC SET1 Figure 17 Cfilter2 Cfilter1 4 CREF 5 IVCC RSET11 SET1 RSET12 CREF D/A-Output1 VSET2 µC_supply RSET22 1 RSET21 Figure 16 VSET1,2 1.5V PWM2 Rfilter1 SET1 Rfilter2 Cfilter2 SET2 VSET1 Cfilter1 VSET2 GND Different use cases for analog dimming pin SET1,2 32 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Analog Dimming The relation between the analog dimming and the V(FBH1,2-FBL1,2)_VALID threshold is shown in Figure 18. When SET1,2 pin is used to set the analog dimming, the V(FBH1,2-FBL1,2)_VALID threshold is a direct partition of the SET voltage. Thus, in case the voltage on SET pin is above 100% of analog dimming the V(FBH1,2-FBL1,2)_VALID threshold could not be exceeded by the regulated voltage V(FBH1,2-FBL1,2) with the following implications: • The forced CCM mode is applied only once the VSOFT_START1,2 exceeds the VSOFT_START1,2_LOFF • During rising edge of the soft start the internal PWM is extended always until the VSOFT_START1,2 exceeds the VSOFT_START1,2_LOFF VFBH1,2 - FBL1,2_VALID 120mV 20mV 18% 100% Figure 18 Relation between Analog Dimming V(FBH1,2-FBL1,2)_VALID 8.2 LED current calibration procedure Analog dimming The LED current calibration procedure improves the accuracy during analog dimming. In order to be most effective, this routine has to be performed in the application, when the TLD5501-2QV temperature and the output voltage are the ones in which the driver has to be accurate. The output current must be 0 during the procedure run. The optimum should be to re-calibrate the output periodically every time the application has PWMI1,2=LOW for a sufficent long time . Current calibration procedure: • Power the Load with a low analog dimming value (for example 10%) • Set PWMI1,2 = LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions and bring the output current to 0) • Quickly (to avoid Vout drifts) µC enables the calibration routine: LOOPCTRL_CH1,2.ENCAL_CH1,2 = HIGH • Quickly (to avoid Vout drifts) µC starts the calibration: LEDCURRCAL_CH1,2.SOCAL_CH1,2 = HIGH • Waiting time (needed to internally perform the calibration routine) → aprox. 200 µs • TLD5501-2QV will set the FLAG: LEDCURRCAL_CH1,2.EOCAL_CH1,2 = HIGH, when calibration routine has finished • Reconnect the load • The Output current is automatically adjusted to a low offset and more accurate analog dimming value Datasheet 33 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Analog Dimming Once the Calibration routine is correctly performed, the output current accuracy with analog dimming = 10% (LEDCURRADIM_CH1,2.ADIMVAL_CH1,2 = 24) is 10%. The Calibration routine is not affecting the accuracy at 100% analog dimming. The ENCAL_CH1,2 Bits affect both device operation and CALIBVAL_CH1,2 reading result: • ENCAL_CH1,2 = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read back from CALIBVAL_CH1,2 • ENCAL_CH1,2 = LOW: SPI value written in CALIBVAL_CH1,2 is used by internal circuitry and can be read back; calibration routine start is inhibited As a result, μC can use a stored result from a previously performed calibration to directly impose the desired value without waiting for a new routine to finish. 8.3 Electrical Characteristics Table 9 EC Analog Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Source currents on SET1,2 Pin Symbol ISET1,2_source Values Min. Typ. Max. – – 1 Unit Note or Test Condition Number µA 1) P_8.3.5 VSET1,2 = 0.2 V to 1.4 V 1) Specified by design: not subject to production test Datasheet 34 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Linear Regulator 9 Linear Regulator The TLD5501-2QV features an integrated voltage regulator for the supply of the internal gate driver stages. Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative gate driver supply if required. 9.1 IVCC Description When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal gate drivers with a typical voltage of 5 V and current up to ILIM (P_9.2.2). An external output capacitor with low ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the external MOSFET switches will draw transient currents from the linear regulator and its output capacitor (Figure 19, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC (P_9.2.4). Alternative IVCC_EXT Supply Concept: The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers. This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 19, drawing B). Integrated undervoltage protection for the external switching MOSFET: An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This undervoltage reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls below their undervoltage Reset switch OFF Thresholds VIVCC_RTH,d (P_9.2.9) and VIVCC_EXT_RTH,d (P_9.2.5). In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching activity. The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the external logic level N-channel MOSFETs. A VIN Internal VREG B IVCC Internal VREG VIN Power On Reset IVCC_EXT Datasheet Power On Reset IVCC_EXT Gate Drivers Figure 19 IVCC External VREG Gate Drivers Voltage Regulator Configurations 35 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Linear Regulator 9.2 Electrical Characteristics Table 10 EC Line Regulator VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number IVCC Output Voltage VIVCC 4.8 5 5.2 V VIN = 13.5 V; 0.1 mA ≤ IIVCC ≤ 50 mA P_9.2.1 Output Current Limitation ILIM 70 90 110 mA 1) P_9.2.2 Drop out Voltage (VIN VIVCC) VDR – 200 350 mV VIN = 5 V; IIVCC = 10 mA P_9.2.3 IVCC Buffer Capacitor CIVCC 10 – – µF 1) 2) P_9.2.4 V 3) P_9.2.5 VIVCC = 4 V IVCC_EXT Undervoltage VIVCC_EXT_R 3.7 Reset switch OFF TH,d Threshold 3.9 IVCC Undervoltage Reset VIVCC_RTH,d 3.7 switch OFF Threshold 3.9 IVCC and IVCC_EXT VIVCCX_HYST 0.335 Undervoltage Hysterisis 0.365 4.1 VIVCC_EXT decreasing 4.1 V 3) P_9.2.9 VIVCC decreasing 0.395 V VIVCC increasing; VIVCC_EXT increasing P_9.2.6 1) Not subject to production test, specified by design 2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum. Use capacitors with LOW ESR 3) Selection of external switching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be considered Datasheet 36 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions 10 Protection and Diagnostic Functions 10.1 Description The TLD5501-2QV has integrated circuits to diagnose and protect against overcurrent, overvoltage, open load, short circuits of the load and overtemperature faults. Furthermore, the device provides a 2 Bit information of ILED1,2 by the SPI to the µC. In IDLE state, only the Over temperature Shut Down, Over Temperature Warning, IVCC or IVCC_EXT Undervoltage Monitor, VDD or VEN/INUVLO Undervoltage Monitor are reported according to specifications. In Figure 20 a summary of the protection, diagnostic and monitor functions is displayed. Protection and Diagnostic Open Load SPI Output Overvoltage Output Overcurrent SPI STD Diagnosis SPI OR SPI No output currents Short at the Load SPI Device Overtemperature SPI Linear Regul ators OFF OR (only IVCC disabled in case of overtemperature) Input Undervoltage Monitoring Read-back via SPI 2BIT data IOUT1 2BIT data IOUT2 IOUTMON1 KILIS Factor 8 IOUTMON2 KILIS Factor 8 Figure 20 Protection, Diagnostic and Monitoring Overview Note: A device Overtemperature event overrules all other fault events! Datasheet 37 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions 10.2 Output Overvoltage, Overcurrent, Open Load, Short circuit protection The VFB pin measures the voltage on the application output and in accordance with the populated resistor divider, short to ground, open load and output overvoltage thresholds are set. Refer to Figure 22 and Figure 21 for more details. VVFB1,2 Overvoltage VVFB1,2_OVTH = fixed Open LOAD VVFB1,2_OL,rise = fixed Normal Operation VVFB1,2_S2G = adjustable Short Circuit e.g. 50V Threshold can be adjusted via SPI Figure 21 VOUT1,2 Definition of Protection Ranges VOUT1,2 VIN1,2 DC/DC Regulator COUT1,2 IOUT1,2 RFB1,2 RVFBH1,2 VVFB1,2_OVTH VVFB1,2_OL,rise RVFBL1,2 Figure 22 VFB Protection Pin - Overview 10.2.1 Short Circuit protection VVFB1,2_S2G The device detects a short circuit at the output if this condition is verified: • The pin VFB1,2 falls below the threshold voltage VVFB1,2_S2G for at least 8 clock cycles During the rising edge of the Soft Start the short circuit detection via VFB1,2 is ignored until VSOFT_START1,2_LOFF (see Figure 8). After a short circuit detection, the SPI flag (SHRTLED_CH1,2) in the FAULTS_CH1,2 register is set to HIGH and the gate drivers stop delivering output current. The Device will auto restart with the soft start routine described in Chapter 6.2. Datasheet 38 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions Voltage dividers between VOUT1,2, VFB1,2 pins and AGND are used to adjust the application short circuit thresholds Vshort_led1,2 following Equation (10.1). V short _ led 1, 2 = VVFB 1, 2 _ S 2 G ⋅ RVFBH 1, 2 + RVFBL 1, 2 (10.1) RVFBL 1, 2 The short circuit threshold voltage VVFB1,2_S2G (P_10.8.17) is set by 4-Bits in the SPI register MFSSETUP1_CH1,2.LEDCHAIN_CH1,2 as shown in Table 11. The adjustable short circuit threshold VVFB1,2_S2G enables applications with a large VOUT operation range. The MFSSETUP1_CH1,2.LEDCHAIN_CH1,2 register allows configuration of the short circuit threshold in 16 Steps. The step size depends on the sizing of the RVFBH1,2 and RVFBL1,2 resistors. In order to have proper short circuit detection MFSSETUP1_CH1,2.LEDCHAIN_CH1,2 should be calculated as shown in Equation (10.2). 𝐿𝐸𝐷𝐶𝐻𝐴𝐼𝑁_𝐶𝐻1,2 = 𝑉𝑠ℎ𝑜𝑟𝑡 _𝑙𝑒𝑑 ∙ 𝐾𝑉𝐹𝐵1,2 45𝑚𝑉 (10.2) Where KVFB=RVFBL1,2/(RVFBH1,2 + RVFBL1,2) and Vshort_led is the desired short circuit threshold value at VOUT1,2. The Table 11 below displays the relationship between the bitcode and the short circuit threshold voltage VVFB1,2_S2G based on an example (resistor divider RVFBH = 56 kΩ, RVFBL1,2 = 1.5 kΩ). The application overvoltage protection is instead not dependent by LEDCHAIN_CH1,2 and, based on the Equation (10.3) for this particular resistor divider is fixed to 56 V. Table 11 Adjustable Short Circuit threshold overview LEDCHAIN_CH1,2 VOUT_OVLO k = RVFBL / (RVFBH Vopen_load + RVFBL) Vshort_led (V) (VFB1,2_S2G / k) VVFB1,2_S2G(V) 1 56.0 0.026 51.4 1.7 0.045 2 (default) 56.0 0.026 51.4 3.5 0.091 3 56.0 0.026 51.4 5.2 0.136 4 56.0 0.026 51.4 7.0 0.182 5 56.0 0.026 51.4 8.7 0.227 6 56.0 0.026 51.4 10.4 0.272 7 56.0 0.026 51.4 12.2 0.318 8 56.0 0.026 51.4 13.9 0.363 9 56.0 0.026 51.4 15.7 0.409 10 56.0 0.026 51.4 17.4 0.454 11 56.0 0.026 51.4 19.2 0.499 12 56.0 0.026 51.4 20.9 0.545 13 56.0 0.026 51.4 22.6 0.590 14 56.0 0.026 51.4 24.4 0.636 15 56.0 0.026 51.4 26.1 0.681 0 56.0 0.026 51.4 27.9 0.726 Datasheet 39 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions Note: If the short circuit condition disappears, the device will re-start with the soft start routine as described in Chapter 6.2 10.2.2 Overvoltage Protection Voltage dividers between VOUT1,2, VFB1,2 pins and AGND are used to adjust the overvoltage protection thresholds (refer to Figure 22). To fix the overvoltage protection thresholds the following Equation (10.3) is used: VOUT1,2 _ OV _ protected = VVFB1,2 _ OVTH ⋅ RVFBH1,2 + RVFBL1,2 RVFBL1,2 (10.3) If VVFB1,2 gets higher than its overvoltage thresholds VVFB1,2_OVTH , the SPI flags (OUTOV_CH1,2) in the FAULTS_CH1,2 registers are set to HIGH and the gate drivers stop switching for output regulation (High Impedance, both MOS are OFF). When VVFB1,2_OVTH- VVFB1,2_OVTH,HYS threshold is reached the device will auto restart. If the FAULTS_CH1,2.OUTOVLAT_CH1,2 bits are set to HIGH the overvoltage protection is changed into latched behavior and the µC has to set the DVCCTRL.CLRLAT bit to reset the OUTOV flag and restart the switching activities. 10.2.3 Overcurrent on Load Protection If the output current IOUT ( or the voltage VOUT for voltage regulators) exceeds the nominal value, driving V(FBH1,2FBL1,2) > VFBHL_OCTH,rise , the SPI flag OUTOC_CH1,2 in the FAULTS_CH1,2 register is set to HIGH and the output stage is set to High Impedance (both MOS are OFF), reducing the risk of load damage. IOUT and VOUT are shown in Figure 22 The device recovers automatically from the overcurrent protection when V(FBH1,2-FBL1,2) < VFBHL_OCTH,fall . 10.2.4 Open Load Detection To reliably detect an open load event, two conditions need to be observed for at least 8 clock cycles: 1) Voltage threshold: VVFB1,2 > VVFB1,2_OL,rise 2) Output current information: V(FBH1,2-FBL1,2) < VFBH1,2_FBL1,2_OL During the rising edge of the Soft Start the open load detection is ignored until VSOFT_START1,2_LOFF. After an open load detection, the SPI flag (OL_CH1,2) in the FAULTS_CH1,2 register is set to HIGH without affecting the gate drivers activity. An Open Load error causes an increase of the output voltage as well. An Overvoltage condition could be reported in combination with an Open Load error. 10.3 Output current Monitoring The output current can be monitored through an analog output pin and an SPI routine. The IOUTMON1,2 pin provides a linear indication of the current flowing through the LEDs. The following Equation (10.4) is applicable: V IOUTMON 1, 2 = 200 mV + I OUT 1, 2 ⋅ R FB 1, 2 ⋅ 8 (10.4) The nominal output impedence of the IOUTMON1,2 is 24 kΩ. Purpose of the SPI current monitor routine is to verify if the system is in loop. Datasheet 40 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions • The output of the Led Current Sense is compared to the output of the Analog Dimming DAC • The comparator works like a 2 bit window ADC around 8 bit DAC output To execute the current monitor routine the CURRMON_CH1,2.SOMON_CH1,2 bit has to be set HIGH and the result is ready when CURRMON_CH1,2.EOMON_CH1,2 is read HIGH. The result of the monitor routine for the output current is reported on the CURRMON_CH1,2.LEDCURR_CH1,2 bits. OUT1,2 ADC out 2Bit Monitoring IOUTMON1,2 Vint_supply 11b V_sense_out + IDC_offset - IIN_feedback Latch Datasheet ADC in ADC out + ADC CLK - DAC Vref_int Figure 23 01b ADC CLK ADC Latch 8 bit resolution 4 bit calibration 00b EA COMP1,2 VIOUT_target +25% to LED Load V_sense_in FBL1,2 10b Logic VIOUT_target RFB1,2 VIOUT_target VFBH1,2-FBL1,2 feedback + IOUT_sense - VIOUT_target -25% FBH1,2 Output Current Monitoring General Overview 41 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions 10.4 Device Temperature Monitoring A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning temperature, the temperature warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again). If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC regulator are shut down as described in Figure 24 and the temperature shut-down bit: TSD is set to HIGH. The TSD bit is latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior. Note: The Device will start up with a soft start routine after a TSD condition disappear. Tj TjSD,hyst TjSD TjW TjSD_exit TjW_exit TjW,Hyst t xSGDx Gate Drivers autorestart Operating t OFF IVCC 5V IVCC autorestart OFF t TW bit 1 NO ERROR TW bit is reset automatically 0 t 1 NO ERROR 0 Figure 24 Datasheet Warning TSD error bit TSD error bit latched until next reset or CLRLAT t Device Overtemperature Protection Behavior 42 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions 10.5 Electrical Characteristics Table 12 EC Protection and Diagnosis VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Unit Note or Test Condition Number Typ. Max. 0.091 0.101 V VVFB1,2 decreasing; P_10.8.17 MFSSETUP1_CH1,2. LEDCHAIN_CH1,2 = 0010B Short Circuit Protection Short to GND thresholds VVFB1,2_S2G 0.081 by VFB1,2 voltage (default) Temperature Protection: Thermal Warning junction temperature Tj,W 125 140 155 °C 1) P_10.8.2 Temperature warning Hysteresis Tj,W,hyst – 10 – °C 1) P_10.8.3 Over Temperature Shutdown Tj,SD 160 175 190 °C 1) P_10.8.4 Over Temperature Shutdown Hysteresis Tj,SD,hyst – 10 – °C 1) P_10.8.5 1.46 1.50 V 40 58 mV Overvoltage Protection: VFB1,2 Over Voltage Feedback Threshold Output Over Voltage Feedback Hysteresis VVFB1,2_OVT 1.42 P_10.8.18 H VVFB1,2_OVT 25 1) P_10.8.19 Output Voltage decreasing H,HYS Overcurrent Protection IOUT Overcurrent rising Threshold VFBHL_OCT 185 IOUT Overcurrent falling Threshold VFBHL_OCT 165 205 225 mV Differential signal (not referred to GND) P_10.8.30 185 205 mV Differential signal (not referred to GND) P_10.8.31 1.34 1.39 V VFBH1,2-FBL1,2 = 0 V P_10.8.20 15 24 mV VVFB1,2 = 1.4 V; Differential signal (not referred to GND) P_10.8.21 1.28 1.33 V VFBH1,2-FBL1,2 = 0 V P_10.8.22 H,rise H,fall Open Load and Open Feedback Diagnostics Open Load rising Thresholds VVFB1,2_OL, 1.29 Open Load reference Voltages VFBH1,2-FBL1,2 VFBH1,2_FBL – Open Load falling Thresholds VVFB1,2_OL,f 1.23 rise 1,2_OL all 1) Specified by design; not subject to production test Datasheet 43 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Protection and Diagnostic Functions Note: Datasheet Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation 44 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11 Infineon FLAT SPECTRUM Feature set 11.1 Description The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout is already done and the HW designed. 11.2 Synchronization Function The gate driver switching behavior of the TLD5501-2QV are per default 180° phase shifted between the two channels. Synchronization and Spread Spectrum modulation will be done on top of the 180° phase shift between the two channels. The TLD5501-2QV features a SYNC input pin which can be used by a µC pin to define an oscillator switching frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to the dedicated DC/DC devices in the system. Refer to Figure 25 TLD5xxx-2QV (Device #1) SYNC CH1 LOGIC GATE CONTROL LSGD1 GATE CONTROL LSGD2 SYNC +180° CH2 LOGIC e.g. 400kHz Phaseshift A SYNC1 µC SYNC SYNC2 e.g. 400kHz Phaseshift B Defined phase shift between Outputs of different devices TLD5xxx-2QV (Device #2) CH1 LOGIC Datasheet LSGD1 GATE CONTROL LSGD2 SYNC INPUT +180° CH2 LOGIC Figure 25 GATE CONTROL Synchronization Overview 45 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.3 Spread Spectrum The Spread Spectrum modulation technique significantly improves the lower frequency range of the spectrum (f < 30 MHz). By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor is important for the low frequency filter characteristic. This can be an economic benefit if there is a strong requirement for average limits. The TLD5501-2QV features a built in Spread Spectrum function which can be disabled (SWTMOD.ENSPREAD) and adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency fFM, (P_11.6.3) and (P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency fdev, (P_11.6.1) and (P_11.6.2) (SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 26 for more details. The following adjustments can be programmed when SWTMOD.ENSPREAD = HIGH: SWTMOD.FMSPREAD = LOW: 12 kHz SWTMOD.FMSPREAD = HIGH: 18 kHz SWTMOD.FDEVSPREAD = HIGH: ±10% of fSW SWTMOD.FDEVSPREAD = LOW: ±20% of fSW Note: The Spread Spectrum function can not be used when the synchronization pin is used. fSW fdev t 1 f Figure 26 Datasheet FM Spread Spectrum Overview 46 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.4 EMC optimized schematic Figure 27 below displays the Application circuit with additional external components for improved EMC behavior. CIVCC HSGD1 SOFT_START1 RSPI1 RSPI2 RSPI3 RSPI4 SPI µC SYNC signal RFREQ EN LHI VDD CSN SI SO SCLK SYNC VFB1 FBH1 FBL1 PGND1 FREQ BST2 RCOMP2 SOFT_START2 COUT11 COUT12 RM1 M2 CM1 RSWCS1 M3 RG3 D4 SGND2 L2 RG4 M4 RSWCS2 RM2 CM2 COUT21 COUT12 RFB2 COUT13 VFB2 FBH2 FBL2 PGND2 SET2 IOUTMON2 VSS COUT13 VPOW_FILT SWN2 CSoft_Start2 RFB1 CIN3 HSGD2 Channel LSGD2 SWCS2 2 CM4 CBST2 D3 CCOMP2 Output Current Monitoring CH2 RG2 IVCC_ext COMP2 Analog Dimming CH2 D2 SGND1 PWM I2 Digital dimminig CH2 L1 RVFBH1 Channel LSGD1 1 SWCS1 IOUTMON1 Output Current Monitoring CH1 Device Enable Fail Safe Activation Digital Supply (+5V) RG1 CM3 VPOW RVFBL1 SET1 M1 SWN1 CSoft_Start1 CCOMP1 LPI CIN2 CBST1 D1 COMP1 Analog Dimming CH1 VPOW_FILT BST1 PWM I1 Digital dimminig CH1 RCOMP1 D1 RVFBH2 VIN IVCC_ext RVFBL2 CIN1 IVCC Vbat AGND Figure 27 Application Drawing Including Additional Components for an Improved EMC Behavior TLD5501-2QV Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Datasheet 47 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.5 Electrical Characteristics Table 13 EC Spread Spectrum VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – ±10 – % Number Spread Spectrum Parameters Frequency Deviation fdev 1) P_11.6.1 SWTMOD.FDEV SPREAD = HIGH Frequency Deviation fdev – ±20 – % 1) P_11.6.2 SWTMOD.FDEV SPREAD = LOW Frequency Modulation fFM – 12 – kHz 1) P_11.6.3 SWTMOD.FMSP READ = LOW Frequency Modulation fFM – 18 – kHz 1) P_11.6.4 SWTMOD.FMSP READ = HIGH 1) Specified by design; not subject to production test Datasheet 48 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits. Otherwise, a TER (i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as with 8 bit SPI devices. SO MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB LSB CSN SCLK time SPI _16bit.emf Figure 28 Serial Peripheral Interface 12.1 SPI Signal Description CSN - Chip Select The system microcontroller selects the TLD5501-2QV by means of the CSN pin. Whenever the pin is in LOW state, data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CSN HIGH to LOW Transition • The requested information is transferred into the shift register. • SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI. • If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will occur. • TER Flag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of the SCLK according to the Figure 29. Datasheet 49 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) STDDIAG.TER SI OR SO 1 0 SI SPI SO S CSN SCLK S SPI_16bitTER .emf Figure 29 Combinatorial Logic for TER bit CSN LOW to HIGH Transition • Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the transmission error bit (TER) is set and the command is ignored. • Data from shift register is transferred into the addressed register. SCLK - Serial Clock This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition, otherwise the command may be not accepted. SI - Serial Input Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 12.5 for further information. SO Serial Output Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Chapter 12.5 for further information. 12.2 Daisy Chain Capability The SPI of the TLD5501-2QV provides daisy chain capability. In this configuration several devices are activated by the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see Figure 30), in order to build a chain. The end of the chain is connected to the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. Datasheet 50 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Figure 30 SO SPI SI SO SPI SCLK SI device 3 CSN SCLK MI MCSN MCLK SO SPI CSN SI CSN MO device 2 SCLK device 1 SPI_DaisyChain_1.emf Daisy Chain Configuration In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn HIGH (see Figure 31). MI MO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 MCSN MCLK SPI_DaisyChain_2.emf Figure 31 Datasheet Data Transfer in Daisy Chain Configuration 51 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12.3 Timing Diagrams t CS(lead) tCS (lag) tCS(td) tSCLK(P ) CSN 0.7VDD 0.2VDD tSCLK (H) tSCLK (L) 0.7VDD SCLK 0.2VDD tSI (s u) t SI (h) 0.7VDD SI 0.2VDD t SO(en) tSO(v ) tSO (dis) 0.7Vcc SO 0.2Vcc SPI _Timings.emf Figure 32 Datasheet Timing Diagram SPI Access 52 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12.4 Electrical Characteristics VIN = 8 V to 36 V, TJ = -40°C to +150°C, VDD= 3 V to 5.5 V, all voltages with respect to ground; (unless otherwise specified) Table 14 EC Serial Peripheral Interface (SPI) Parameter Symbol Values Min. Typ. Max. Unit Note or Number Test Condition Input Characteristics (CSN, SCLK, SI) - LOW level of pin CSN VCSN(L) 0 – 0.8 V – P_12.4.1 SCLK VSCLK(L) 0 – 0.8 V – P_12.4.2 SI VSI(L) 0 – 0.8 V – P_12.4.3 Input Characteristics (CSN, SCLK, SI) - HIGH level of pin CSN VCSN(H) 2 – VDD V – P_12.4.4 SCLK VSCLK(H) 2 – VDD V – P_12.4.5 SI VSI(H) 2 – VDD V – P_12.4.6 L-input pull-up current at CSN pin -ICSN(L) 31 63 94 μA VDD = 5 V; VCSN = 0.8 V P_12.4.7 H-input pull-up current at CSN pin -ICSN(H) 22 45 67 μA VDD = 5 V; VCSN = 2 V P_12.4.8 L-Input Pull-Down Current at Pin SCLK ISCLK(L) 6 12 18 μA VSCLK = 0.8 V; P_12.4.9 SI ISI(L) 6 12 18 μA VSI = 0.8 V P_12.4.10 SCLK ISCLK(H) 15 30 45 μA VSCLK = 2 V; P_12.4.11 SI ISI(H) 15 30 45 μA VSI = 2 V P_12.4.12 L level output voltage VSO(L) 0 – 0.4 V ISO = -2 mA P_12.4.13 H level output voltage VSO(H) VDD 0.4 V – VDD V ISO = 2 mA; VDD = 5 V P_12.4.14 Output tristate leakage current ISO(OFF) -1 – 1 μA VCSN = VDD; VSO = 0 V or VSO = VDD P_12.4.15 Enable lead time (falling CSN to rising SCLK) tCSN(lead) 200 – – ns 1) P_12.4.17 Enable lag time (falling SCLK to rising CSN) tCSN(lag) 200 – – ns 1) P_12.4.18 Transfer delay time (rising CSN to tCSN(td) falling CSN) 250 – – ns 1) P_12.4.19 Output enable time (falling CSN to tSO(en) SO valid) – – 200 ns 1) P_12.4.20 H-Input Pull-Down Current at Pin Output Characteristics (SO) Timings Datasheet CL = 20 pF at SO pin 53 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Table 14 EC Serial Peripheral Interface (SPI) (cont’d) Parameter Min. Typ. Max. Unit Note or Number Test Condition Output disable time (rising CSN to tSO(dis) SO tristate) – – 200 ns Serial clock frequency – Serial clock period Serial clock HIGH time Serial clock LOW time Symbol fSCLK tSCLK(P) tSCLK(H) tSCLK(L) Values 1) P_12.4.21 CL = 20 pF at SO pin 200 75 75 – – – – 5 – – – MHz 1) P_12.4.22 ns 1) P_12.4.24 ns 1) P_12.4.25 ns 1) P_12.4.26 P_12.4.27 Data setup time (required time SI tSI(su) to falling SCLK) 20 – – ns 1) Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1) P_12.4.28 ns 1) P_12.4.29 Output data valid time with capacitive load tSO(v) – – 100 CL = 20 pF 1) Not subject to production test, specified by design Datasheet 54 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12.5 SPI Protocol The relationship between SI and SO content during SPI communication is shown in Figure 33. The SI line represents the frame sent from the µC and the SO line is the answer provided by the TLD5501-2QV. The first SO response is the response from the previous command. SI frame A frame B frame C SO (previous response ) response to frame A response to frame B SPI_SI2SO.emf Figure 33 Relationship between SI and SO during SPI communication The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the µC. Although the biggest majority of commands and frames implemented in TLD5501-2QV can be decoded without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission to decode TLD5501-2QV response frame completely. More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows: SI write register A read register A (new command ) SO (previous response ) Standard diagnostic register A content SPI_RWseq.emf Figure 34 Register content sent back to µC There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received frame: • in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8 with a minimum of 16 bits), shown in Figure 35 • when TLD5501-2QV logic supply comes out of an Undervoltage reset condition (VDD < VDD(UV) as shown in Figure 36 or EN/INUVLO < VEN/INUVLOth ) • in case of a read or write command for a “not used” or “reserved” register (in this case TLD5501-2QV answers with Standard Diagnosis at the next SPI transmission) Datasheet 55 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) frame A (error in trans .) SI SO (new command) (previous response) Standard diag + TER SPI_SO_TER.emf Figure 35 TLD5501-2QV response after an error in transmission VDD ≥ VDD(UV) SI SO Figure 36 Datasheet frame A frame B Standard diag + TER (SO = „Z“) frame C response to frame B TLD5501-2QV response after coming out of Power-On reset at VDD 56 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12.6 SPI Registers Overview Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard diagnosis is LOW). A new command can be executed in the second frame. Table 15 SPI Command Summary1) Requested Operation Frame sent to TLD5501-2QV (SI pin) Frame received from TLD5501-2QV (SO pin) with the next command Read Standard Diagnosis 0xxxxxxxxxxxxxx1B (“xxxxxxxxxxxxB” = don’t care) 0dddddddddddddddB (Standard Diagnosis) Write 8-bit register Bank 0: 10aaaaaaccccccccB Bank 1: 11aaaaaaccccccccB where: “aaaaaaB” = register address “ccccccccB” = new register content 0dddddddddddddddB (Standard Diagnosis) Read 8-bit registers Bank 0: 00aaaaaaxxxxxxx0B Bank 1: 01aaaaaaxxxxxB where: “aaaaaaB” = register address “xxxxxxxB” = don’t care Bank 0: 10aaaaaaccccccccB Bank 1: 11aaaaaaccccccccB where: “aaaaaaB” = register address “ccccccccB” = register content 1) “a” = address bits, “c” = register content, “d” = diagnostic bit 12.6.1 Standard Diagnosis The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility routines. The bits SWRST, UVLORST, TER, CAPUV_CH1, CAPUV_CH2, and IVCCUVLO are latched and automatically cleared after a STD diagnosis reading. The bit TSD is latched and clearable only via explicit CLRLAT command. The bits STATE and TW are real time status flags. The bits EOMON, EOCAL, FAULT_CH1 and FAULT_CH2 are mirrors of internal registers. A CLRLAT command resets the diagnostic Latched Flags and Latched protections for the OUTOV_CH1,2, TSD bits, restarting the switching activity if this was halted due the previously mentioned faults. In standard operating condition (active state, no Limp Home), if no special routines have been executed and no faults have been detected, the readout of the STD should be 1000H. 15 0 14 SWRST Datasheet 13 12 11 10 9 UVLO STATE TER EO x RST MON 8 7 6 5 4 3 2 1 0 EOC CAPU CAPU IVCCU FAULT FAULT TSD TW AL V_CH V_CH VLO _CH2 _CH1 2 1 57 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Field Bits Type Description SWRST 14 r SWRST Monitor 0B , no SWRST occured 1B , there was at least one SWRST since last readout UVLORST 13 r VDD OR VEN/INUVLO Undervoltage Monitor 0B , there was no VDD OR VEN/INUVLO undervoltage since last readout 1B , there was at least one VDD undervoltage OR VEN/INUVLO undervoltage condition since last readout STATE 12:11 r Operative State Monitor 00B , (reserved) 01B , Limp Home Mode 10B , Active Mode 11B , Idle Mode TER 10 r Transmission Error 0B , Previous transmission was successful (modulo 16 + n*8 clocks received, where n = 0, 1, 2...) 1B , Previous transmission failed or first transmission after reset EOMON 9 r Mirror of EOMON_CH1,2 This bit is the mirror of EOMON_CH1 or EOMON_CH2 bits, according to the last SOMON_CH1,2 command received. EOCAL 7 r Mirror of EOCAL_CH1,2 This bit is the mirror of EOCAL_CH1 or EOCAL_CH2 bits, according to the last SOCAL_CH1,2 command received. CAPUV_CH2 6 r Undervoltage at High Side Drivers monitor bit for CH2: 0B , VBST2 - VSWN2 voltage difference is above the Gate Driver undervoltage threshold VBST2-VSWN2_UVth = no undervoltage at Gate Drivers detected 1B , VBST2 - VSWN2 voltage is below the Gate Driver undervoltage threshold VBST2-VSWN2_UVth = undervoltage at Gate Drivers detected CAPUV_CH1 5 r Undervoltage at High Side Drivers monitor bit for CH1: 0B , VBST1 - VSWN1 voltage difference is above the Gate Driver undervoltage threshold VBST1-VSWN1_UVth = no undervoltage at Gate Drivers detected 1B , VBST1 - VSWN1 voltage is below the Gate Driver undervoltage threshold VBST1-VSWN1_UVth = undervoltage at Gate Drivers detected IVCCUVLO 4 r IVCC or IVCC_EXT Undervoltage Lockout Monitor 0B , IVCC and IVCC_EXT above VIVCC_RTH,d or VIVCC_EXT_RTH,d threshold since last readout 1B , Undervoltage on IVCC or IVCC_EXT occurred since last readout FAULT_CH2 3 r Fault Diagnosis Flag of CH2 This bit is the mirror of SHRTLED_CH2, OL_CH2, OUTOV_CH2 combined in logic OR Datasheet 58 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Field Bits Type Description FAULT_CH1 2 r Fault Diagnosis Flag of CH1 This bit is the mirror of SHRTLED_CH1, OL_CH1, OUTOV_CH1 combined in logic OR TSD 1 r Over Temperature Shutdown 0B , Tj below temperature shutdown threshold 1B , Overtemperature condition detected since last readout TW 0 r Over Temperature Warning 0B , Tj below temperature warning threshold 1B , Tj exceeds temperature warning threshold Datasheet 59 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) 12.6.2 Register structure Table 18 describes in detail the available registers with their bit-fields function, size and position Table 16 and Table 17 show register addresses and summarize bit-field position inside each register Table 16 Register Bank 0 Bit 15 1 4 Name W R ADDR /R B 1 12 11 10 9 8 3 7 6 5 4 3 2 1 0 Data LEDCURRA W/ 0 DIM_CH1 R 0 0 0 0 0 0 ADIMVAL_CH1 LEDCURRC W/ 0 AL_CH1 R 0 0 0 0 1 1 x DAC_OF SOCAL EOCAL CALIBVAL_CH1 F_CH1 _CH1 _CH1 SWTMOD W/ 0 R 0 0 0 1 0 1 x x x x x ENSP FMSP FDEVS READ READ PREAD DVCCTRL W/ 0 R 0 0 0 1 1 0 x x x x x CLRLA SWRS IDLE T T MFSSETUP W/ 0 1_CH1 R 0 0 1 0 0 1 x x x x LEDCHAIN_CH1 CURRMON W/ 0 _CH1 R 0 0 1 1 0 0 x x x x SOMON EOMO LEDCURR_CH1 _CH1 N_CH 1 FAULTS_C H1 W/ 0 R 0 0 1 1 1 1 OUT x OC_ CH1 x OUTOV x LAT_C H1 OUTO OL_C V_CH H1 1 SHRTL ED_CH 1 LOOPCTRL W/ 0 _CH1 R 0 1 0 0 0 1 PW x M_1 x x x ENCAL _CH1 Table 17 Register Bank 1 Bit 15 1 4 Name W R ADDR /R B 1 12 11 10 9 8 3 7 6 5 x 4 3 x 2 1 0 Data LEDCURRA W/ 1 DIM_CH2 R 0 0 0 0 0 1 ADIMVAL_CH2 LEDCURRC W/ 1 AL_CH2 R 0 0 0 0 1 0 x DAC_O SOCAL EOCAL CALIBVAL_CH2 FF_CH2 _CH2 _CH2 MFSSETUP W/ 1 1_CH2 R 0 0 1 0 0 0 x x x x LEDCHAIN_CH2 CURRMON W/ 1 _CH2 R 0 0 1 1 0 1 x x x x SOMON EOMO LEDCURR_CH2 _CH2 N_CH 2 Datasheet 60 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Table 17 Register Bank 1 (cont’d) Bit 15 1 4 1 12 11 10 9 8 3 FAULTS_C H2 W/ 1 R 0 0 1 1 1 0 OUT x OC_ CH2 x OUTOV x LAT_C H2 OUTO OL_C V_CH H2 2 SHRTL ED_CH 2 LOOPCTRL W/ 1 _CH2 R 0 1 0 0 0 0 PWM x _2 x x x ENCAL _CH2 7 6 5 4 3 x 2 1 x 0 A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis Frame is send out. Table 18 Register description Register name Field Bits Type Purpose LEDCURRADIM _CH1,2 ADIMVAL_CH1, 2 7:0 r/w LED Current Configuration Register 00000000B, analog dimming @ 0% of LED current fixed via RFB1,2 11110000B, (default) analog dimming @ 100% of LED current fixed via RFB1,2 LEDCURRCAL_ CH1,2 CALIBVAL_CH1 ,2 3:0 r/w LED Current Accuracy Trimming Configuration Register LED current calibration value definition, the first bit is the calibration sign: 0000B, (default) Initial state in the middle of the range 0111B, maximum calibration value positive 1111B, maximum calibration value negative EOCAL_CH1,2 4 r End of calibration routine signalling bit: 0B , (default) calibration routine not completed, not successfully performed or never run. 1B , calibration successfully performed (is reset to 0B when SOCAL_CH1,2 is set to 1B) SOCAL_CH1,2 5 r/w Start of calibration routine signalling bit: 0B , (default) no calibration routine started 1B , calibration routine start (autoclear) DAC_OFF_CH1, 2 6 r/w Switch OFF internal analog dimming DAC bit: 0B , (default) internal DAC active 1B , internal DAC inactive and analog dimming error amplifier reference mapped to SET1,2 pin Datasheet 61 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Table 18 Register description (cont’d) Register name Field Bits Type Purpose SWTMOD FDEVSPREAD 0 r/w Switching Mode Configuration Register Deviation Frequency fDEV definition: 0B , (default) ±20% of fSW 1B , ±10% of fSW FMSPREAD 1 r/w Frequency Modulation Frequency fFM definition: 0B , (default) 12 kHz 1B , 18 kHz ENSPREAD 2 r/w Enable Spread Spectrum feature: 0B , Spread Spectrum modulation disabled 1B , (default) Spread Spectrum modulation enabled IDLE 0 r/w Device Control Register IDLE mode configuration bit: 0B , ACTIVE mode (default) 1B , IDLE mode SWRST 1 r/w Software reset bit: 0B , (default) normal operation 1B , execute reset command CLRLAT 2 r/w Clear Latch bit: 0B , (default) normal operation 1B , execute CLRLAT command MFSSETUP1_C H1,2 LEDCHAIN_CH1 ,2 3:0 r/w Short Circuit configuration Register Short circuit threshold and MFS ratio bits: change the VVFB1,2_S2G threshold 0001B, smallest Value 1 Step 0010B, (default) 2 Steps 1000B, 8 Steps 1111B, 15 Steps 0000B, largest Value 16 Steps CURRMON_CH1 ,2 LEDCURR_CH1, 2 1:0 r Current Monitor Register Status of the LED Current bits: 00B , (default) LED current between Target and +25% 01B , LED current above +25% of Target 10B , LED current between Target and -25% 11B , LED current below -25% of Target EOMON_CH1,2 2 r End of LED/Input Current Monitoring bits: 0B , (default) Current monitoring routine not completed, not successfully performed or never run. 1B , Current Monitor routine successfully performed (is reset to 0B when SOMON_CH1,2 is set to 1B) SOMON_CH1,2 3 r/w Start of LED/Input Current Monitoring bits: 0B , (default) Current monitor routine not started 1B , Start of the current monitor routine DVCCTRL Datasheet 62 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Serial Peripheral Interface (SPI) Table 18 Register description (cont’d) Register name Field Bits Type Purpose FAULTS_CH1, 2 SHRTLED_CH1, 2 0 r Detailed Fault and Diagnosis Registers Shorted Load Diagnosis Bit: 0B , Short circuit condition not detected since last readout 1B , Short circuit condition detected since last readout This bit is latched and automatically cleared after a FAULTS_CH1,2 register reading OL_CH1,2 1 r Open Load in ON state Diagnosis Bit: 0B , Open load condition not detected since last readout 1B , Open load condition detected since last readout This bit is latched and automatically cleared after a FAULTS_CH1,2 register reading OUTOV_CH1,2 2 r Output overvoltage Monitor Bit: 0B , Output overvoltage not detected since last readout 1B , Output overvoltage detected since last readout This bit is latched and automatically cleared after a FAULTS_CH1,2 register reading (default condition if OUTOVLAT_CH1,2 is not set). See Chapter 10.2.2 for further details. OUTOVLAT_CH1 ,2 4 r/w Output latch after overvoltage error enable Bit: 0B , (default) gate driver outputs are autorestarting after an overvoltage event 1B , gate drivers are latched low (output Mos are High Impedance) and bit OUTOV_CH1,2 is latched after an overvoltage event until a CLRLAT command OUTOC_CH1,2 7 r Output overcurrent Monitor Bit: 0B , Output overcurrent not detected since last readout 1B , Output overcurrent detected since last readout This bit is latched and automatically cleared after a FAULTS_CH1,2 register reading ENCAL_CH1,2 0 r/w Loop Control Register Enable automatic output current calibration Bits of CH1,2: 0B , (default) DAC of CH1,2 takes CALIBVAL_CH1,2 from SPI registers 1B , DAC of CH1,2 takes CALIBVAL_CH1,2 from last completed automatic calibration procedure; SOCAL_CH1,2 bits can be set. PWM_1,2 7 r/w Bits to enable/disable the gate drivers of the main switches (gate driver resulting status is the OR function with the PWMI1,2 pins value): 0B , (default) disable 1B , enable LOOPCTRL_CH 1,2 Datasheet 63 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Application Information 13 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. CIVCC CIN1 CIN2 CBST1 COMP1 SET1 SPI µC SYNC signal RFREQ M2 RSWCS1 SGND1 EN LHI VDD CSN SI SO SCLK SYNC VFB1 FBH1 FBL1 PGND1 FREQ BST2 COUT11 COUT12 RFB1 COUT13 RVFBH1 Channel LSGD1 1 SWCS1 IOUTMON1 Output Current Monitoring CH1 Device Enable Fail Safe Activation Digital Supply (+5V) L1 SWN1 CSoft_Start1 Analog Dimming CH1 M1 HSGD1 SOFT_START1 CCOMP1 VPOW BST1 PWMI1 Digital dimminig CH1 RCOMP1 D1 RVFBL1 VIN IVCC_ext IVCC Vbat VPOW IVCC_ext CIN3 D2 CBST2 SWN2 COMP2 RCOMP2 SOFT_START2 Channel LSGD2 SWCS2 2 CSoft_Start2 SGND2 CCOMP2 IOUTMON2 Output Current Monitoring CH2 L2 COUT21 COUT22 M4 RSWCS2 RFB2 COUT23 VFB2 FBH2 FBL2 PGND2 SET2 Analog Dimming CH2 M3 HSGD2 RVFBH2 Digital dimminig CH2 RVFBL2 PWMI2 AGND VSS Figure 37 Application Drawing - TLD5501-2QV as BUCK current Regulator, Separate Channels Table 19 BOM - TLD5501-2QV as BUCK current regulator Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- BAT46WJ Diode CIN2, CIN3 4.7 µF, 100 V TDK X7R Capacitor CCOMP1, CCOMP2 22n F, 16 V TDK X7R Capacitor CSOFT_START1 , CSOFT_START2 22 nF, 16 V TDK X7R Capacitor COUT11, COUT21, COUT12, COUT22 4.7 µF, 60 V TDK X7R Capacitor CIN1, COUT13 , COUT23 100 nF, 60 V TDK X7R Capacitor COUT23 100 µF, 80 V TDK Tantalum Capacitor CIVCC 10 µF, 16 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5501-2QV IC L1 , L2 10 µH Coilcraft XAL1010-103MEC Inductor RFB1, RFB2 0.50 Ω, 1% Panasonic -- Resistor Datasheet 64 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Application Information Table 19 BOM - TLD5501-2QV as BUCK current regulator Reference Designator Value Manufacturer Part Number Type RVFBL1 , RVFBL2 1.5 kΩ, 1% Panasonic -- Resistor RVFBH1, RVFBH2 56 kΩ, 1% Panasonic -- Resistor RCOMP1,RCOMP2 0 Ω, 5% Panasonic -- Resistor RFREQ 37.4 kΩ, 1% Panasonic -- Resistor RSWCS1 , RSWCS2 0.005 Ω, 1% Panasonic ERJB1CFR05U Resistor M1 , M2, M3 , M4 Dual MOSFET: 100 V / 26 mΩ N-ch Infineon IPG20N06S4L-26 Transistor Vbat CIVCC VIN IVCC_ext D1 IVCC CIN1 VPOW CIN2 BST1 PWMI1 CBST1 μC SYNC signal RVFBH RSWCS1 VOUT RFB2 VFB1 FBH1 FBL1 PGND1 EN LHI VDD CSN SI SO SCLK SYNC IVCC_ext VPOW CIN3 D2 FREQ RFREQ M2 RFF SGND1 COUT13 D3 RFB3 SPI COUT11 COUT12 Channel LSGD1 1 SWCS1 IOUTMON1 Device Enable Fail Safe Activation Digital Supply (+5V) L1 SWN1 RVFBL SET1 Analog Dimming CH1 M1 HSGD1 SOFT_START1 RFB1 COMP1 CFF BST2 CBST2 PWMI2 Output Activation M3 HSGD2 L2 SWN2 COUT21 COUT22 COMP2 RCOMP SOFT_START2 Channel 2 RSWCS2 CSoft_Start SGND2 CCOMP SET2 Analog Dimming CH2 M4 LSGD2 SWCS2 IOUTMON2 VSS VFB2 FBH2 FBL2 PGND2 AGND Figure 38 Application Drawing - TLD5501-2QV as BUCK voltage regulator parallel channels Table 20 BOM - TLD5501-2QV as BUCK voltage regulator with parallel channels Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- -- Diode CIN2 , CIN3 4.7 µF, 50 V TDK X7R Capacitor CCOMP 39 nF, 16 V TDK X7R Capacitor CSOFT_START 47 nF, 16 V TDK X7R Capacitor CFF 68nF, 50V TDK X7R Capacitor COUT11, COUT21, COUT12, COUT22 4.7 µF, 60 V TDK X7R Capacitor Datasheet 65 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Application Information Table 20 BOM - TLD5501-2QV as BUCK voltage regulator with parallel channels Reference Designator Value Manufacturer Part Number Type COUT13 100 µF, 80 V -- Electrolytic Capacitor CIVCC 10 µF, 16 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5501-2QV IC LOUT1 , LOUT2 10 µH Coilcraft XAL1010-103MEC Inductor RFB1 , RFB2 , RFB3 0, 150Ω, 48kΩ 1% Panasonic -- Resistor RVFBL , RVFBH 1.5 kΩ, 56 kΩ, 1% Panasonic -- Resistor RCOMP 1 kΩ Panasonic -- Resistor RFF 470Ω 1% Panasonic -- Resistor RFREQ 37.4 kΩ, 1% Panasonic -- Resistor RSWCS1 , RSWCS2 0.005 Ω, 1% Panasonic ERJB1CFR05U Resistor M1 , M2 , M3 , M4 Dual MOSFET: 100 V / 14 mΩ N-ch Infineon IPG20N06S4L-14 Transistor Datasheet 66 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Application Information 13.1 • Further Application Information For further information you may contact http://www.infineon.com/ Datasheet 67 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Package Outlines Package Outlines 6.8 11 x 0.5 = 5.5 0.1±0.03 B +0.03 1) 3 1 0. 0.4 x 45° Index Marking C ± 26 36 25 48 13 1 12 (0 (0.2) 2) 37 .35 ) 0.05 MAX. 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 39 0.5 0. 24 0.15 ±0.05 0.1 ±0.05 SEATING PLANE 7 ±0.1 48x 0.08 6.8 5 0 0. 0.5 ±0.07 A (6) 7 ±0.1 0.9 MAX. (0.65) (5.2) 14 0.23 ±0.05 (5.2) Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 PG-VQFN-48 (with LTI) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Datasheet 68 Dimensions in mm Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Revision History 15 Revision History Revision Date Changes Rev. 2.00 2021-03-26 Editorial changes and typos Rev. 2.00 2021-03-26 Change package name and updated product validation AEC Q100 Rev. 2.00 2021-03-26 Update Figure 2 Rev. 2.00 2021-03-26 Update footnotes of Table 3 Rev. 2.00 2021-03-26 P_4.2.1, P_4.3.2, P_6.4.43, P_6,4,47, P_6.4.64, P_10.8.30, P_10.8.31, P_10.8.21: added notes Rev. 2.00 2021-03-26 P_5.3.7 min: 1.64 → 1.6, max: 1.86 → 1.9 Rev. 2.00 2021-03-26 Update Chapter 6.1 Rev. 2.00 2021-03-26 Update Figure 7 Rev. 2.00 2021-03-26 Improved description of Adjustable Soft Start Ramp Chapter 6.2 Rev. 2.00 2021-03-26 Update Figure 8 Rev. 2.00 2021-03-26 Improved description of Programming Output Voltage (Constant Voltage Regulation Chapter 6.5) Rev. 2.00 2021-03-26 Added P_6.6.1 Rev. 2.00 2021-03-26 Update Chapter 8 Rev. 2.00 2021-03-26 Update Chapter 8.1 Rev. 2.00 2021-03-26 Improved description of Output current Monitoring Chapter 10.3 Rev. 2.00 2021-03-26 Added note in Spread Spectrum description Chapter 11.3 Rev. 2.00 2021-03-26 Removed introduction table in Chapter 12.6 Rev. 2.00 2021-03-26 Added Table 15 Rev. 2.00 2021-03-26 Update Chapter 12.6.1 Rev. 2.00 2021-03-26 Update Table 16 and Table 17 Rev. 2.00 2021-03-26 Update BOM Table 19 and Table 20 Rev. 2.00 2021-03-26 Update Figure 38 Rev. 1.00 2017-07-11 Initial Datasheet Datasheet 69 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface Table of Content 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 4.1 4.2 4.3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 5.1 5.2 5.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 6.1 6.2 6.3 6.4 6.5 6.6 Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flexible current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 7.1 7.2 Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 8.1 8.2 8.3 Analog Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 9.1 9.2 Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.3 10.4 10.5 Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output Overvoltage, Overcurrent, Open Load, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . 38 Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Overcurrent on Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 11.1 11.2 11.3 11.4 Infineon FLAT SPECTRUM Feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Datasheet 70 Rev. 2.00 2021-03-26 TLD5501-2QV Dual SYNC Buck Controller with SPI Interface 11.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 12.1 12.2 12.3 12.4 12.5 12.6 12.6.1 12.6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13 13.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table of Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Datasheet 71 Rev. 2.00 2021-03-26 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-03-26 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference TLD5501-2QV IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.