TLD55421QVXUMA1

TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Infineon® LITIX™ Power Flex Package PG-VQFN-48 PG-TQFP-48 Marking TLD55421QV TLD55421QU Sales Name TLD5542-1QV 1 TLD5542-1QU Overview Features • Single inductor high power Buck-Boost controller • Wide LED forward voltage range (2 V up to 55 V) • Wide VIN range (IC 4.5 V to 40 V, power 4.5 V to 55 V) • Switching frequency range from 200 kHz to 700 kHz • SPI for diagnostics and control • Maximum efficiency in every condition (up to 96%) • Constant current (LED) and constant voltage regulation • Drives multiple loads with a single IC thanks to the Fast Output Discharge operation • Limp Home function (fail safe mode) • EMC optimized device: features an Auto Spread Spectrum • LED and input current sense with dedicated monitor outputs • Advanced protection features for device and load • Enhanced dimming features: Analog and PWM dimming • LED current accuracy +/- 3% • Available in a small thermally enhanced PG-VQFN-48 or PG-TQFP-48 package • Automotive AEC Qualified VIN CIN2 CIN1 IVCC VFB_VIN HSGD1 CCOMP RPU2 RPU1 RFREQ I/O I/O I/O EOMFS LEDCUR VDD VDD CSN SI SO SCLK RSPI2 RSPI3 RSPI4 CFILT1 Datasheet FILT COUT1 RFB COUT3 SWCS FREQ PWMI RSPI1 Figure 1 SOFT_START RSWCS CSOFT_START VDD M3 LSGD1 COMP M4 LOUT M2 RCOMP GND M1 SWN1 I/O SPI SPI CBST1 CBST2 RVFBH EN/INUVLO Micro controller COUT2 BST1 BST2 VDD D2 D1 RVFBL IIN1 VDD CIVCC IVCC_ext VIN IIN2 SGND PGND1 PGND2 LSGD2 SWN2 HSGD2 VFB FBH High Power LED Load FBL VSS IOUTMON AGND CFILT2 Application Drawing - TLD5542-1 as current regulator www.infineon.com 1 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Overview Description The TLD5542-1 is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features and SPI interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and minimum number of external components. The TLD5542-1 offers both analog and digital (PWM) dimming.The switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external clock source. A built in programable Spread Spectrum switching frequency modulation and the forced continuous current regulation mode improve the overall EMC behavior. Furthermore the current mode regulation scheme provides a stable regulation loop maintained by small external compensation components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up. The TLD5542-1 is suitable for use in the harsh automotive environment. Table 1 Product Summary Power Stage input voltage range VPOW 4.5 V … 55 V Device Input supply voltage range VVIN 4.5 V … 40 V Maximum output voltage (depending by the application conditions) VOUT(max) 55 V as LED Driver Boost Mode 50 V as LED Driver Buck Mode 50 V as Voltage regulator Switching Frequency range fSW 200 kHz... 700 kHz Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Up) RDS(ON_PU) 2.3 Ω Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Down) RDS(ON_PD) 1.2 Ω SPI clock frequency fSCLK(MAX) 5 MHz Protective Functions • Over load protection of external MOSFETs • Shorted load, output overvoltage protection • Input undervoltage protection • Thermal shutdown of device with autorestart behavior • Electrostatic discharge protection (ESD) Diagnostic Functions • Latched diagnostic information via SPI • Device Overtemperature shutdown and Temperature Prewarning • Smart monitoring and advanced functions provide ILED and IIN information Limp Home Function • Limp Home activation via LHI pin Applications • Especially designed for driving multiple high power LED functions (I.E. Low Beam, High Beam, DRL) • Automotive Exterior Lighting: full LED headlamp assemblies • General purpose DC/DC voltage regulator Datasheet 2 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Block Diagram 2 Block Diagram IVCC Internal Supply LDO VIN SYNC Auto-Spread Spectrum Generator VI N Voltage Protection + Enable BUCK LO GIC LSGD1 PWM Generator Diagnosis Overvoltage + Short to GND Limp Home Mode PGND2 BOOST LOGIC Analog Dimming Pin Fast Output Discharge Operation Mode SWN2 Output current accuracy calibration HSGD2 BST2 Switch Current Error Amplifier VDD CSN 8 Bit DAC Analog Dimming SPI SCLK PGND1 LSGD2 Digital Dimming PWMI FILT IVCC_EXT Soft Start LHI EOMFS SWN1 IVCC_EXT Thermal Protection + Prewarning SOFT_START BST1 HSGD1 Slope Comp. SET IVCC_EXT GATE DRIVER Oscillator FREQ EN/INUVLO Power On Reset SWCS SGND VFB SI Figure 2 Datasheet AGND IINMON VSS IIN1 IIN2 LED Current Monitor LEDCUR Input Current Monitor Input/diag nosis regi ster IOUTMON SO Feedback Error Amplifier + Short to GND COMP FBH FBL DIM_HALF VFB_VIN Block Diagram - TLD5542-1 3 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Pin Configuration Pin Configuration 3.1 Pin Assignment 36 35 34 33 32 31 30 29 28 27 26 25 DIM_HALF FREQ SYNC LEDCUR EOMFS VDD SI SCLK CSN SO VSS TEST2 3 37 38 39 40 41 42 43 44 45 46 47 48 EP 24 23 22 21 20 19 18 17 16 15 14 13 PWMI FILT SET VFB_VIN VFB COMP SGND SWCS IOUTMON n.c. FBL FBH n.c. HSGD1 BST1 SWN1 PGND1 LSGD1 LSGD2 PGND2 SWN2 BST2 HSGD2 n.c. 1 2 3 4 5 6 7 8 9 10 11 12 LHI SOFT_START IINMON AGND EN/INUVLO IIN1 IIN2 VIN n.c. IVCC IVCC_EXT n.c. Figure 3 Datasheet Pin Configuration - TLD5542-1 4 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Pin Configuration 3.2 Pin Definitions and Functions Table 2 Pin Definitions and Functions Pin Symbol I/O 1) Function Power Supply n.c. 1, 12, 15, 45, 48 - Not connected, tie to AGND on the Layout; 44 VIN - Power Supply Voltage; Supply for internal biasing. 31 VDD - Digital GPIO Supply Voltage; Connect to reverse voltage protected 5 V or 3.3 V supply. 47 IVCC_EXT I PD External LDO input; Input to alternatively supply internal Gate Drivers via an external LDO. Connect to IVCC pin to use internal LDO to supply gate drivers. Must not be left open. 5, 8 PGND1, 2 - Power Ground; Ground for power potential. Connect externally close to the chip. 26 VSS - Digital GPIO Ground; Ground for GPIO pins. 40 AGND - Analog Ground; Ground Reference - EP - Exposed Pad; Connect to external heatspreading Cu area (e.g. inner GND layer of multilayer PCB with thermal vias). Gate Driver Stages 2 HSGD1 O Highside Gate Driver Output 1; Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN1. Connect to gate of external switching MOSFET. 11 HSGD2 O Highside Gate Driver Output 2; Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN2. Connect to gate of external switching MOSFET. 6 LSGD1 O Lowside Gate Driver Output 1; Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET. 7 LSGD2 O Lowside Gate Driver Output 2; Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET. 4 SWN1 IO Switch Node 1; SWN1 pin swings from a diode voltage drop below ground up to VIN. 9 SWN2 IO Switch Node 2; SWN2 pin swings from ground up to a diode voltage drop above VOUT. Datasheet 5 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Pin Configuration Table 2 Pin Definitions and Functions Pin Symbol I/O 46 IVCC O 1) Function Internal LDO output; Used for internal biasing and gate driver supply. Bypass with external capacitor close to the pin. Pin must not be left open. Inputs and Outputs 37 LHI I 23 FILT - MFS Filter; Connect with a 220pF capacitor to GND to filter MFS reference Voltage. 25 TEST2 - Test Pin; Used for Infineon end of line test, connect to GND in application. 41 EN/INUVLO I 35 FREQ I 34 SYNC I PD Synchronization Input; Apply external clock signal for synchronization. 24 PWMI I PD Control Input; Digital input 5 V or 3.3 V. 13 FBH I Output current Feedback Positive; Non inverting Input (+). 14 FBL I Output current Feedback Negative; Inverting Input (-). 3 BST1 IO Bootstrap capacitor; Used for internal biasing and to drive the Highside Switch HSGD1. Bypass to SWN1 with external capacitor close to the pin. Pin must not be left open. 10 BST2 IO Bootstrap capacitor; Used for internal biasing and to drive the Highside Switch HSGD2. Bypass to SWN2 with external capacitor close to the pin. Pin must not be left open. 17 SWCS I Current Sense Input; Inductor current measurement - Non Inverting Input (+). 18 SGND I Current Sense Ground; Inductor current sense - Inverting Input (-). Route as Differential net with SWCS on the Layout. 42 IIN1 I Input Current Monitor Positive; Non Inverting Input (+), connect to VIN if input current monitor is not needed. 43 IIN2 I Input Current Monitor Negative; Inverting Input (-), connect to VIN if input current monitor is not needed. 19 COMP O Compensation Network Pin; Connect R and C network to pin for stability phase margin adjustment. Datasheet PD Limp Home Input Pin; Used to enter in Limp Home state during Fail Safe condition. PD Enable/Input Under Voltage Lock Out; Used to put the device in a low current consumption mode, with additional capability to fix an undervoltage threshold via external components. Pin must not be left open. Frequency Select Input; Connect external resistor to GND to set frequency. 6 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Pin Configuration Table 2 Pin Definitions and Functions 1) Pin Symbol I/O 38 SOFT_START O Softstart configuration Pin; Connect a capacitor CSOFT_START to GND to fix a soft start ramp default time. 21 VFB_VIN I Input Voltage Feedback for analog dimming compensation; Connect with a Resistor divider to Vin. If not used , short to IVCC 36 DIM_HALF I Dual Range Output Current; Double the analog dimming compensation when High. 20 VFB I Voltage Loop Feedback Pin; VFB is intended to set output overvoltage protection and F.D. output voltage sensing. 22 SET I Analog current sense adjustment Pin; 39 IINMON O Input current monitor output; Monitor pin that produces a voltage proportional to VIN1-IN2. Typical IINMON will be equal 1 V when VIIN1-VIIN2 = 50 mV. 16 IOUTMON O Output current monitor output; Monitor pin that produces a voltage proportional to VFBH-FBL plus an offset. Connect with a bypass capacitor to ground 33 LEDCUR O LED current Flag; An open drain output used to detect the presence of load current on MFS topologies 32 EOMFS O End of MFS routine Flag; An open drain output which is pulled to LOW when MFS routine is ongoing, released to high when complete. 30 SI I PD Serial data in; Digital input 5 V or 3.3 V. 29 SCLK I PD Serial clock; Digital input 5 V or 3.3 V. 28 CSN I PU SPI chip select; Digital input 5 V or 3.3 V. Active LOW. 27 SO O Serial data out; Digital output, referenced to VDD. Function SPI 1) O: Output, I: Input, PD: pull-down circuit integrated, PU: pull-up circuit integrated Datasheet 7 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 3 Absolute Maximum Ratings1) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply Voltages VIN Supply Input VVIN -0.3 – 60 V – P_4.1.1 VDD Digital supply voltage VVDD -0.3 – 6 V – P_4.1.2 IVCC Internal Linear Voltage Regulator Output voltage VIVCC -0.3 – 6 V – P_4.1.3 -0.3 – 6 V – P_4.1.4 -0.3 – 5.5 V – P_4.1.54 -0.3 – 5.5 V 2) P_4.1.55 IVCC_EXT VIVCC_EXT External Linear Voltage Regulator Input voltage Gate Driver Stages LSGD1,2 - PGND1,2 Lowside Gatedriver voltage VLSGD1,2- HSGD1,2 - SWN1,2 Highside Gatedriver voltage VHSGD1,2- SWN1, SWN2 switching node voltage VSWN1, 2 -1 – 60 V – P_4.1.6 (BST1-SWN1), (BST2-SWN2) Boostrap voltage VBST1,2- -0.3 – 6 V 2) P_4.1.7 BST1, BST2 Boostrap voltage related to GND VBST1, 2 -0.3 – 65 V – P_4.1.8 SWCS Switch Current Sense Input voltage VSWCS -0.3 – 0.3 V – P_4.1.9 SGND Switch Current Sense GND voltage VSGND -0.3 – 0.3 V – P_4.1.10 SWCS-SGND Switch Current Sense differential voltage VSWCS- -0.5 – 0.5 V – P_4.1.11 PGND1,2 Power GND voltage VPGND1,2 -0.3 – 0.3 V – P_4.1.28 VIIN1, 2 -0.3 – 60 V – P_4.1.12 PGND1,2 SWN1,2 SWN1,2 SGND High voltage Pins IIN1, IIN2 Input Current monitor voltage Datasheet 8 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface General Product Characteristics Table 3 Absolute Maximum Ratings1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number IIN1-IIN2 Input Current monitor differential voltage VIIN1-IIN2 -0.5 – 0.5 V 2) P_4.1.13 FBH, FBL Feedback Error Amplifier voltage VFBH, FBL -0.3 – 60 V – P_4.1.14 FBH-FBL Feedback Error Amplifier differential voltage VFBH-FBL -0.5 – 0.5 V 2) P_4.1.15 EN/INUVLO Device enable/input undervoltage lockout VEN/INUVLO -0.3 – 60 V – P_4.1.16 PWMI Digital Input voltage VPWMI -0.3 – 5.5 V – P_4.1.17 CSN Voltage at Chip Select pin VCSN -0.3 – 5.5 V – P_4.1.18 SCLK Voltage at Serial Clock pin VSCLK -0.3 – 5.5 V – P_4.1.19 SI Voltage at Serial Input pin VSI -0.3 – 5.5 V – P_4.1.20 SO Voltage at Serial Output pin VSO -0.3 – 5.5 V – P_4.1.21 SYNC Synchronization Input voltage VSYNC -0.3 – 5.5 V – P_4.1.22 LHI Limp Home Input Voltage VLHI -0.3 – 5.5 V – P_4.1.58 VFB, VFB_VIN VVFB, Output and Input Voltage feedback pins VVFB_VIN -0.3 – 5.5 V – P_4.1.25 DIM_HALF Dual Range Output Current VDIM_HALF -0.3 – 5.5 V – P_4.1.26 FILT MFS Filter pin voltage VFILT -0.3 – 3 V – P_4.1.62 EOMFS, LEDCUR Flags output voltage VFLAGS -0.3 – 5.5 V – P_4.1.61 SET Analog dimming Input voltage VSET -0.3 – 5.5 V – P_4.1.29 COMP Compensation Input voltage VCOMP -0.3 – 3.6 V – P_4.1.30 Digital (I/O) Pins Analog Pins Datasheet 9 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface General Product Characteristics Table 3 Absolute Maximum Ratings1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Min. SOFT_START Softstart Voltage VSOFT_STAR -0.3 Number Typ. Max. Unit Note or Test Condition – 3.6 V – P_4.1.31 T FREQ Voltage at frequency selection pin VFREQ -0.3 – 3.6 V – P_4.1.32 IINMON Voltage at input monitor pin VIINMON -0.3 – 3.6 V – P_4.1.33 IOUTMON Voltage at output monitor pin VIOUTMON -0.3 – 5.5 V – P_4.1.34 Junction Temperature Tj -40 – 150 °C – P_4.1.35 Storage Temperature Tstg -55 – 150 °C – P_4.1.36 VESD,HBM -2 – 2 kV HBM3) P_4.1.37 4) Temperatures ESD Susceptibility ESD Resistivity of all Pins ESD Resistivity to GND VESD,CDM -500 – 500 V CDM P_4.1.38 ESD Resistivity of corner Pins to GND VESD,CDM_c -750 – 750 V CDM4) P_4.1.39 orner 1) 2) 3) 4) Not subject to production test, specified by design. Does not refer to GND ESD susceptibility, Human Body Model “HBM” according to AEC Q100-002 ESD susceptibility, Charged Device Model “CDM” AECQ100-011 Rev. D Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Table 4 Functional Range Parameter Symbo l Min. Values Typ. Max. Unit Note or Test Condition – V 1) Number Device Extended Supply Voltage Range VVIN 4.5 Device Nominal Supply Voltage Range VVIN 8 – 36 V – P_4.2.2 Power Stage Voltage Range VPOW 4.5 – 55 V 1) P_4.2.5 Datasheet 40 P_4.2.1 (parameter deviations possible) 10 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface General Product Characteristics Table 4 Functional Range (cont’d) Parameter Symbo l Min. Values Number Typ. Max. Unit Note or Test Condition Digital Supply Voltage VDD 3 – 5.5 V – P_4.2.3 Junction Temperature Tj -40 – 150 °C – P_4.2.4 1) Not subject to production test, specified by design. Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 5 Parameter Junction to Case Junction to Ambient Symbol RthJC RthJA Values Min. Typ. Max. – 0.9 – – 25 – Unit Note or Test Condition Number K/W 1) 2) P_4.3.1 K/W 3) P_4.3.2 2s2p 1) Not subject to production test, specified by design. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed to ambient temperature). Ta = 25°C; The IC is dissipating 1 W. 3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has 2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and 25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W. Datasheet 11 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply 5 Power Supply The TLD5542-1 is supplied by the following pins: • VIN (main supply voltage) • VDD (digital supply voltage) • IVCC_EXT (supply for internal gate driver stages) The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and digital blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption may be observed at the VDD pin. The SPI and IO interfaces are supplied by the VDD pin. IVCC_EXT is the supply for the low side driver stages, which is also used to charge, by means of external Schottky diodes, the bootstrap capacitors. These capacitors provide power to the high side driver stages. If no external voltage is available, IVCC_EXT pin must be shorted to IVCC, which is the output of an internal 5 V LDO. The supply pins VIN, VDD and IVCC_EXT have undervoltage detections. Undervoltage on VDD prevents the activation of the gate driver stages and any SPI communication (the SPI registers are reset). Undervoltage on IVCC_EXT or IVCC pins forces a deactivation of the driver stages, thus stopping the switching activity, but has no effect on the SPI register settings. Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a resistor divider from VIN to GND (refer to Chapter 10.3). If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator, stop switching, stop communications and reset all the registers. Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and IVCC/IVCC_EXT. VIN VREG (5V) R1 EN/INUVLO IVCC Internal pre-regulated voltage Supply Undervoltage detection R2 IVCC_EXT VREG digital VREG analog LS - Drivers PGNDx Undervoltage detection BSTx Bandgap Reference VDD Figure 4 Datasheet SPI & I/O Register Banks HS - Drivers LOGIC SWNx Power Supply Concept Drawing 12 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply Usage of EN/INUVLO pin in different applications The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption mode. An undervoltage threshold is fixed by placing an external resistor divider (A) in order to avoid low voltage operating conditions. This pin can be driven by a µC-port as shown in (B) (C). A Vin VIN Datasheet D Vin VIN VIN R1 EN/INUVLO Figure 5 Vin VIN R1 R2 C B Vin GND µC Port EN/INUVLO µC Port R2 GND EN/INUVLO EN/INUVLO GND GND Usage of EN/INUVLO pin in different applications 13 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply 5.1 Different Power States TLD5542-1 has the following power states: • SLEEP state • IDLE state • LIMP HOME state • ACTIVE state The transition between the power states is determined according to these variables after a filter time of max. 3 clock cycles: • VIN level • EN/INUVLO level • IVCC level • IVCC_EXT level • VDD level • LHI level • DVCCTRL.IDLE bit state The state diagram including the possible transitions is shown in Figure 6. The Power-up condition is entered when the supply voltage VVIN exceed its minimum supply voltage threshold VVIN(ON). SLEEP When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset, independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption is low. Refer to parameters: IVDD(SLEEP), and IVIN(SLEEP). The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE. IDLE In IDLE state, the current consumption of the device can reach the limits given by parameter IVDD (P_5.3.4). The internal voltage regulator and IVCC linear regulator are working. Not all diagnosis functions are available (refer to Chapter 10 for additional informations). In this state there is no switching activity, independently from the supply voltages VIN, VDD, IVCC and IVCC_EXT. When VDD is available, the SPI registers are working and SPI communication is possible. Limp Home The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to maintain a defined current/voltage level on the output via a backup control circuitry. The backup control circuitry turns on required loads during a malfunction of the µC. For detailed info, refer to Chapter 8. When Limp Home state is entered, SPI registers are reset to their default values and SPI communication is possible but only in read mode (SPI registers can be read but cannot be written). In order to regulate the output current/voltage, it is necessary that VIN and IVCC_EXT are present and above their undervoltage threshold. ACTIVE In active state the device will start switching activity to provide power at the output only when PWMI = HIGH. To start the Highside gate drivers HSGD1,2 the voltage level VBST1,2 - VSWN1,2 needs to be above the threshold Datasheet 14 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply VBST1,2 - VSWN1,2_UVth. In ACTIVE state the device current consumption via VIN and VDD is dependent on the external MOSFET used and the switching frequency fSW. Power-up LHI = LOW & EN/INUVLO = HIGH EN/INUVLO = LOW SLEEP EN/INUVLO = LOW LHI = HIGH & EN/INUVLO = HIGH EN/INUVLO = LOW LHI = HIGH IDLE VIN = HIGH & IVCC = HIGH & IVCC_EXT = HIGH & VDD = HIGH & DVCCTRL.IDLE = LOW VIN = LOW or IVCC = LOW or IVCC_EXT = LOW or VDD = LOW or DVCCTRL.IDLE = HIGH LIMP HOME EN/INUVLO = LOW LHI = LOW ACTIVE LHI = HIGH Figure 6 Simplified State Diagram 5.2 Different Possibilities to RESET the device There are several reset triggers implemented in the device. After any kind of reset, the Transmission Error Flag (TER) is set to HIGH. Under Voltage Reset: EN/INUVLO: When EN/INUVLO is below VEN/INUVLOth (P_5.3.7), the SPI interface is not working and all the registers are reset to their default values. In addition, the device enters SLEEP mode and the current consumption is minimized. VDD: When VVDD is below VVDD(UV) (P_5.3.6), the SPI interface is not working and all the registers are reset to their default values. Reset via SPI command: There is a command (DVCCTRL.SWRST = HIGH) available to RESET all writeable registers with the exception of MUXCTRL, to their default values. Note that the result coming from the Calibration routine, which is readable by the SPI when DVCCTRL.ENCAL = HIGH, is not reset by the SWRST. Reset via Limp Home: When Limp Home state is detected the registers are reset to the default values. Datasheet 15 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply 5.3 Electrical Characteristics Table 6 EC Power Supply VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number VVIN(ON) – – 4.7 V VIN increasing; VEN/INUVLO = HIGH; VDD = 5 V; IVCC = IVCC_EXT = 10 mA; P_5.3.1 Input Undervoltage switch OFF VVIN(OFF) – – 4.5 V VIN decreasing; VEN/INUVLO = HIGH; VDD = 5 V; IVCC = IVCC_EXT = 10 mA; P_5.3.14 Device operating current IVIN(ACTIVE) – 5 7 mA 1) ACTIVE mode; VPWMI = 0 V; VVFB_VIN = 1/(51+1)*VVIN; VVFB=0.7V P_5.3.2 VIN Sleep mode supply current IVIN(SLEEP) – – 1.5 µA VEN/INUVLO = 0 V; VCSN = VDD = 5 V; VIN = 13.5 V; VIVCC = VIVCC_EXT= 0 V; P_5.3.3 Digital supply current IVDD – – 0.5 mA VIN = 13.5 V; fSCLK = 0 Hz; VPWMI = 0 V; VEN =VCSN = VDD = 5 V; P_5.3.4 Digital Supply Sleep mode current IVDD(SLEEP) – – 1.5 µA VEN/INUVLO = 0 V; VCSN = VDD = 5 V; VIN = 13.5 V; VIVCC = VIVCC_EXT = 0 V; P_5.3.5 Undervoltage shutdown threshold voltage VVDD(UV) 1 – 3 V VCSN = VDD; P_5.3.6 VSI = VSCLK = 0 V; SO from LOW to HIGH impedance; 1.75 1.9 V – Power Supply VIN Input Voltage Startup Digital Power Supply VDD EN/INUVLO Pin characteristics Input Undervoltage falling Threshold Datasheet VEN/INUVLOth 1.6 16 P_5.3.7 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Power Supply Table 6 EC Power Supply (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. EN/INUVLO Rising Hysteresis VEN/INUVLO(hy – Typ. Max. Unit Note or Test Condition Number 90 – mV 1) P_5.3.8 0.89 1.34 µA VEN/INUVLO = 0.8 V; P_5.3.9 2.2 3.3 µA VEN/INUVLO = 2 V; P_5.3.10 st) EN/INUVLO input Current LOW IEN/INUVLO(LO 0.45 W) EN/INUVLO input Current HIGH IEN/INUVLO(HI 1.1 GH) LHI Pin characteristics LOW level VLHI(L) 0 - 0.8 V – P_5.3.16 HIGH level VLHI(H) 2.0 - 5.5 V – P_5.3.17 L-Input pull-down current ILHI(L) 6 12 18 μA VLHI = 0.8 V; P_5.3.18 H-Input pull-down current ILHI(H) 15 30 45 μA VLHI = 2.0 V; P_5.3.19 tACTIVE – – 0.7 ms 1) P_5.3.11 Timings SLEEP mode to ACTIVE time VIVCC = VIVCC_EXT; CIVCC = 10 µF; VIN = 13.5 V; VDD = 5 V; 1) Not subject to production test, specified by design. Datasheet 17 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description 6 Regulator Description The TLD5542-1 includes all of the functions necessary to provide constant current to the output as usually required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.6). It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external MOSFETs. This topology is able to operate in high power Boost, Buck-Boost and Buck mode applications with maximum efficiency. The transition between the different regulation modes is done automatically by the device itself, with respect to the application boundary conditions. The Buck-Boost to Boost transition can be smoothed by mean of BB_BST_CMP bitfield. A SPI flag provides mode feedback to the µC (refer to SPI bits REGUSETMON.REGUMODFB). 6.1 Regulator Diagram Description The analog current control loop (A5, A6 with complessive gain = IFBxgm) connected to the sensing pins FBL, FBH regulates the output current. The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error in the output current loop is used to determine the appropriate duty cycle to get a constant output current. An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application boundary conditions. The inductor current for the current mode loop is sensed by the RSWCS resistor. RSWCS is used also to limit the maximum external switches / inductor current. If the Voltage across RSWCS exceeds its overcurrent threshold (VSWCS_buck or VSWCS_boost for buck or boost operation respectively) the device reduces the duty cycle in order to bring the switches current below the imposed limit. The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations. The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers (HSGD1,2 and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup . Once the soft start expires a forced CCM regulation mode is performed. The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage across RFB sets the output current. The output current is adjusted via the SPI register LEDCURRADIM.ADIMVAL plus an offset trimming on LEDCURRCAL.CALIBVAL register. Refer to Chapter 8.1 for more details. Datasheet 18 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description IIN M4 M1 COUT HSGD2 FBH LOUT M2 + M3 ISWCSx LSGD2 SWCS + LSGD1 FBL - BOOST A2 A8 - RSWCS A5 VOUT + HSGD1 IOUT RFB SLOPE SELECTION & Compensation - VIN - A9 A3 BUCK - + + SGND GATE DRIVER LOGIC HSGD1 HSGD2 LSGD1 LSGD2 CLK VFEEDBACK RVFBL2 Correction Unit ISoft_Start_PU RVFBH1 VFB 10k SOFT START LOGIC - VFB_VIN RVFBL1 GAIN VREF_INT A6 + RVFBH2 - ISoft_Start_PD SOFT START COMP 8 bit resolution 4 bit calibration DAC 1 SET Figure 7 RCOMP 0 MIN VCOMP CCOMP VSST CSOFT_START DAC_OFF OR LHI Regulator Block Diagram - TLD5542-1 An Infineon proprietary correction unit (see Figure 7) ensures optimum performance on MFS architecture, minimizing dependency of comp voltage by the analog dimming value, and reduces overshoots during load jump up. The correction unit provides an input voltage feedback to the regulator loop, proportional to Vout/Vin through the VFB/VFB_VIN signals. Therefore, the 2 voltage dividers at VFB and VIN_VFB are related to each other, and their ratio is setting the feedback amount. Correction unit feedback can be disabled by setting SWTMOD.VFB_VIN_OFF bitfield. The negative feedback applied to VCOMP is also proportional to the analog dimming value. The smaller the analog dimming value, the larger is the feedback voltage: 𝑉𝐹𝐸𝐸𝐷𝐵𝐴𝐶𝐾 ≈ 0.05 ∙ 𝑉𝑉𝐹𝐵 ∙ 100% − 𝐴𝐷𝐼𝑀[%] 𝑉𝑉𝐹𝐵𝑉𝐼𝑁 (6.1) [𝑉] In order to ensure good accuracy on VFB_VIN reading, the total resistance on the divider should be less than 100kΩ. It is recommended to have VFB_VIN / VFB voltage dividers ratio equal to 1 / 1.5 (I.E. RVFBH2=RVFBH1=51kΩ , RVFBL2=1kΩ , RVFBL1 =1.5kΩ). If the input voltage feedback is too high (I.E. RVFBL2 is too low), VCOMP may saturate toward the operating range limit ( 2V ) and the output current regulation would be affected. Minimum temperature, maximum Vout/Vin ratio and minimum ADIM value shall be considered as worst case condition when checking for VCOMP dynamic operating range. Datasheet 19 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description 6.2 Adjustable Soft Start Ramp The soft start routine has 2 functionalities: • Fault management: fault mask and wait-before-retry time (Figure 8 and chapter Chapter 10.2) • Limit input inrush current and output overshoots by limiting Vcomp (Figure 7) in boost mode The soft start routine is applied in two cases: • At startup (first PWM rise after IDLE to ACTIVE transition) • After output short to GND detection The soft start routine is active during the rising and falling edges of the VSST. The soft start timing is defined by a capacitor placed at the SOFT_START pin and the pull-up and pull down current sources (ISoft_Start_PU, ISoft_Start_PD). Minimum value for soft start capacitor has to be designed such that, at startup, the output voltage exceeds the short to ground threshold (VFBH_S2G_inc), before the soft start voltage reaches VSOFT_START_LOFF . Minimum temperature and minimum input voltage shall be considered as worst case condition for previously mentioned dimensioning. tACT IVE VIN VIN(ON) EN/INUVLO VIVCC_EXT VIVCC_EXT_RTH,d +VIVCCX_HYST t PWMI 8 clock cycles FBH VFBH_S2G_inc VFBH_S2G_dec SWN SHORT DETECTION ISOFT_START_PU ISOFT_START ISOFT_START_PD Vsoft_Start_reg Vsoft_Start_LOFF VSOFT_START Vsoft_Start_RESET Application Status Norm al Operation Startup Vout shorted to GND WAIT_BE FORE_RETRY tSO FT_STA RT Figure 8 Norm al Operation FAULT_MASK Soft Start timing diagram on a short to ground detected by the FBH pin Soft Start rising edge time is aproximately: 𝑡𝑆𝑂𝐹𝑇 _𝑆𝑇𝐴𝑅𝑇 =VSoft_Start_LOFF ∙ 𝐼 (6.2) 𝐶𝑆𝑜𝑓𝑡 _𝑆𝑡𝑎𝑟𝑡 𝑆𝑜𝑓𝑡 _𝑆𝑡𝑎𝑟𝑡 _𝑃𝑈 The Soft Start routine limits the inrush current during boost mode by clamping the COMP pin through a buffer as in Figure 7. Therefore this functionality is effective only when Soft Start capacitor is sufficiently larger than the comp capacitor. Datasheet 20 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description If the inductor current is low during the soft start rising edge, DCM is enabled and MOSFET M4 is disabled. If the inductor current increases then M4 may get enabled. After the soft start has been completed (VSOFT_START > VSOFT_START_LOFF) CCM is forced and M4 is permanently enabled, independently from the inductor current level. To avoid overshoot at startup on voltage regulators, may be useful to keep CCM forced also during soft start by setting CCM_4EVER bitfield. If a short circuit on the output is detected, a pull-down current source ISOFT_START_PD (P_6.4.20) is activated. This current brings down the VSOFT_START until VSOFT_START_RESET (P_6.4.22) is reached. Afterwards the pull-up current source ISOFT_START_PU (P_6.4.19) turns on again. If the fault condition hasn’t been removed until VSOFT_START_LOFF (P_6.4.21) is reached, the pull-down current source turns back on again, initiating a new cycle. This will continue until the fault is removed. If a low duty cycle PWMI is applied at startup, the output voltage may be still below the short to ground threshold once the soft start fault mask is expired. Therefore the TLD5542-1 has a special feature in order to prevent short to ground in case of startup with low duty cycle PWM. At first PWMI rise after IDLE to ACTIVE transition, the internal PWM signal is extended if the following conditions are met: • A capacitor is connected to the IOUTMON pin (suggested 220pF) • IDLE mode is kept for less than 10ms • PWMI rise is provided within 10ms from IDLE to ACTIVE transition The PWMI extension last until one of the two following conditions is reached: • Until VSOFT_START exceeds VSoft_Start_LOFF • Until VFBH-FBL exceeds VFBH_FBL_IN 6.3 Switching Frequency setup The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency with an external resistor according to the graph in Figure 9 or the following approximate formulas. f SW [kHz] = 5375* ( RFREQ[kΩ]) −0.8 (6.3) RFREQ[kΩ] = 46023* ( f SW [kHz])−1.25 (6.4) Figure 9 Datasheet Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ 21 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description 6.4 Operation of 4 switches H-Bridge architecture Inductor LOUT connects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4) Figure 10 BOOST MODE BUCK-BOOST MODE BUCK MODE M1 ON PWM PWM M2 OFF PWM PWM M3 PWM PWM OFF M4 PWM PWM ON 4 switches H-Bridge architecture Transistor Status summary VIN VOUT M1 HSGD1 M4 HSGD2 LOUT SWN1 SWN2 M2 M3 LSGD1 LSGD2 RSWCS Figure 11 4 switches H-Bridge architecture overview 6.4.1 Boost mode (VIN < VOUT) • M1 is always ON, M2 is always OFF • Every cycle M3 turns ON first and inductor current is sensed (peak current control) • M3 stays ON until the upper reference threshold is reached across RSWCS (Energizing) • M3 turns OFF, M4 turns ON until the end of the cycle (Recirculation) • Switches M3 and M4 alternate, behaving like a typical synchronous boost Regulator (see Figure 12) Datasheet 22 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description VIN ON VOUT M1 M4 HSGD1 LOUT SWN1 ILOUT HSGD2 (2) Recirculation SWN2 (1) Energizing OFF M2 M3 LSGD2 LSGD1 M1+M3 M1 + M4 M1+M3 M1 + M4 M1+M3 M1 + M4 t RSWCS Figure 12 4 switches H-Bridge architecture in BOOST mode Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach. • M2 is always OFF in this mode (open) • M1 is always ON in this mode (closed connection of inductor to VIN) • M4 acts as a synchronous diode, with significantly lower conduction power losses (I2 x RDSON vs. 0.7 V x I) Note: Diode is source of losses and lower system efficiency! LOUT M1 (ON) M4 VIN HSGD1 LSGD1 M2 (OFF) LOUT VOUT D1 VOUT VIN HSGD2 M3 M3 LSGD2 RSWCS RSWCS b) standard asynchronous BOOSTER a) 4 switch architecture BOOSTER Figure 13 4 switches H-Bridge architecture in BOOST mode compared to standard async Booster 6.4.2 Buck mode (VIN > VOUT) • M4 is always ON, M3 is always OFF • Every cycle M2 turns ON and inductor current is sensed (valley current control) • M2 stays ON until the lower reference threshold is reached across RSWCS (Recirculation) • M2 turns OFF, M1 turns ON until the end of the cycle (Energizing) • Switches M1 and M2 alternate, behaving like a typical synchronous BUCK Regulator (see Figure 14) Datasheet 23 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description VIN VOUT M1 HSGD1 (3) Energizing ON M4 LOUT SWN1 ILOUT HSGD2 SWN2 (4) Recirculation M2 M3 OFF M2+M4 LSGD2 LSGD1 M1 + M4 M1 + M4 M2+M4 M1 + M4 M2+M4 t RSWCS Figure 14 4 switches H-Bridge architecture in BUCK mode Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach. • M3 is always OFF in this mode (open). • M4 is always ON in this mode (closed connection inductor to VOUT). • M2 acts as a synchronous diode, with significantly lower conduction losses (I2 x RDSON vs. 0.7 V x I) LOUT VIN M4 (ON) M1 HSGD1 M2 M3 (OFF) LSGD1 VOUT LOUT M1 VIN VOUT HSGD1 HSGD2 LSGD2 D1 RSWCS b) standard asynchronous BUCK a) 4 switch architecture BUCK Figure 15 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK 6.4.3 Buck-Boost mode (VIN ~ VOUT) • When VIN is close to VOUT the controller is in Buck-Boost operation • All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output (M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost control scheme • The two buck boost waveforms and switching behaviors are displayed in Figure 16 below Datasheet 24 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description VIN ≤ VOUT ILOUT VIN VOUT M1 M4 (2) Direct Transfer HSGD1 HSGD2 M1 + M4 M1 + M4 M1 + M3 M1 + M4 M2+ M4 LSGD1 M1 + M3 M1 + M4 t M1 + M4 t VIN ≥ VOUT ILOUT LSGD2 RSWCS M2 + M4 M1 + M4 M1 + M4 M2 + M4 M1 + M4 M1 + M4 M1+ M3 M3 M1 + M4 M1+ M3 (1) Energizing M2 M1 + M4 M2+ M4 M1 + M3 SWN2 M1+ M3 LOUT (3) Recirculation SWN1 M2+ M4 (4) Direct Transfer M2 + M4 M1 + M4 Figure 16 4 switches H-Bridge architecture in BUCK-BOOST mode 6.5 Fast Output Discharge Operation Mode - Multi Floating Switches Topology Multiple light functions can be driven by a single DC/DC converter adopting a Multi Floating Switch (MFS) topology. In a MFS topology, each LED Function is connected in series and can be independently turned off via a bypass switch. Because of the series connections, all the functions are driven with the same current (except for Loads with complementary duty cycle I.E. DRL, LB ). Different brightness can be achieved with individual PWM duty cycles. In order to drive different LED functions in this topology, a Buck Boost converter is probably needed. A single stage buck boost topology has high efficiency buts requires several µF of output capacitance (COUT). The extra voltage present on this capacitor, when shorting one function to turn it off, may create a current spike in the LEDs that have to remain on. The TLD5542-1 has a dedicated state machine which controls a fast discharge of the output cap to a desired fraction of the initial output voltage. This Fast Output Discharge feature (F.D.), if carefully configured, limits the current spike during load jump events preventing LED damage. An Example of the Multi Floating Switch topology architecture and operation are shown in Figure 17 RVFBH F1 OFF F1 OFF To VFB External MOSFET Control via µC (C) (B) F2 OFF F2 ON External MOSFET Control via µC I F2 I F2 Vout Final RVFBL To VFB COUT DC/DC LITIX FLEX External MOSFET Control via µC (A) Datasheet 3x4.7µF RVFBH I F1 RVFBL F1 ON External MOSFET Control via µC Figure 17 I Disch COUT DC/DC LITIX FLEX RVFBL RVFBH VBAT CIN To VFB External MOSFET Control via µC FINAL CONDITION Vout Disharging 3x4.7µF COUT DC/DC LITIX FLEX FAST DISCHARGE Vout Initial 3x4.7µF INITIAL CONDITION F2 ON External MOSFET Control via µC Multi Floating Switch topology: operation sequence on 2 Functions: (F1+F2) to (F2) 25 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description The F.D. operation consists of discharging the capacitor COUT to the final load voltage (Figure 17-B) before the bypass switch closure. The external Microcontroller Software has to take care of the synchronization between the TLD5542-1 F.D. operation and the bypass Switches activation. The discharged energy from COUT is recovered back to the Input capacitor CIN which could cause a small overshoot on the CIN itself. This feature allows high efficiency designs also when PWM operation with repetitive Load Jumps is needed. The F.D. feature is needed when a negative VOUT step is performed, so when one or more LED functions are switched off. If additional LED functions are turned on, increasing the output voltage, the F.D. does not have to be used. In case analog dimming is performed during a load Jump (I.E. from 1A LB to 300mA DRL), even with a positive VOUT step, a discharge of the COMP capacitor could be necessary. In MFS topologies, a short interruption of the current is observed during the Load Transitions (either positive or negative) in all the functions, until VOUT is stable and the device control loop is able to provide the target output current. We will refer to any Voltage-Current or Load configuration just before the Load Jump as "Initial" (Figure 17A), while we will refer to any value after the system is in the new Load configuration as "Final" (Figure 17-C). Set the Target COUT discharge voltage The Target output voltage (VOUTFinal) of an F.D. operation is communicated to the TLD5542-1 as a fraction of the VOUT at the beginning of the Jump (VOUTInitial), and not as an absolute Value. In order to F.D. the output Capacitor to a desired Ratio of the initial voltage, two SPI commands have to be sent to the TLD5542-1 register MFSSETUP1. • The first is to write in the MFSSETUP1.LEDCHAIN the Ratio Denominator • The second is to write in the MFSSETUP1 register the Ratio Numerator and the Start Of Multi Floating Switch, respectively in the LEDCHAIN and SOMFS bitfields The time interval between the Ratio Denominator and Numerator SPI commands, needs to be long enough to sample the Initial Voltage of the F.D. in the FILT capacitor. After the second command, as soon as the Chip select is raised the F.D. begins. The final output voltage of the F.D. operation, after a MFS routine is correctly performed, will be approximately: VOUTFinal = RatioNumer ator ⋅ VOUTInitial RatioDenom inator (6.5) If RatioNumerator is bigger than RatioDenominator, the output voltage remains constant, but the COMP capacitor is discharged during all the TPREP F.D. operation will exit if the output voltage reaches VFBH_S2G_dec. Example: In order to jump from 6LED (18 V) to 2LEDs (6 V), the Ratio is 1/3 of initial voltage. So the 2 SPI commands that have to be sent are: Spi command 1: set MFSSETUP1 to 0x06 (Ratio Denominator = 6) Spi command 2: set MFSSETUP1 to 0x22 (Ratio Numerator+SOMFS = 0x02+0x20) Preparation Time tprep: The TLD5542-1 enables the user to set a period tprep on the load jump, where CCOMP is discharged continuously with a constant current (IEA_neg). Datasheet 26 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description The Preparation Time has to be sufficient for the capacitor CCOMP to be discharged the desired value. (6.6) 𝑡𝐷𝑖𝑠𝑐 ℎ𝐶𝑜𝑚𝑝 𝐶𝐶𝑂𝑀𝑃 = 𝐷𝑣𝑐𝑜𝑚𝑝 = 𝑡𝑝𝑟𝑒𝑝 𝐼𝐸𝐴_𝑛𝑒𝑔 In order to set a preparation time on the TLD5542-1, a SPI command has to be sent to the register MFSSETUP2.MFSDLY). The Equation (6.7) below describes the relationship between the switching frequency fSW and the MFSSETUP2.MFSDLY register value. t prep = 1 f SW ⋅ [2 + ( MFSDLY ) dec ] (6.7) For SPI command details refer to Chapter 12.6. The F.D. procedure is automatically extended until Cout capacitor is discharged to the target value, and Tprep is expired. If there is the need to do not discharge the CCOMP, but Discharge only the Vout , is possible to set MFSSETUP2.MFSDLY to 0 on a F.D. routine, Cout will be anyway discharged to the target voltage. Fast Discharge Phase After programming the desired output voltage Ratio via SPI , the right Preparation Time and activating the state machine (MFSSETUP1.SOMFS = HIGH) the TLD5542-1 inverts the inductor current IL and keeps its negative peak at a reduced switch current limit ISwLim until the VOUT reaches the desired target. 𝐼𝑆𝑤𝐿𝑖𝑚 ≈ 𝑉𝑆𝑊𝐶𝑆 _𝑏𝑜𝑜𝑠𝑡 2 ∙ 𝑅𝑆𝑊𝐶𝑆 3 (6.8) Figure 18 displays the relation of inductor current IL and the output voltage VOUT during a fast output discharge operation mode. Datasheet 27 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description External Mosfet Closure I F1 No current at the Load during F.O.D. I F2 EOMFS TPREP LED N. INITIAL LED N. FINAL + SOMF SPI CSN TPREP IL TDISCHARGE_COUT 1CLK ISwLim VCOMP VOUT_INITIAL VOUT_FINAL Normal Switching activity F1+F2 on Figure 18 Fast Output Discharge Current Break Recovery Low Normal Switching activity F1 on Fast Output Discharge timing diagram If the discharge current limit ISwLim needs to be reduced further , the MFSSETUP1.ILIM_HALF_MFS bit can be used to reduce it to the Equation (6.9) (only during the F.D. phase and not in normal operation), see SPI Chapter for further details Chapter 12.6. 𝐼𝑆𝑤𝐿𝑖𝑚 ≈ 𝑉𝑆𝑊𝐶𝑆 _𝑏𝑜𝑜𝑠𝑡 1 ∙ 𝑅𝑆𝑊𝐶𝑆 2 (6.9) Setting the EA_IOUT_MFS bit will reduce (only during the F.D. phase) the saturation current of the error amplifier A6 (IEA_neg) that discharges the Comp capacitor. Once VOUT reaches the desired target, the current recovery phase brings IL from a negative value back to 0 A and the device stays in “Brake-Low condition” (both Lowside gatedrivers = ON) until the programmed preparation time (MFSSETUP2.MFSDLY) expires. Only when both the current recovery phase has ended and tprep is expired an SPI flag( STD bit EOMFS) and the pin EOMFS are set to HIGH. One clock cycle after EOMFS is asserted, the TLD5542-1 starts automatically switching again. Figure 18 displays one Fast Output Discharge cycle. Sequence of operations to perform a Fast Output Discharge In order to perform a F.D .operation, the user has to : • Send via SPI to MFSSETUP1.LEDCHAIN the Ratio Denominator. • Set via SPI an adequate Preparation Time • Send via SPI to MFSSETUP1.LEDCHAIN the Ration Numerator + SOMFS Datasheet 28 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description • Wait until preparation time is expired and Vout has reached the target value (EOMFS is asserted) • Adjust the Floating switches to the new configuration In case of short to GND the routine is not executed or it is aborted. At startup (after EN = High), if PWM has never been set to HIGH, F.D. routine can not be executed. If a F.D. is needed just after device enable (for instance to lower the output voltage after a low battery reset), PWMI has to be set to 1 before the SOMFS command, and the F.D. procedure will be executed only once the SS is expired. Other than for the 2 above exceptions, it is always possible to perform F.D. independently from PWM signal and output overvoltage condition. Datasheet 29 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description 6.6 Programming Output Voltage (Constant Voltage Regulation) For a voltage regulator, the output voltage can be set by selecting the values RFB1, RFB2 according to the following Equation (6.10): 𝑉𝑂𝑈𝑇 = 𝑅𝐹𝐵1 + 𝑅𝐹𝐵2 ∙ 𝑉𝐹𝐵𝐻−𝐹𝐵𝐿 𝑅𝐹𝐵1 (6.10) Refer to the voltage regulator application drawing on Figure 45. After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits ADIMVAL. Datasheet 30 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description 6.7 Electrical Characteristics Table 7 EC Regulator VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 145.5 150 154.5 mV ADIMVAL = 240; P_6.4.1 12 15 18 mV ADIMVAL =24; Calibration Procedure not performed P_6.4.5 Regulator: VFBH-FBL_REF reference voltage VFBHFBL_REF VFBH-FBL_REF reference voltage VFBHFBL_REF FBH Bias current @ highside sensing setup IFBH_HSS 65 110 155 µA 1) VFBL = 7 V; VFBH - FBL = 150 mV; P_6.4.8 FBL Bias current @ highside sensing setup IFBL_HSS 17 30 43 µA 1) VFBL = 7 V; VFBH - FBL = 150 mV; P_6.4.9 A6 sense Amp +sat current IEA_pos 25 29 33 µA 1) VCOMP = 1V; ADIMVAL = 240; VFBH - FBL = 0 mV P_6.10.2 A6 sense Amp -sat current IEA_neg -63 -56 -49 µA 1) VCOMP = 1V; ADIMVAL = 240; VFBH - FBL = 500 mV P_6.10.3 A5A6 sense Amp gm IFBxgm – 890 – µS 1) P_6.4.10 Output Monitor Voltage VIOUTMON 1.33 1.4 1.47 V P_6.4.11 Maximum BOOST Duty Cycle DBOOST_MA 89 91 93 % VFBH - FBL = 150 mV; 1) fsw = 300 kHZ; 1 1.05 V P_6.4.15 VIIN1 - IIN2 = 50 mV; VIIN1 = VVIN(ON) to 55 V; EA_GM=0 P_6.4.12 X 0.95 1) Input current Monitor Voltage VIINMON Switch Peak Over Current Threshold - BOOST VSWCS_boost 70 76 82 mV 1) P_10.8.1 5 Switch Peak Over Current Threshold - BUCK VSWCS_buck -60 -50 -40 mV 1) P_10.8.1 6 ISoft_Start_P 22 26 32 µA VSoft_Start = 1 V; P_6.4.19 2.6 3.2 µA VSoft_Start = 1 V; P_6.4.20 1.75 1.85 V – P_6.4.21 0.2 0.3 V – P_6.4.22 Soft Start Soft Start pull up current U Soft Start pull down current ISoft_Start_P 2.2 D Soft Start Latch-OFF Threshold VSoft_Start_L 1.65 OFF Soft Start Reset Threshold VSoft_Start_R 0.1 ESET Datasheet 31 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description Table 7 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition 2 2.1 V 1) P_6.9.3 No Faults Number Soft Start Voltage during regulation VSoft_Start_r 1.9 Output Current init reference Voltage VFBH-FBL VFBH_FBL_IN 11 17.5 24 mV VFB = 1.4 V; P_10.8.1 0 Output Current EA_GM boost reference Voltage VFBH-FBL VFBH_FBL_E – 120 - mV 1) VFB = 1.4 V; ADIMVAL =240; P_6.10.4 eg A Oscillator Switching Frequency fSW 285 300 315 kHz Tj = 25°C; RFREQ= 37.4 kΩ; P_6.4.23 SYNC Frequency fSYNC 200 – 700 kHz – P_6.4.24 SYNC Turn On Threshold VSYNC,ON 2 – – V – P_6.4.25 SYNC Turn Off Threshold VSYNC,OFF – – 0.8 V – P_6.4.26 SYNC High Input Current ISYNC,H 15 30 45 µA VSYNC = 2.0 V; P_6.4.62 SYNC Low Input Current ISYNC,L 6 12 18 µA VSYNC = 0.8 V; P_6.4.63 – 4 V VBST1,2 - VSWN1,2 decreasing; P_6.4.64 HSGD1,2 NMOS driver on-state RDS(ON_PU) 1.4 resistance (Gate Pull Up) HS 2.3 3.7 Ω VBST1,2 - VSWN1,2 = 5 V; Isource = 100 mA; P_6.4.28 HSGD1,2 NMOS driver on-state RDS(ON_PD) 0.6 resistance (Gate Pull Down) HS 1.2 2.2 Ω VBST1,2 - VSWN1,2 = 5 V; Isink = 100 mA; P_6.4.29 LSGD1,2 NMOS driver on-state resistance (Gate Pull Up) RDS(ON_PU) 1.4 2.3 3.7 Ω VIVCC_EXT = 5 V; Isource = 100 mA; P_6.4.30 LSGD1,2 NMOS driver on-state resistance (Gate Pull Down) RDS(ON_PD)L 0.4 1.2 1.8 Ω VIVCC_EXT = 5 V; Isink = 100 mA; P_6.4.31 HSGD1,2 Gate Driver peak sourcing current IHSGD1,2_SR 380 – – mA 1) P_6.4.32 HSGD1,2 Gate Driver peak sinking current IHSGD1,2_SN 410 Gate Driver for external Switch Gate Driver undervoltage threshold VBST1,2VSWN1,2_UVth Datasheet 3.4 VBST1,2VSWN1,2_UVt h LS S VHSGD1,2 - VSWN1,2 = 1 V to 4 V; VBST1,2 - VSWN1,2 = 5 V C – – mA 1) P_6.4.33 VHSGD1,2 - VSWN1,2 = 4 V to 1 V; VBST1,2 - VSWN1,2 = 5 V K 32 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Regulator Description Table 7 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – mA LSGD1,2 Gate Driver peak sourcing current ILSGD1,2_SRC 370 – LSGD1,2 Gate Driver peak sinking current ILSGD1,2_SN 550 – LSGD1,2 OFF to HSGD1,2 ON delay tLSOFF- HSGD1,2 OFF to LSGD1,2 ON delay tHSOFF- 1) Number P_6.4.34 VLSGD1,2 = 1 V to 4 V; VIVCC_EXT = 5 V; – mA 1) P_6.4.35 VLSGD1,2 = 4 V to 1 V; VIVCC_EXT = 5 V; K 15 30 40 ns 1) P_6.4.36 35 60 75 ns 1) P_6.4.37 HSON_delay LSON_delay 1) Not subject to production test, specified by design Datasheet 33 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Digital Dimming Function 7 Digital Dimming Function PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string. 7.1 Description A PWM signal can be transmitted to the TLD5542-1 as described below. PWM via direct interface The PWMI pin can be fed with a pulse width modulated (PWM) signals, this enables when HIGH and disables when LOW the gate drivers of the main switches. µC PWM Digital dimming PWMI +3.3V or +5V SPI VDD CSN SI SO SCLK VSS AGND Figure 19 Digital Dimming Overview Note: In Register REGUSETMON.REGUMODFB the regulation mode can be read. During PWMI = LOW the SPI will always deliver the Regulation mode which was present at PWMI = HIGH as actual regulation mode, instead of “no Regulation”. To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state should not be used to suspend the output current for long time intervals. To stop in a safe manner DVCCTRL.IDLE=HIGH or EN/INUVLO=LOW can be used. Datasheet 34 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Digital Dimming Function VEN/INUVLO tACT IVE VEN/INUVLOth t VIVCC_EXT VIVCC_EXT_RTH,d +VIVCCX_HYST t tPWMI,H TPWMI VPWMI VPWMI,ON VPWMI,OFF t Switching activity t VCOMP t VOUT t ILED t VIOUTMON 200mV t Power ON Figure 20 Datasheet Normal Dim Normal Dim Normal Dim Gate ON Gate OFF Gate ON Gate OFF Gate ON Gate OFF Diagnosis ON Diag OFF Diag ON Diag OFF Diag ON Diag OFF Timing Diagram LED Dimming and Start up behavior example ( VVDD and VVIN stable in the functional range and not during startup) 35 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Digital Dimming Function 7.2 Electrical Characteristics Table 8 EC Digital Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number PWMI Input: PWMI Turn On Threshold VPWMI,ON 2 – – V – P_7.2.1 PWMI Turn Off Threshold VPWMI,OFF – – 0.8 V – P_7.2.2 PWMI High Input Current IPWMI,H 15 30 45 µA VPWMI = 2.0 V; P_7.2.4 PWMI Low Input Current IPWMI,L 6 12 18 µA VPWMI = 0.8 V; P_7.2.5 Datasheet 36 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Analog Dimming and Limp Home 8 Analog Dimming and Limp Home If the TLD5542-1 is used as current regulator, the analog dimming feature allows control of the LED peak current level from the default maximum value. If the device is used as voltage regulator, then the analog dimming can be used to reduce the output voltage. In this chapter the assumption is to have it as a current regulator. 8.1 Description For the calculation of the output current IOUT the following Equation (8.1) is used: I OUT = V FBH − V FBL R FB (8.1) The analog dimming feature is adjusting the average LED current level via the control of the feedback error amplifier reference voltage VFBH-FBL_REF. In the default state (DAC_OFF=0 and LHI=LOW), the current adjustment is done via a 8BIT SPI parameter (LEDCURRADIM.ADIMVAL) as shown on Figure 21 . If DAC_OFF = 1 then the error amplifier reference voltage is the minimum between SET pin and DAC value. Therefore, in order to have a full scale dimming via SET pin , ADIMVAL has to be set to 240. VFBH-FBL_REF [mV] 4 bit CALIB VAL 150 0 240 8 bit ADIMVAL Figure 21 Analog Dimming Overview Analog dimming adjustment during Limp Home state: To enter in Limp Home state the LHI pin must be HIGH. Note: If the PWMI and the EN/INUVLO are not set to HIGH, it is not possible to enable switching, even during Limp Home state. In Limp Home state, or if DAC_OFF=1, the analog dimming control is done via the SET pin. A resistor divider between IVCC/IVCC_EXT, SET and GND can be used to fix a load current/voltage value (refer to below). When Limp Home is entered, the device will discharge the output capacitor with a F.D. Routine down to VFBH_S2G_dec (MFSDLY set to the default Value). At the end of the F.D. routine, if the PWMI is kept HIGH, the device will start regulating with the analog dimming level provided by the SET pin. Datasheet 37 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Analog Dimming and Limp Home CIN > VIN(PO) > VIVCC_EXT_RTH,d IVCC HSGD1 FAIL SAFE Circuit HIGH CBST1 CBST2 M1 SWN1 LIMPHOME COUT M4 LOUT M2 LHI IOUT RFB M3 LSGD1 RVFBH BST1 BST2 RVFBL SET Current Regulation D2 D1 R5 IVCC R4 default output current/voltage adjustment CIVCC IVCC_ext VIN EN/INUVLO Load PWMI_LH FAIL SAFE Circuit SPI Writing disabled during Limp Home state Figure 22 CSN SI SO SCLK RFB2 SGND PGND1 PGND2 LSGD2 SWN2 HSGD2 VFB FBH PWMI RFB3 Set HIGH to activate output FBL VSS Voltage Regulation RSWCS SWCS AGND Limp Home state schematic overview Using the SET pin to adjust the output current: During Limp Home state or if DAC_OFF = 1, the average IOUT can be adjusted by controlling the voltage at the SET pin (VSET) between 0.2 V and 1.4 V. The typical IOUT behaviour is described by Equation (8.2) below: I OUT = V SET − 200 mV R FB ⋅ 8 (8.2) If VSET is 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators. To assure the switching activity is stopped and IOUT = 0, VSET has to be < 100 mV, see Figure 23. VFBH-FBL 150mV 100mV 0mV 200mV 1.4V Analog Dimming Enabled Figure 23 Analog Dimming Overview 8.2 LED current calibration procedure 1.5V VSET Analog Dimming Disabled The LED current calibration procedure improves the accuracy during analog dimming. In order to be most effective, this routine has to be performed in the application, when the TLD5542-1 temperature and the output Datasheet 38 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Analog Dimming and Limp Home voltage are the ones in which the driver has to be accurate. The output current must be 0 during the procedure run. The optimum should be to re-calibrate the output periodically every time the application has PWMI=LOW for a sufficent long time . Current calibration procedure: • Power the load with a low analog dimming value (for example 10%) • Set PWMI = LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions and bring the output current to 0) • Quickly (to avoid Vout drifts) µC enables the calibration routine: DVCCTRL.ENCAL = HIGH • Quickly (to avoid Vout drifts) µC starts the calibration: LEDCURRCAL.SOCAL = HIGH • Waiting time (needed to internally perform the calibration routine) → aprox. 200 µs • TLD5542-1 will set the FLAG: LEDCURRCAL.EOCAL = HIGH, when calibration routine has finished • Reconnect the load • The output current is automatically adjusted to a low offset and more accurate analog dimming value Once the calibration routine is correctly performed, the output current accuracy with analog dimming = 10% (LEDCURRADIM.ADIMVAL = 24) is 10%. The Calibration routine is not affecting the accuracy at 100% analog dimming. The ENCAL Bits affect both device operation and CALIBVAL reading result: • ENCAL = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read back from CALIBVAL • ENCAL = LOW: SPI value written in CALIBVAL is used by internal circuitry and can be read back; calibration routine start is inhibited As a result, μC can use a stored result from a previously performed calibration to directly impose the desired value without waiting for a new routine to finish. OUT H-Bridge Vint_supply FBH VFBH-FBL RFB V_sense_in FBL + IOUT_sense - V_sense_out + to LED Load IDC_offset Latch - IIN_feedback ADC out - ADC CLK EA ADC Latch 8 bit resolution 4 bit calibration DAC + COMP 2Bit Monitoring Logic ADC CLK Figure 24 Datasheet LED current accuracy calibration overview 39 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Analog Dimming and Limp Home 8.3 Electrical Characteristics Table 9 EC Analog Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Source current on SET Pin Symbol ISET_source Values Min. Typ. Max. – – 1 Unit Note or Test Condition µA 1) Number VSET = 0.2 V to 1.4 V; P_8.3.4 1) Specified by design: not subject to production test. Datasheet 40 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Linear Regulator 9 Linear Regulator The TLD5542-1 features an integrated voltage regulator for the supply of the internal gate driver stages. Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative gate driver supply if required. 9.1 IVCC Description When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal gate drivers with a typical voltage of 5 V and current up to ILIM (P_9.2.2). An external output capacitor with low ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the external MOSFET switches will draw transient currents from the linear regulator and its output capacitor (Figure 25, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC (P_9.2.4). Alternative IVCC_EXT Supply Concept: The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers. This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 25, drawing B). Integrated undervoltage protection for the external switching MOSFET: An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This undervoltage reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls below their undervoltage Reset switch OFF Thresholds VIVCC_RTH,d (P_9.2.9) and VIVCC_EXT_RTH,d (P_9.2.5). In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching activity. The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the external logic level N-channel MOSFETs. A VIN EN/ INUVLO Internal VREG VIN Voltage Protection + Enable B IVCC Power On Reset VIN EN/ INUVLO IVCC_EXT Gate Drivers Figure 25 Datasheet Internal VREG VIN Voltage Prot ection + Enable IVCC Power On Reset IVCC_EXT External VREG Gate Drivers Voltage Regulator Configurations 41 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Linear Regulator 9.2 Electrical Characteristics Table 10 EC Line Regulator VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number IVCC Output Voltage VIVCC 4.8 5 5.2 V VIN= 13.5 V; 0.1 mA ≤ IIVCC ≤ 50 mA; P_9.2.1 Output Current Limitation ILIM 70 90 110 mA 1) P_9.2.2 Drop out Voltage (VIN VIVCC) VDR – 200 350 mV VIN = 5 V; IIVCC = 10 mA; P_9.2.3 IVCC Buffer Capacitor CIVCC 10 – – µF 1) 2) P_9.2.4 V 3) P_9.2.5 VIVCC = 4 V; IVCC_EXT Undervoltage VIVCC_EXT_R 3.6 Reset switch OFF TH,d Threshold 3.8 IVCC Undervoltage Reset VIVCC_RTH,d 3.6 switch OFF Threshold 3.8 IVCC and IVCC_EXT VIVCCX_HYST 0.315 Undervoltage Hysterisis 0.365 4.0 VIVCC_EXT decreasing; 4.0 V 3) P_9.2.9 VIVCC decreasing; 0.395 V VIVCC increasing; VIVCC_EXT increasing; P_9.2.6 1) Not subject to production test, specified by design 2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum. Use capacitors with LOW ESR. 3) Selection of external switching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be considered. Datasheet 42 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions 10 Protection and Diagnostic Functions 10.1 Description The TLD5542-1 has integrated circuits to diagnose and protect against overvoltage, short circuits of the load and overtemperature faults. Furthermore, the device provides a 2 Bit information of ILED, IIN by the SPI to the µC. In IDLE state, only the overtemperature Shut Down, overtemperature warning, IVCC or IVCC_EXT undervoltage monitor, VDD or VEN/INUVLO undervoltage monitor are reported according to specifications. In a summary of the protection, diagnostic and monitor functions is displayed. SPI Protection and Diagnostic SPI STD Diagnosis Overvoltage SPI OR Stop gate drivers Short at the Load SPI Device Overtemperature SPI Linear Regulators OFF OR (only IVCC disabled in case of overtemperature) Input Undervoltage LEDCUR pin Monitoring COMPARATOR Read-back via SPI 2BIT data FBH - FBL 2BIT data IIN1- IIN2 2BIT data Mode Indication IOUTMON pin GAIN , OFFSET IINMON pin GAIN Figure 26 Protection, Diagnostic and Monitoring Overview - TLD5542-1 Note: A device Overtemperature event overrules all other fault events! Datasheet 43 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions 10.2 Output Overvoltage, Short circuit protection The VFB pin measures the voltage on the application output and in accordance with the populated resistor divider overvoltage thresholds is set. The Short to GND at the output is detected by a fixed threshold on the FBH pin VIN VFBH_S2G CIVCC IVCC BST1 BST2 HSGD1 M1 SWN1 VOUT D2 D1 CBST1 CBST2 M4 COUT RVFBH VVFB_OVTH LOUT M2 RFB M3 LSGD1 RVFBL SWCS RSWCS SGND PGND LSGD2 SWN2 HSGD2 VFB FBH FBL Figure 27 Over Voltage and Short to grond Protection Pins - Overview 10.2.1 Short Circuit protection The device detects a short circuit at the output if this condition is verified: • The pin FBH falls below the threshold voltage VFBH_S2G_dec for at least 8 clock cycles It is possible to disable short circuit protection by setting SWTMOD.S2G_OFF to 1, this could be useful for high output voltage swing applications (like MFS topology) . In case of short to GND, the device will simply regulate the pre-fixed current to GND, without endangering the application. During the rising edge of the Soft Start the short circuit detection is ignored until VSOFT_START_LOFF (see Figure 8). After a short circuit detection, the SPI flag (SHRTLED) in the STD diagnosis register is set to HIGH and the gate drivers stop delivering output current (Brake-Low condition, both LS MOSFETs ON). The Device will auto restart with the soft start routine described in Chapter 6.2. The dedicated diagnosis flag (SHRTLED) will be cleared after the next reading cycle of the STD diagnosis. To prevent false S2G tripping after startup, a large enough soft-start capacitor must be used to allow the output voltage to get above the S2G condition. Note: Datasheet If the short circuit condition disappears, the device will re-start with the soft start routine as described in Chapter 6.2. 44 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions 10.2.2 Overvoltage Protection A voltage divider between VOUT, VFB pin and AGND is used to adjust VOUT overvoltage protection threshold (VOUT_OV), refer to Figure 27 and Equation (10.1): 𝑉𝑂𝑈𝑇 _𝑂𝑉 = 𝑉𝑉𝐹𝐵_𝑂𝑉𝑇𝐻 ∙ 𝑅𝑉𝐹𝐵𝐻 + 𝑅𝑉𝐹𝐵𝐿 𝑅𝑉𝐹𝐵𝐿 (10.1) If VVFB gets higher than its overvoltage threshold VVFB_OVTH , the SPI flag (OUTOV) in the STD diagnosis set to HIGH and the gate drivers stop switching for output regulation (Brake-Low condition both LS MOSFETs ON). When VVFB_OVTH- VVFB_OVTH,HYS threshold is reached the device will auto restart. The dedicated diagnosis flag (OUTOV) will be cleared after the next reading cycle of the STD diagnosis. If the overvoltage threshold VOUT_OV is set below the maximum VIN application operating range, then attention needs to be paid to the overvoltage behavior. If load current persists during overvoltage event, repetitive overvoltage triggering may occur with a high frequency. This prevents inductor current regulation and the output current may even increase. To avoid this condition, proper sizing of the external components is needed (i.e. increase the output capacitance or the overvoltage threshold in order to delay the overvoltage trigger). 10.3 Input voltage monitoring, protection Input undervoltage shutdown level can be defined through an external resistor divider, as shown in . EN/INUVLO pin voltages are internally compared to their respective thresholds by means of hysteretic comparators. Neglecting the hysteresis, the following equations hold: 𝑈𝑉𝑡ℎ = 𝑅1 + 𝑅2 ∙ 𝐸𝑁/𝐼𝑁𝑈𝑉𝐿𝑂𝑡ℎ 𝑅2 (10.2) RIN VIN IN2 IN1 R1 EN/INUVLO R2 Figure 28 Input Voltage Protection 10.4 Input current Monitoring The two inputs (IIN1, IIN2) can be used to monitor the Input current. The input current, measured via IIN1 and IIN2 pins, can be monitored through an analog output pin and an SPI routine. Datasheet 45 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions The IINMON pin provides a linear indication of the current flowing through the input. The following Equation (10.3) is applicable: V IINMON = I IN ⋅ R IN ⋅ 20 (10.3) Purpose of the input current monitoring routine is to verify if the input current level is in the range of the Input Current Sense threshold VIIN1-IIN2. • The output of the Input Current Sense is compared to the internal precise reference voltage • The comparator works like a 2 bit window ADC referred to the internal precise reference voltage To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready when CURRMON.EOMON is read HIGH. The result of the input monitor routine is reported on the CURRMON.INCURR bit. RIN VIN ADC out 2Bit Monitoring Vint_supply 00b 01b 1 + ADC CLK 3 + Vref_int - Latch ADC out ADC CLK ADC Latch IINMON Figure 29 Input Current Monitoring General Overview 10.5 Output current Monitoring 1 2 3 LIMIT = VIN1-IN2 * 20 2 IIN @ 90% of Limit IIN_sense IN1 10b Logic IIN @ 75% of Limit VIN1-IN2 11b feedback - IIN @ 60% of Limit IN2 ADC in The output current can be monitored through an analog output pin, an open drain flag, an SPI routine and a STD diagnosis bit. LEDCUR is an open drain output, signaling LED current detected in MFS topologies. The corresponding detection threshold is defined by kLEDC_INC and kLEDC_DEC. LEDCUR pin voltage raises to HIGH when VFBH-FBL/VFBH-FBL_REF > kLEDC_INC, and is pulled LOW when VFBH-FBL/VFBHFBL_REF < kLEDC_DEC. Both kLEDC_INC and kLEDC_DEC are depending on analog dimming value, as shown on . The same information is also present on the STD diagosis via SPI , in the LEDCUR bit. For a less immediate, but more detailed information about the output current, the SPI current monitor routine can be used: • The output of the Led Current Sense is compared to the output of the Analog Dimming DAC • The comparator works like a 2 bit window ADC around 8 bit DAC output To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready when CURRMON.EOMON is read HIGH. When CURRMON.SOMON bit is set to HIGH both input and output current monitor routines are executed in parallel. The result of the monitor routine is reported on the CURRMON.LEDCURR bit. Datasheet 46 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions The IOUTMON pin provides a linear indication of the current flowing through the LEDs. The typical IOUTMON behaviour follows Equation (10.4) : = 200 mV + I OUT ⋅ R FB ⋅ 8 V IOUTMON (10.4) The typical output impedance of the IOUTMON is 24k Ohm. ADC out OUT H-Bridge 2Bit Monitoring IOUTMON Vint_supply 11b Datasheet 8 bit dim 4 bit cal 01b ADC in ADC out + ADC CLK ADC Latch - DAC Vref_int EA COMP VIOUT_target +25% + Figure 30 Latch - VIOUT_target LEDCUR 00b ADC CLK + IDC_offset 10b Logic V_sense_out VIOUT_target to LED Load V_sense_in FBL - VFBH-FBL RFB feedback + IOUT_sense - VIOUT_target -25% FBH Output Current Monitoring General Overview 47 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions 10.6 Device Temperature Monitoring A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning temperature, the temperature warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature falls below the warning threshold (with hysteresis), the TW bit is reset to LOW again). If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC regulator are shut down as described in Figure 31 and the temperature shut-down bit: TSD is set to HIGH. The TSD bit is latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior. Note: The Device will start up with a soft start routine after a TSD condition disappear. Tj TjSD,hyst TjSD TjW TjSD_exit TjW_exit TjW,Hyst t xSGDx Gate Drivers autorestart Operating t OFF IVCC 5V IVCC autorestart OFF t TW bit 1 NO ERROR TW bit is reset automatically 0 t 1 NO ERROR 0 Figure 31 Datasheet Warning TSD error bit TSD error bit latched until next reset or CLRLAT t Device Overtemperature Protection Behavior 48 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Protection and Diagnostic Functions 10.7 Electrical Characteristics Table 11 EC Protection and Diagnosis VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Short to GND exit threshold VFBH_S2G_i 1.95 2.05 2.15 V 1) VFBH increasing; P_6.9.1 Short to GND entry threshold VFBH_S2G_d 1.65 1.75 1.85 V 1) VFBH decreasing; P_6.9.2 Short Circuit Protection nc ec LEDCUR detect threshold increasing kLEDC_INC 60 70 80 % 1) ADIMVAL = 240 VFBH-FBL increasing; P_10.7.1 LEDCUR detect threshold increasing kLEDC_INC 45 55 65 % 1) ADIMVAL = 48 VFBH-FBL increasing; P_10.7.2 LEDCUR detect threshold decreasing kLEDC_DEC 50 60 70 % 1) ADIMVAL = 240 VFBH-FBL decreasing; P_10.7.3 LEDCUR detect threshold decreasing kLEDC_DEC 30 40 50 % 1) ADIMVAL = 48 VFBH-FBL decreasing; P_10.7.4 LEDCUR detect hysteresys kLEDCUR_HY - 12 - % 1) P_10.7.5 ADIMVAL = 48 to 240 S Temperature Protection: Thermal Warning junction temperature Tj,W 125 140 155 °C 1) P_10.8.2 Temperature warning Hysteresis Tj,W,hyst – 10 – °C 1) P_10.8.3 Over Temperature Shutdown Tj,SD 160 175 190 °C 1) P_10.8.4 Over Temperature Shutdown Hysteresis Tj,SD,hyst – 10 – °C 1) P_10.8.5 Overvoltage Protection: VFB Over Voltage Feedback Threshold VVFB_OVTH 1.42 1.46 1.50 V Output Over Voltage Feedback Hysteresis VVFB_OVTH, 25 40 58 mV Output Voltage decreasing; P_10.8.7 2.1 – kΩ 1) P_10.8.14 HYS P_10.8.6 Flags LEDCUR, EOMFS Pin Output Impedance RF12 – When Pull Down is active I=100uA 1) Specified by design; not subject to production test. Note: Datasheet Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 49 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11 Infineon FLAT SPECTRUM Feature set 11.1 Description The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout is already done and the HW designed. 11.2 Synchronization Function The TLD5542-1 features a SYNC input pin which can be used by a µC pin to define an oscillator switching frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to the dedicated DC/DC devices in the system. Refer to Figure 32 Note: The Synchronization function can not be used when the Spread Spectrum is active. H-Bridge DCDC MASTER BUCKBOOST GATE CONTROL SYNC LOGIC e.g. 400kHz Phaseshift A H-Bridge DCDC Slave SYNC1 µC SYNC SYNC2 e.g. 400kHz Phaseshift B Figure 32 Datasheet INPUT BUCKBOOST GATE CONTROL LOGIC defined phase shift between Outputs of different devices Synchronization Overview 50 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.3 Spread Spectrum The Spread Spectrum modulation technique significantly improves the lower frequency range of the spectrum (f < 30 MHz). By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor is important for the low frequency filter characteristic. This can be an economic benefit if there is a strong requirement for average limits. The TLD5542-1 features a built in Spread Spectrum function which can be enabled (SWTMOD.ENSPREAD) and adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency fFM, (P_11.6.3) and (P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency fdev, (P_11.6.1) and (P_11.6.2) (SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 33 for more details. The following adjustments can be programmed when SWTMOD.ENSPREAD = HIGH: SWTMOD.FMSPREAD = LOW: 12 kHz SWTMOD.FMSPREAD = HIGH: 18 kHz SWTMOD.FDEVSPREAD = HIGH: ±8% of fSW SWTMOD.FDEVSPREAD = LOW: ±16% of fSW Note: The Spread Spectrum function can not be used when the synchronization pin is used. fSW fdev t 1 f Figure 33 Datasheet FM Spread Spectrum Overview 51 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.4 EMC optimized schematic Figure 34 below displays the Application circuit with additional external components for improved EMC behavior. LPI VIN CPI1 CPI2 CIN2 RIIN CPI3 CPI4 CIN1 CIVCC IVCC_EXT VIN IVCC Rfilter BST1 BST2 IIN2 Cfilter R1 IIN1 EN/INUVLO R2 D1 DHSG1 RFREQ SOFT_START FREQ PWMI IINMON IOUTMON Digital dimminig Advanced monitoring via µC +3.3V or +5V VDD CSN SI SO SCLK Spread Spectrum ON/OFF via SPI SWCS CBST2 CBST1 LOUT RM2 M2 LSGD1 COMP CM1 RHSG1 DLSG1 CSOFT_START RM1 M1 HSGD1 CM2 RLSG1 CFBH-FBL RVFBH CPO1 CPO2 RHSG2 CPO3 CPO4 RVFBL M3 DLSG2 SGND PGND1 PGND2 LSGD2 SWN2 HSGD2 VFB COUT CM3 RSWCS FBH M4 CM4 RM3 LPO RFB RM4 SWN1 CCOMP RCOMP D2 RLSG2 DHSG2 4LED in series / 1A CFBH FBL VSS AGND CFBL RSPI Figure 34 Application Drawing Including Additional Components for an Improved EMC Behavior Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Datasheet 52 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Infineon FLAT SPECTRUM Feature set 11.5 Electrical Characteristics Table 12 EC Spread Spectrum VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – ±8 – % Number Spread Spectrum Parameters Frequency Deviation fdev 1) P_11.6.1 SWTMOD.FDEV SPREAD = HIGH; Frequency Deviation fdev – ±16 – % 1) P_11.6.2 SWTMOD.FDEV SPREAD = LOW; Frequency Modulation fFM – 12 – kHz 1) P_11.6.3 SWTMOD.FMSP READ = LOW; Frequency Modulation fFM – 18 – kHz 1) P_11.6.4 SWTMOD.FMSP READ = HIGH; 1) Specified by design; not subject to production test. Datasheet 53 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits. Otherwise, a TER (i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as with 8 bit SPI devices. SO MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB LSB CSN SCLK time SPI _16bit.emf Figure 35 Serial Peripheral Interface 12.1 SPI Signal Description CSN - Chip Select The system microcontroller selects the TLD5542-1 by means of the CSN pin. Whenever the pin is in LOW state, data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CSN HIGH to LOW Transition • The requested information is transferred into the shift register. • SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI. • If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will occur. • TER Flag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of the SCLK according to the Figure 36. Datasheet 54 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) STDDIAG.TER SI OR SO 1 0 SI SPI SO S CSN SCLK S SPI_16bitTER .emf Figure 36 Combinatorial Logic for TER bit CSN LOW to HIGH Transition • Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the transmission error bit (TER) is set and the command is ignored. • Data from shift register is transferred into the addressed register. SCLK - Serial Clock This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition, otherwise the command may be not accepted. SI - Serial Input Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 12.5 for further information. SO Serial Output Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Chapter 12.5 for further information. 12.2 Daisy Chain Capability The SPI of the TLD5542-1 provides daisy chain capability. In this configuration several devices are activated by the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see Figure 37), in order to build a chain. The end of the chain is connected to the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. Datasheet 55 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Figure 37 SO SPI SI SO SPI SCLK SI device 3 CSN SCLK MI MCSN MCLK SO SPI CSN SI CSN MO device 2 SCLK device 1 SPI_DaisyChain_1.emf Daisy Chain Configuration In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn HIGH (see Figure 38). MI MO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 MCSN MCLK SPI_DaisyChain_2.emf Figure 38 Datasheet Data Transfer in Daisy Chain Configuration 56 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12.3 Timing Diagrams t CS(lead) tCS (lag) tCS(td) tSCLK(P ) CSN 0.7VDD 0.2VDD tSCLK (H) tSCLK (L) 0.7VDD SCLK 0.2VDD tSI (s u) t SI (h) 0.7VDD SI 0.2VDD t SO(en) tSO(v ) tSO (dis) 0.7Vcc SO 0.2Vcc SPI _Timings.emf Figure 39 Datasheet Timing Diagram SPI Access 57 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12.4 Electrical Characteristics VIN = 8 V to 36 V, TJ = -40°C to +150°C, VDD= 3 V to 5.5 V, all voltages with respect to ground; (unless otherwise specified) Table 13 EC Serial Peripheral Interface (SPI) Parameter Symbol Values Min. Typ. Max. Unit Note or Number Test Condition Input Characteristics (CSN, SCLK, SI) - LOW level of pin CSN VCSN(L) 0 – 0.8 V – P_12.4.1 SCLK VSCLK(L) 0 – 0.8 V – P_12.4.2 SI VSI(L) 0 – 0.8 V – P_12.4.3 Input Characteristics (CSN, SCLK, SI) - HIGH level of pin CSN VCSN(H) 2 – VDD V – P_12.4.4 SCLK VSCLK(H) 2 – VDD V – P_12.4.5 SI VSI(H) 2 – VDD V – P_12.4.6 L-input pull-up current at CSN pin -ICSN(L) 31 63 94 μA VDD = 5 V; VCSN = 0.8 V; P_12.4.7 H-input pull-up current at CSN pin -ICSN(H) 22 45 67 μA VDD = 5 V; VCSN = 2 V; P_12.4.8 L-Input Pull-Down Current at Pin SCLK ISCLK(L) 6 12 18 μA VSCLK = 0.8 V; P_12.4.9 SI ISI(L) 6 12 18 μA VSI = 0.8 V; P_12.4.10 SCLK ISCLK(H) 15 30 45 μA VSCLK = 2 V; P_12.4.11 SI ISI(H) 15 30 45 μA VSI = 2 V; P_12.4.12 L level output voltage VSO(L) 0 – 0.4 V ISO = -2 mA; P_12.4.13 H level output voltage VSO(H) VDD 0.4 V – VDD V ISO = 2 mA; VDD = 5 V; P_12.4.14 Output tristate leakage current ISO(OFF) -1 – 1 μA VCSN = VDD; VSO = 0 V or VSO = VDD; P_12.4.15 Enable lead time (falling CSN to rising SCLK) tCSN(lead) 200 – – ns 1) P_12.4.17 Enable lag time (falling SCLK to rising CSN) tCSN(lag) 200 – – ns 1) P_12.4.18 Transfer delay time (rising CSN to tCSN(td) falling CSN) 250 – – ns 1) P_12.4.19 Output enable time (falling CSN to tSO(en) SO valid) – – 200 ns 1) P_12.4.20 H-Input Pull-Down Current at Pin Output Characteristics (SO) Timings Datasheet CL = 20 pF at SO pin; 58 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 13 EC Serial Peripheral Interface (SPI) (cont’d) Parameter Min. Typ. Max. Unit Note or Number Test Condition Output disable time (rising CSN to tSO(dis) SO tristate) – – 200 ns Serial clock frequency – Serial clock period Serial clock HIGH time Serial clock LOW time Symbol fSCLK tSCLK(P) tSCLK(H) tSCLK(L) Values 1) P_12.4.21 CL = 20 pF at SO pin; 200 75 75 – – – – 5 – – – MHz 1) P_12.4.22 ns 1) P_12.4.24 ns 1) P_12.4.25 ns 1) P_12.4.26 P_12.4.27 Data setup time (required time SI tSI(su) to falling SCLK) 20 – – ns 1) Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1) P_12.4.28 ns 1) P_12.4.29 Output data valid time with capacitive load tSO(v) – – 100 CL = 20 pF; 1) Not subject to production test, specified by design Datasheet 59 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12.5 SPI Protocol The relationship between SI and SO content during SPI communication is shown in Figure 40. The SI line represents the frame sent from the µC and the SO line is the answer provided by the TLD5542-1. The first SO response is the response from the previous command. SI frame A frame B frame C SO (previous response ) response to frame A response to frame B SPI_SI2SO.emf Figure 40 Relationship between SI and SO during SPI communication The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the µC. Although the biggest majority of commands and frames implemented in TLD5542-1 can be decoded without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission to decode TLD5542-1 response frame completely. More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows: SI write register A read register A (new command ) SO (previous response ) Standard diagnostic register A content SPI_RWseq.emf Figure 41 Register content sent back to µC There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received frame: • in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8 with a minimum of 16 bits), shown in Figure 42 • when TLD5542-1 logic supply comes out of an Undervoltage reset condition (VDD < VDD(UV) as shown in Figure 43 or EN/INUVLO < VEN/INUVLOth ) • in case of a read or write command for a “not used” or “reserved” register (in this case TLD5542-1 answers with Standard Diagnosis at the next SPI transmission) Datasheet 60 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) frame A (error in trans .) SI SO (new command) (previous response) Standard diag + TER SPI_SO_TER.emf Figure 42 TLD5542-1 response after an error in transmission VDD ≥ VDD(UV) SI SO Figure 43 Datasheet frame A frame B Standard diag + TER (SO = „Z“) frame C response to frame B TLD5542-1 response after coming out of Power-On reset at VDD 61 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12.6 SPI Registers Overview 15 Frame 14 13 12 11 10 9 8 W/R RB ADDR 7 6 5 4 3 2 1 0 Data Write Register in bank 0 SI 1 0 ADDR Data Read Register in bank 0 SI 0 0 ADDR x x x x x x x 0 x x x x x x x 1 Read Standard Diagnosis SI 0 x x x x x x x Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard diagnosis is LOW). A new command can be executed in the second frame. 12.6.1 Standard Diagnosis The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility routines. The bits UVLORST, TER, OUTOV, IVCCUVLO and SHRTLED are latched and automatically cleared after a STD diagnosis reading. A CLRLAT command resets the diagnostic Latched Flag TSD bit. The TSD bit is always latched and clearable only via explicit CLRLAT command. The STD bits which are real time status monitors or mirror of internal registers are not cleared after a STD diagnosis reading or via explicit CLRLAT command: • The STATE bits and TW are real time status flags • The bits EOMON, EOMFS and EOCAL are mirror of internal register • The SWRST_BSTUV bit is the logic OR of: 15 0 • latched SWRST flag after a DVCSTRL.SWRST command (clearable via STD Diagnosis reading ) • real time monitor of gate driver undervolage (VBSTx-VSWNx_UVth) 14 13 12 11 SWRST_ UVLO STATE BSTUV RST Datasheet 10 9 8 7 TER EO EOM EOC 0 MON FS AL 62 6 5 4 3 2 1 0 OUTOV IVCCU LED SHRT TSD VLO CUR LED TW Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Field Bits Type Description SWRST_BSTUV 14 r SWRST OR VBSTx-VSWNx_UVth Monitor 0B , no SWRST or undervoltage on the Gate Drivers occured 1B , there was at least one SWRST since last readout OR an undervoltage condition at the gate drivers is occurring UVLORST 13 r VDD OR VEN/INUVLO Undervoltage Monitor 0B , there was no VDD OR VEN/INUVLO undervoltage since last readout 1B , there was at least one VDD undervoltage OR VEN/INUVLO undervoltage condition since last readout STATE 12:11 r Operative State Monitor 00B , (reserved) 01B , Limp Home Mode 10B , Active Mode 11B , Idle Mode TER 10 r Transmission Error 0B , Previous transmission was successful (modulo 16 + n*8 clocks received, where n = 0, 1, 2...) 1B , Previous transmission failed or first transmission after reset EOMON 9 r End of LED/Input Current Monitor Routine Bit 0B , Current monitoring routine not completed, not successfully performed or never run. 1B , Current Monitor routine successfully performed (is reset to 0B when SOMON is set to 1B) EOMFS 8 r End of MFS Routine Bit 0B , MFS routine not completed, not successfully performed or never run. 1B , MFS routine successfully performed (is reset to 0B when SOMOFS is set to 1B) EOCAL 7 r End of Calibration Routine 0B , Calibration routine not completed, not successfully performed or never run. 1B , Calibration routine successfully performed (is reset to 0B when SOCAL is set to 1B) OUTOV 5 r Output overvoltage Monitor 0B , Output overvoltage not detected since last readout 1B , Output overvoltage was detected since last readout IVCCUVLO 4 r IVCC or IVCC_EXT Undervoltage Lockout Monitor 0B , IVCC and IVCC_EXT above VIVCC_RTH,d or VIVCC_EXT_RTH,d threshold since last readout 1B , Undervoltage on IVCC or IVCC_EXT occurred since last readout LEDCUR 3 r LED Current Flag (see LEDCUR pin description Chapter 10.5) 0B , LED current not detected 1B , LED current detected Datasheet 63 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Field Bits Type Description SHRTLED 2 r Shorted LED Diagnosis 0B , Short circuit condition not detected since last readout 1B , Short circuit condition detected since last readout TSD 1 r Over Temperature Shutdown 0B , Tj below temperature shutdown threshold 1B , Overtemperature condition detected since last readout TW 0 r Over Temperature Warning 0B , Tj below temperature warning threshold 1B , Tj exceeds temperature warning threshold Datasheet 64 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) 12.6.2 Register structure Table 15 describes in detail the available registers with their bit-fields function, size and position Table 14 shows register addresses and summarize bit-field position inside each register Table 14 Register Bank 0 Bit 15 14 13 12 11 1 9 8 0 Name W/ R R B ADDR 7 6 5 4 3 2 1 0 Data LEDCURR W/ 0 ADIM R 0 0 0 0 0 0 ADIMVAL LEDCURR W/ 0 CAL R 0 0 0 0 1 1 x DAC_ SOCAL EOCAL OFF CALIBVAL SWTMOD W/ 0 R 0 0 0 1 0 1 x DCM_ CCM4E VFB_VI EN VER N_OFF S2G_O ENSP FMSP FDEVSP FF READ READ READ DVCCTRL W/ 0 R 0 0 0 1 1 0 EA_IO EA_G SLOPE UT M MFSSETU W/ 0 P1 R 0 0 1 0 0 1 EA_IO ILIM_ SOMFS EOMFS LEDCHAIN UT_MF HALF S _MFS MFSSETU W/ 0 P2 R 0 0 1 0 1 0 MFSDLY CURRMON W/ 0 R 0 0 1 1 0 0 x x SOMO N REGUSET MON W/ 0 R 0 0 1 1 1 1 x x x MUXCTRL W/ 1 R 1 1 1 1 1 0 MFS_R AMUX SO_MUX_SEL EF _EN ENCAL CLRLA SWRS IDLE T T EOMON INCURR REGUMODFB LEDCURR BB_BST_CMP A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis Frame is send out. Datasheet 65 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 15 Register description Register name Field Bits Type Purpose LEDCURRADIM ADIMVAL 7:0 r/w LED Current Configuration Register 00000000B, analog dimming @ 0% of LED current fixed via RFB 11110000B, (default) analog dimming @ 100% of LED current fixed via RFB LEDCURRCAL CALIBVAL 3:0 r/w LED Current Accuracy Trimming Configuration Register LED current calibration value definition, the first bit is the calibration sign: 0000B, (default) Initial state in the middle of the range 0111B, maximum calibration value positive 1111B, maximum calibration value negative EOCAL 4 r End of calibration routine signalling bit: 0B , (default) calibration routine not completed, not successfully performed or never run. 1B , calibration successfully performed (is reset to 0B when SOCAL is set to 1B) SOCAL 5 r/w Start of calibration routine signalling bit: 0B , (default) no calibration routine started 1B , calibration routine start (autoclear) DAC_OFF 6 r/w Switch OFF internal analog dimming DAC bit: 0B , (default) internal DAC active 1B , internal DAC inactive and analog dimming error amplifier mapped to SET pin Datasheet 66 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 15 Register description (cont’d) Register name Field Bits Type Purpose SWTMOD FDEVSPREAD 0 r/w Switching Mode Configuration Register Deviation Frequency fDEV definition: 0B , (default) ±16% of fSW 1B , ±8% of fSW FMSPREAD 1 r/w Frequency Modulation Frequency fFM definition: 0B , (default) 12 kHz 1B , 18 kHz ENSPREAD 2 r/w Enable Spread Spectrum feature: 0B , (default) Spread Spectrum modulation disabled 1B , Spread Spectrum modulation enabled S2G_OFF 3 r/w Short to GND protection enable Bit 0B , (default) Short to ground protection enabled 1B , Short to ground protection disabled VFB_VIN_OFF 4 r/w Vin Feedback Enable on VFB_VIN pin 0B , (default) Enable Vin Feedback 1B , Disable Vin Feedback CCM_4EVER 5 r/w Forced Continuous Conduction Mode 0B , (default) Forced CCM after soft start finish 1B , Forced CCM even during soft start ramp up DCM_EN 6 r/w Enable Bit to allow DCM regulation (MOSFET M4 control) 0B , (default) DCM is disabled (M4 alternately switching), 1B , DCM is enabled (M4 is permanently OFF) Datasheet 67 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 15 Register description (cont’d) Register name Field Bits Type Purpose DVCCTRL IDLE 0 r/w Device Control Register IDLE mode configuration bit: 0B , ACTIVE mode (default) 1B , IDLE mode SWRST 1 r/w Software reset bit: 0B , (default) normal operation 1B , execute reset command CLRLAT 2 r/w Clear Latch bit: 0B , (default) normal operation 1B , execute CLRLAT command ENCAL 3 r/w Enable automatic output current calibration bit: 0B , (default) DAC takes CALIBVAL from SPI registers 1B , DAC takes CALIBVAL from last completed automatic calibration procedure; SOCAL Bit can be set. SLOPE 5:4 r/w slope compensation strenght: 00B , (default) Nominal 01B , +25% 10B , -50% 11B , -25% EA_GM 6 r/w Increase the gain of the error amplifier, active only when output current is below 80% of target (i.e. < VFBH_FBL_EA ): 0B , (default) inactive 1B , IFBxgm boosted to 1420µS EA_IOUT 7 r/w Bit to decrease the saturation current of the error amplifier in current mode control loop: 0B , (default) inactive 1B , active: error amplifier saturation current reduced to 10uA Datasheet 68 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 15 Register description (cont’d) Register name Field Bits Type Purpose MFSSETUP1 LEDCHAIN 3:0 r/w Multifloat Switch configuration Register MFS ratio bits: set MFS jump ratio 0001B, smallest Value 1 Step 0010B, 2 Steps 1000B, (default) 8 Steps 1111B, 15 Steps 0000B, largest Value 16 Steps EOMFS 4 r End of MFS routine bit: 0B , (default) MFS routine not completed, not successfully performed or never run. 1B , MFS routine successfully performed (is reset to 0B when SOMFS is set to 1B). SOMFS 5 r/w Start of MFS routine bit: 0B , (default) MFS routine not activated 1B , MFS routine activated ILIM_HALF 6 r/w Bit to decrease the Switch Current Limit (ISwLim) during F.D. operation: 0B , (default)inactive ISwLim = 2/3of default value 1B , ISwLim reduced to 1/2of default value EA_IOUT_MFS 7 r/w Bit to decrease the saturation current of the error amplifier (A6) in current mode control loop only during MFS routine: 0B , (default) inactive 1B , active: error amplifier current reduced to 20% MFSDLY 7:0 r/w Multifloatswitch configuration register 2 (delay time programming) 00000000B, smallest delay time in respect to fSW 11111111B, largest delay time in respect to fSW 10000000B, (default) delay time in respect to fSW MFSSETUP2 Datasheet 69 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Serial Peripheral Interface (SPI) Table 15 Register description (cont’d) Register name Field Bits Type Purpose CURRMON LEDCURR 1:0 r Current Monitor Register Status of the LED Current bits: 00B , (default) LED current between Target and +25% 01B , LED current above +25% of Target 10B , LED current between Target and -25% 11B , LED current below -25% of Target INCURR 3:2 r Status of the Input Current bits: 00B , (default) Input current between 75% and 90% of Limit 01B , Input current between 90% and the Limit 10B , Input current between 60% and 75% of Limit 11B , Input current below 60% of Limit EOMON 4 r End of LED/Input Current Monitoring bit: 0B , (default) Current monitoring routine not completed, not successfully performed or never run. 1B , Current Monitor routine successfully performed (is reset to 0B when SOMON is set to 1B) SOMON 5 r/w Start of LED/Input Current Monitoring bit: 0B , (default) Current monitor routine not started 1B , Start of the current monitor routine REGUMODFB 3:2 r Regulation Setup And Monitor Register Feedback of Regulation Mode bits: 01B , (default) Buck 10B , Boost 11B , Buck-Boost BB_BST_CMP 1:0 r/w Buck boost to Boost transition compensation level: 00B , (default) Min compensation: useful when low switching frequencies are selected 01B , Low compensation: I.E. adopted @fSW=250kHz 10B , Mid compensation: I.E. adopted @fSW=400kHz 11B , Max compensation: useful when high switching frequencies are selected I.E. @fSW=500kHz SO_MUX_SEL 5:0 r/w Internal Muxes Configuration Register Digital Multiplexer selector, output on SO pin: 000000B, (default) SO pin configured as normal SPI output 000100B, as default with in addition internal oscillator clock available when CS_N is high AMUX_EN 6 r/w Analog Mux enable, output on FILT pin: 0B , (default) Analog Mux disabled 1B , Analog Mux enabled MFS_REF 7 r/w MFS reference to FILT pin Path Enable: 0B , (default) path disabled 1B , Path Enabled REGUSETMON MUXCTRL Datasheet 70 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Application Information 13 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VIN CIN2 CIN1 ADC BST1 BST2 VFB_VIN HSGD1 EN/INUVLO DIM_HALF M1 ADC RCOMP CSOFT_START RPU1 Micro controller RPU2 VDD RFREQ I/O I/O I/O VDD FREQ VOUT DRL FBL IOUTMON AGND High Beam CFILT2 M5 ADC RVFBL4 GND M7 Low Beam SGND PGND1 PGND2 LSGD2 SWN2 HSGD2 VFB FBH RVFBH4 CFILT1 FILT VSS RSPI4 DIM_HALF CSN SI SO SCLK M6 SWCS SOFT_START VDD RSPI2 RSPI3 SPI SPI M3 LSGD1 PWMI EOMFS LEDCUR RSPI1 LOUT M2 COMP M4 COUT1 RSWCS CCOMP VOUT RFB CBST1 CBST2 SWN1 I/O D2 D1 RVFBH RVFBL2 VDD IIN1 RVFBL3 VDD CIVCC IVCC RVFBL RVFBH2 RVFBH3 VIN IVCC_ext VIN IIN2 I/Os Figure 44 Application Drawing - TLD5542-1 on a 3 functions LED Driver Module Table 16 BOM - TLD5542-1 as current regulator (IOUT = 1 A, fSW = 300 kHz) Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- BAT46WJ Diode CIN1 10 µF, 50 V TDK X7R Capacitor CIN2 4.7 µF, 50 V TDK X7R Capacitor CFILT1,2 220 pF, 10 V TDK X7R Capacitor CCOMP 15 nF, 16 V TDK X7R Capacitor CSOFT_START 15 nF, 16 V TDK X7R Capacitor COUT1 3x3.3 µF, 100 V TDK X7R Capacitor CIVCC 10 µF, 16 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5542-1 IC LOUT 10 µH TDK SPM10065VT-100M Inductor RFB 0.100 Ω, 1% Panasonic -- Resistor R1 , R2 , R3 , RPD , REN , RPWMI xx kΩ, 1% , RSense1 , RSense2 , RSYNC , RSCLK , RSI , RSO , RCSN Panasonic -- Resistor RVFBL , RVFBH 1k5Ω, 51kΩ, 1% Panasonic -- Resistor RVFBL2 , RVFBH2 1kΩ, 51kΩ, 1% Panasonic -- Resistor Datasheet 71 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Application Information BOM - TLD5542-1 as current regulator (IOUT = 1 A, fSW = 300 kHz) Table 16 Reference Designator Value Manufacturer Part Number Type RCOMP 1k Ω, 1% Panasonic -- Resistor RFREQ 24 kΩ, 1% Panasonic -- Resistor RSWCS 0.007 Ω, 1% Panasonic ERJB1CFR05U Resistor Infineon IPG20N10S4L-26 Transistor M1 , M2 , M3 , M4, M5, M6, M7 Dual MOSFET: 60V / 26 mΩ N-ch VBAT MRP DTVS Rgate Voltage Regulator CIN2 RIIN CIN1 IVCC VFB_VIN IIN1 SET EN/INUVLO HSGD1 CCOMP SOFT_START I/O VDD CSN SI SO SCLK RSI RSO RSCLK SGND PGND1 PGND2 LSGD2 SWN2 HSGD2 VFB FBH VSS DIM_HALF SYNC AGND LHI VDD RCSN VOUT SWCS FREQ PWMI IINMON IOUTMON RPWMI M3 COUT3 CFF RFF RFREQ RSENSE LOUT LSGD1 COMP M4 COUT1 RSWCS CSOFT_START Micro controller GND M1 CBST1 CBST2 M2 RCOMP SPI SPI COUT2 SWN1 I/O D2 D1 BST1 BST2 VDD I/O A/D CIVCC IVCC_ext VIN IIN2 RVFBH GND Alternative external VREG supply RVFBL VS RFB1 OUT RFB2 CVREG_OUT FBL Figure 45 Application Drawing - TLD5542-1 as adjustable voltage regulator Table 17 BOM - TLD5542-1 as voltage regulator Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- BAT46WJ Diode CIN1 1 µF, 100 V TDK X7R Capacitor CIN2 4.7 µF, 100 V TDK X7R Capacitor CCOMP 22 nF, 16 V TDK X7R Capacitor CFF 10 nF, 50 V TDK X7R Capacitor CSOFT_START 22 nF, 16 V TDK X7R Capacitor COUT1 3x4.7 µF, 100 V TDK X7R Capacitor COUT2 , COUT3 100 nF, 100 V TDK X7R Capacitor CIVCC 10 µF, 16 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5542-1 IC Datasheet 72 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Application Information Table 17 BOM - TLD5542-1 as voltage regulator Reference Designator Value Manufacturer Part Number Type LOUT 10 µH Coilcraft XAL1010-103MEC Inductor RFF 1.5 kΩ, 1% Panasonic -- Resistor RFB1 , RFB2 150Ω, 20.5kΩ, 1% Panasonic -- Resistor RIN 0.005 Ω, 1% Panasonic -- Resistor RPWMI , RSense1 , RSense2 , RSYNC , RSCLK , RSI , RSO , RCSN xx kΩ, 1% Panasonic -- Resistor RVFBL , RVFBH 1.5 kΩ, 24 kΩ, 1% Panasonic -- Resistor RCOMP 0 Ω, 1% Panasonic -- Resistor RFREQ 37.4 kΩ, 1% Panasonic -- Resistor RSWCS 0.007 Ω, 2% -- -- Resistor M1 , M2 , M3 , M4 Dual MOSFET: 100 V / 35 mΩ N-ch Infineon IPG20N10S4L-35 Transistor Datasheet 73 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Application Information 13.1 Further Application Information Typical Performance Characteristics of Device d:сϮϱΣ͕s/EсϭϮsƵŶůĞƐƐŽƚŚĞƌǁŝƐĞƐƉĞĐŝĨŝĞĚ /ssŽůƚĂŐĞǀƐdĞŵƉĞƌĂƚƵƌĞ /sƌŽƉŽƵƚǀƐƵƌƌĞŶƚ ϱ͕ϮϬ Ϯ͕ϱ ϱ͕ϭϱ Ϯ //sсϭϬŵ ϱ͕ϭϬ ϭ͕ϱ ϱ͕Ϭϱ dũсϭϱϬΣ s/s ΀s΁ s/EͲs/s ΀s΁ dũсͲϰϬΣ dũсϮϱΣ ϭ ϱ͕ϬϬ ϰ͕ϵϱ ϰ͕ϵϬ Ϭ͕ϱ ϰ͕ϴϱ Ϭ Ϭ ϭϬ ϮϬ ϯϬ ϰϬ ϰ͕ϴϬ ϱϬ ͲϰϬ ϭϬ ϲϬ >KĐƵƌƌĞŶƚ΀ŵ΁ /s>ŽĂĚƌĞŐƵůĂƚŝŽŶ s&,Ͳ&>ͺZ&dŚƌĞƐŚŽůĚǀƐs&, ϭϱϰ ϱ͕ϭϱ ϭϱϯ ϱ͕ϭ ϭϱϮ s&,Ͳ&>ͺZ&΀ŵs΁ ϱ͕Ϯ s/s ΀s΁ ϱ͕Ϭϱ ϱ ϰ͕ϵϱ ϭϱϬ ϭϰϵ ϭϰϴ ϰ͕ϴϱ ϭϰϳ Ϭ ϭϬ ϮϬ ϯϬ ϰϬ ϭϰϲ ϱϬ ŶĂůŽŐŝŵ͘сϭϬϬй ϭϱϭ ϰ͕ϵ ϰ͕ϴ Ϭ ϭϬ ϮϬ //s΀ŵ΁ s&,Ͳ&>ͺZ&dŚƌĞƐŚŽůĚǀƐdĞŵƉ ϲϬ ϭ͕ϰϯ ŶĂůŽŐŝŵ͘сϭϬϬй͕&,сϭϮs ϭ͕ϰϮ ŶĂůŽŐŝŵ͘сϭϬϬй͕&,сϲϬs ϭϱϭ s/KhdDKE ΀s΁ s&,Ͳ&>ͺZ&΀ŵs΁ ϱϬ /KhdDKEsŽůƚĂŐĞǀƐdĞŵƉ ŶĂůŽŐŝŵ͘сϭϬϬй͕&,сϬ͕ϭϱs ϭϱϮ ϭϱϬ ϭϰϵ s;&,Ͳ&>Ϳ сϭϱϬŵs ϭ͕ϰϭ ϭ͕ϰ ϭ͕ϯϵ ϭϰϴ ϭ͕ϯϴ ϭϰϳ ϭ͕ϯϳ ϭ͕ϯϲ ͲϰϬ ϭϬ ϲϬ ͲϰϬ ϭϭϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ Datasheet ϰϬ ϭ͕ϰϰ ϭϱϯ Figure 46 ϯϬ s&,΀s΁ ϭϱϰ ϭϰϲ ϭϭϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ ϭϬ ϲϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ ϭϭϬ Characterization Diagrams 1 74 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Application Information d:сϮϱΣ͕s/EсϭϮsƵŶůĞƐƐŽƚŚĞƌǁŝƐĞƐƉĞĐŝĨŝĞĚ /KhdDKEsŽůƚĂŐĞǀƐs;&,Ͳ&>Ϳ >hZƚŚƌĞƐŚ͘ǀƐĂŶĂůŽŐĚŝŵŵŝŶŐ ϴϬ ϭ͕Ϯ ϳϬ Ŭ>ͺ/E͕Ŭ>ͺ΀й΁ ϭ͕ϰ s/KhdDKE ΀s΁ ϭ Ϭ͕ϴ Ϭ͕ϲ Ϭ͕ϰ Ϭ͕Ϯ Ϭ ϲϬ ϱϬ ϰϬ ϯϬ Ŭ>ͺ/E ϮϬ Ŭ>ͺ ϭϬ Ϭ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ ϭϰϬ Ϭ ϮϬ ϰϬ ϭϮϬ ϭ͕Ϭϯ /ͺ&>΀Ƶ΁ /ͺ&,΀Ƶ΁ ϴϬ s;//EϭͲ//EϮͿ сϱϬŵs ϭ͕ϬϮ s;&,Ͳ&>Ϳ сϭϱϬŵs ϲϬ ϭ͕Ϭϭ s//EDKE ΀s΁ /&, ΀Ƶ΁͕/&> ΀Ƶ΁ ϭϬϬ ϭ͕Ϭϰ ϭϬϬ ϰϬ ϭ ϮϬ Ϭ͕ϵϵ Ϭ Ϭ͕ϵϴ ͲϮϬ Ϭ͕ϵϳ Ϭ ϱ ϭϬ ϭϱ ϮϬ Ϯϱ ϯϬ ϯϱ ϰϬ ϰϱ ϱϬ ϱϱ Ϭ͕ϵϲ ϲϬ ͲϰϬ ϭϬ s&,΀s΁ ϲϬ ϭϭϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ KƐĐŝůůĂƚŽƌ&ƌĞƋƵĞŶĐLJǀƐdĞŵƉ s;^ddžͲ^tEdžͿǀƐdĞŵƉ ϴϬϬ ϰ ϯ͕ϵ ϳϬϬ ϯ͕ϴ Zͺ&ZYсϲϭ͘ϵŬKŚŵ ϲϬϬ s;^ddžͲ^tEdžͿ ΀s΁ ϱϬϬ s/E сϭϮs s;&,Ͳ&>Ϳ сϭϱϬŵs ϯ͕ϳ Zͺ&ZYсϯϳ͘ϰŬKŚŵ Ĩ^t ΀Ŭ,nj΁ ϴϬ //EDKEsŽůƚĂŐĞǀƐdĞŵƉ /&, ͕/&> ǀƐs&, ͲϰϬ ϲϬ ŶĂůŽŐĚŝŵŵŝŶŐ΀й΁ s;&,Ͳ&>Ϳ ΀ŵs΁ Zͺ&ZYсϭϮ͘ϳŬKŚŵ ϰϬϬ ϯ͕ϲ s^ddžͲs^tEdžͺĚĞĐ΀s΁ ϯ͕ϱ s^ddžͲs^tEdžͺŝŶĐ΀s΁ ϯ͕ϰ ϯϬϬ ϯ͕ϯ ϮϬϬ ϭϬϬ ϯ͕Ϯ ͲϰϬ ϭϬ ϲϬ ϯ͕ϭ ϭϭϬ ͲϰϬ ϭϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ Figure 47 • ϲϬ ϭϭϬ dĞŵƉĞƌĂƚƵƌĞ΀Σ΁ Characterization Diagrams 2 For further information you may contact http://www.infineon.com/ Datasheet 75 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Package Outlines Package Outlines 6.8 11 x 0.5 = 5.5 0.1±0.03 B +0.03 1) 3 1 0. 0.4 x 45° Index Marking C Datasheet 26 36 25 48 13 (0 (0.2) 0.05 MAX. 2) 37 1 12 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 48 ± 0.5 0. 24 0.15 ±0.05 0.1 ±0.05 SEATING PLANE 7 ±0.1 48x 0.08 6.8 5 0 0. 0.5 ±0.07 A (6) 7 ±0.1 0.9 MAX. (0.65) (5.2) 14 .35 ) 0.23 ±0.05 (5.2) Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 PG-VQFN-48 (with LTI) 76 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface 9 7 BOTTOMVIEW D 2) 5 EXPOSEDDIEPAD 5 9 7 1) 2) B 48 INDEXMARKING 1 0.5 0.25 0.08 C 48x COPLANARITY 0.2 A-B D H 4x A 0°..7 ° 0.6±0.15 GAUGE PLANE +0.0 C SEATING PLANE 0.2 A-B D 48x 1) 75 0.125 -0.035 H 0.1 ± 0.05 STAND OFF 1 ±0.05 1.2 MAX. Package Outlines 1 0.22±0.05 0.08 48 A-B D C 48x 1)DOESNOTINCLUDEPLASTICORMETALPROTRUSIONOF 0.25MAX.PERSIDE 2)EXPOSEDPADFORSOLDERINGPURPOSE Figure 49 PG-TQFP-48 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Datasheet 77 Dimensions in mm Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Revision History 15 Revision History Table 18 Revision History Revision Date Changes Rev. 1.0 2019-11-21 Released datasheet Rev. 1.10 2019-12-11 changed ESD in to “CDM” AECQ100-011 including revision : Rev. D Rev. 1.10 2019-12-11 Updated Vout Overvoltage description Chapter 10.2 Datasheet 78 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface Table of Content 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3.1 3.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 4.1 4.2 4.3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 5.1 5.2 5.3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.5 6.6 6.7 Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Boost mode (VIN < VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Buck mode (VIN > VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Buck-Boost mode (VIN ~ VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fast Output Discharge Operation Mode - Multi Floating Switches Topology . . . . . . . . . . . . . . . . . . . . 25 Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 7.1 7.2 Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 8.1 8.2 8.3 Analog Dimming and Limp Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 9.1 9.2 Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 10.1 10.2 10.2.1 10.2.2 10.3 10.4 10.5 10.6 10.7 Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output Overvoltage, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Input voltage monitoring, protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Input current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 Infineon FLAT SPECTRUM Feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Datasheet 79 Rev. 1.10 2019-12-11 TLD5542-1 H-Bridge DC/DC Controller with SPI Interface 11.1 11.2 11.3 11.4 11.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 12.1 12.2 12.3 12.4 12.5 12.6 12.6.1 12.6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13 13.1 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table of Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Datasheet 80 Rev. 1.10 2019-12-11 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-12-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2019 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference TLD5542-1 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.