TLE8110EDXUMA1

TLE8110ED Smart Multichannel Low Si de Switch with Parallel Contr ol and SPI Interface 1 Overview Features • Overvoltage, Overtemperature, ESD-Protection • Direct Parallel PWM Control of all Channels • safeCOMMUNICATION (SPI and Parallel) • Efficient Communication Mode: compactCONTROL • Compatible with 3.3V- and 5V- Micro Controllers I/O ports • clampSAFE for highly efficient parallel use of the channels • Green Product • AEC Qualified Potential applications • Power Switch Automotive and Industrial Systems switching Solenoids, Relays and Resistive Loads Product validation Qualified for Automotive Applications. Product Validation according to AEC-Q100/101. Description 10-channel Low-Side Switch in Smart Power Technology [SPT] with Serial Peripheral Interface [SPI] and 10 open drain DMOS output stages. The TLE8110ED is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via Parallel Input Pins for PWM use or SPI Interface. The TLE8110ED is particularly suitable for Engine Management and Powertrain Systems. Type Package Marking TLE8110ED PG-DSO-36-72 TLE8110ED Data Sheet www.infineon.com 1 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Overview Table 1 Product Summary Parameter Symbol Value Unit Analogue Suppy Voltage VDD 4.50 ... 5.50 V Digital Supply Voltage VCC 3.00 ... 5.50 V VDS(CL)typ 55 V RON1-4 0.30 Ω RON5-6 0.25 Ω RON7-10 0.60 Ω RON1-4 0.60 Ω RON5-6 0.50 Ω RON7-10 1.20 Ω Nominal Output current (CH 1-4) IDnom 1.50 A Nominal Output current (CH 5-6) IDnom 1.70 A Nominal Output current (CH 7-10) IDnom 0.75 A Output Current Shut-down Threshold (CH 1-4) min. IDSD(low) 2.60 A Output Current Shut-down Threshold (CH 5-6) min. IDSD(low) 3.70 A Output Current Shut-down Threshold (CH 7-10) min. IDSD(low) 1.70 A Clamping Voltage (CH 1-10) o On Resistance maximum at Tj = 25 C and IDnom o On Resistance maximum at T j = 150 C and IDnom V Batt VDD = typ. 5V Supply IC VCC = typ. 3.3….5V RST Micro I/O Controller I/O I/O SPI_SI SPI _SO SPI_CLK SPI _CS EN TLE8110 OUT1 IN1 OUT10 IN10 4 to 6 Injectors or Solenoids General purpose Channels in parallel connection General purpose Channels for Relays SPI_SO SPI_SI SPI_CLK SPI_CS Appl _Diag_10ch_TLE8110 .vsd Figure 1 Data Sheet Block Diagram TLE8110ED 2 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 5.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Description Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 6.1 6.2 Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Description Reset and Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical Characteristics Reset Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 7.1 7.2 7.3 7.4 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of the Clamping Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Connection of the Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 19 21 25 8 8.1 8.1.1 8.1.2 8.2 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnosis Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Load diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent / Overtemperature diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 29 30 9 9.1 9.2 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Description Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Electrical Characteristics Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 10.1 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Electrical Characteristics Overload Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 11.1 11.2 11.3 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics 16 bit SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 40 12 12.1 12.2 12.2.1 12.2.2 12.2.3 Control of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface. Signals and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description 16 bit SPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 42 43 43 Data Sheet 3 7 7 7 9 10 10 11 12 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface 12.2.3.1 16-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3.2 2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3.3 16- and 2x8-bit protocol mixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3.4 Daisy-Chain and 2x8-bit protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 safeCOMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4.1 Encoding of the commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4.2 Modulo-8 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Register and Command - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 CMD - Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.1 CMD_RSD - Command: Return Short Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.2 CMD_RSDS - Command: Return Short Diagnosis and Device Status . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.3 CMD_RPC - Command: Return Pattern Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1.4 CMD_RINx - Command: Return Input Pin (INx) - Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 DCC - Diagnosis Registers and compactCONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2.1 DRx - Diagnosis Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2.2 DRx - Return on DRx Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2.3 DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.3 OUTx - Output Control Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.4 ISx - INPUT or Serial Mode Control Register, Bank A and Bank B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.5 PMx - Parallel Mode Register CHx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.6 DEVS - Device Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 45 46 47 48 48 48 49 52 53 54 56 57 60 63 64 65 68 69 70 71 13 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data Sheet 4 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Block Diagram 2 Block Diagram RST VDD IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 Input Control (TTL or CMOS) EN analogue control, diagnostic and protective functions input register S_CS S_CLK SPI (TTL or CMOS) S_SI S_ SO diagnosis register control register VCC Logic control unit OUT1 OUT2 temperature sensor OUT3 OUT4 short circuit detection OUT5 gate control OUT7 open load detection OUT9 OUT6 OUT8 OUT10 short to GND detection GND Figure 2 2.1 Block_diag_10ch_TLE8110.vsd Block Diagram Description Communication The TLE8110ED is a 10-channel low-side switch in PG-DSO-36-72 package providing embedded protection functions. The 16-bit serial peripheral interface (SPI) can be utilized for control and diagnosis of the device and the loads. The SPI interface provides daisy-chain capability in order to assemble multiple devices in one SPI chain by using the same number of micro-controller pins 1). The analogue and the digital part of the device is supplied by 5V. Logic Input and Output Signals are then compatible to 5V logic level [TTL - level]. Optionally, the logic part can be supplied with lower voltages to achieve signal compatibility with e.g. 3.3V logic level [CMOS - level]. The TLE8110ED is equipped with 10 parallel input pins that are routed to each output channel. This allows control of the channels for loads driven by Pulse Width Modulation (PWM). The output channels can also be controlled by SPI. Reset The device is equipped with one Reset Pin and one Enable. Reset [RST] serves the whole device, Enable [EN] serves only the Output Control Unit and the Power Stages. 1) Daisy Chain Data Sheet 5 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Block Diagram Diagnosis The device provides diagnosis of the load, including open load, short to GND as well as short circuit to VBatt detection and over-load/ over-temperature indication. The SPI diagnosis flags indicates if latched fault conditions may have occurred. Protection Each output stage is protected against short circuit. In case of over load, the affected channel is switched off. The switching off reaction time is dependent on two switching thresholds. Restart of the channel is done by clearing the Diagnosis Register 1). This feature protects the device against uncontrolled repetitive short circuits. There is a temperature sensor available for each channel to protect the device in case of over temperature. In case of over temperature the affected channel is switched off and the Over-Temperature Flag is set. Restart of the channel is done by deleting the Flag. This feature protects the device against uncontrolled temperature toggling. Parallel Connection of Channels The device is featured with a central clamping structure, so-called CLAMPsafe. This feature ensures a balanced clamping between the channels and allows in case of parallel connection of channels a high efficient usage of the channel capabilities. This parallel mode is additionally featured by best possible parameter- and thermal matching of the channels and by controlling the channels accordingly. 1) Restart after Clear Data Sheet 6 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Pin Configuration 3 Pin Configuration 3.1 Pin Assignment Figure 3 3.2 1 GND GND 36 2 P_IN1 OUT7 35 3 P_IN2 OUT8 34 4 EN N.C. 33 5 RST GND 32 6 P_IN3 OUT5 31 7 P_IN4 OUT1 30 8 VDD OUT2 29 9 P_IN5 P_IN10 28 Exposed Pad (back-side) 10 VCC P_IN9 27 11 S_SO OUT3 26 12 S_CLK OUT4 25 13 S_CS OUT6 24 14 S_SI GND 23 15 P_IN6 N.C. 22 16 P_IN7 OUT10 21 17 P_IN8 OUT9 20 18 GND GND 19 Pin Configuration Pin Definitions and Functions Pin Symbol Function 1 GND Ground 2 P_IN1 Parallel Input Pin 1. Default assignment to Output Channel 1 3 P_IN2 Parallel Input Pin 2. Default assignment to Output Channel 2 4 EN Enable Input Pin. If not needed, connect with Pull-up resistor to VCC 5 RST Reset Input Pin (active low). If not needed, connect with Pull-up resistor to VCC 6 P_IN3 Parallel Input Pin 3. Default assignment to Output Channel 3 7 P_IN4 Parallel Input Pin 4. Default assignment to Output Channel 4 8 VDD Analogue Supply Voltage 9 P_IN5 Parallel Input Pin 5. Default assignment to Output Channel 5 10 VCC Digital Supply Voltage 11 S_SO Serial Peripheral Interface [SPI], Serial Output 12 S_CLK Serial Peripheral Interface [SPI], Clock Input 13 S_CS Serial Peripheral Interface [SPI], Chip Select (active low) 14 S_SI Serial Peripheral Interface [SPI], Serial Input 15 P_IN6 Parallel Input Pin 6. Default assignment to Output Channel 6 Data Sheet 7 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Pin Configuration Pin Symbol Function 16 P_IN7 Parallel Input Pin 7. Default assignment to Output Channel 7 17 P_IN8 Parallel Input Pin 8. Default assignment to Output Channel 8 18 GND Ground 19 GND Ground 20 OUT9 Drain of Power Transistor Channel 9 21 OUT10 Drain of Power Transistor Channel 10 22 N.C. internally not connected, connect to Ground 23 GND Ground 24 OUT6 Drain of Power Transistor Channel 6 25 OUT4 Drain of Power Transistor Channel 4 26 OUT3 Drain of Power Transistor Channel 3 27 P_IN9 Parallel Input Pin 9. Default assignment to Output Channel 9 28 P_IN10 Parallel Input Pin 10. Default assignment to Output Channel 10 29 OUT2 Drain of Power Transistor Channel 2 30 OUT1 Drain of Power Transistor Channel 1 31 OUT5 Drain of Power Transistor Channel 5 32 GND Ground 33 N.C. internally not connected, connect to Ground 34 OUT8 Drain of Power Transistor Channel 8 35 OUT7 Drain of Power Transistor Channel 7 36 GND Ground Exposed Pad Note: Data Sheet internally not connected, connect to Ground The exposed pad of TLE8110ED is not connected to ground pins internally. It is highly recommended to connect the exposed pad to GND pins on the PCB. 8 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Pin Configuration 3.3 Terms VBatt PG-DSO-36 IP_IN1 VP_IN1 IP_IN 2 VP _IN2 IEN VEN IRST VRST IP_IN 3 V P_IN3 IP_IN 4 V P_IN4 IVDD V VDD I P_IN5 V P_IN5 IVCC V VCC IS _SO VS _SO IS_CLK VS _CLK IS _CS VS_CS VS_SI V P_IN6 V P_IN7 IS _SI IP_IN6 IP_IN7 IP_IN8 VP_IN 8 1 GND GND 36 I OUT7 2 P_IN1 OUT7 35 I OUT8 3 P_IN2 4 EN 5 RST 6 P_IN3 7 P_IN4 8 VDD 9 10 OUT8 34 N.C. 33 GND 32 OUT5 31 IOUT1 OUT1 30 IOUT2 OUT2 29 Exposed P_IN5 P_IN10 Pad (back-side) VCC P_IN9 28 27 11 S_SO OUT3 26 12 S_CLK OUT4 25 VOUT7 VOUT8 I OUT5 V OUT5 VOUT1 VOUT2 IP_IN10 V P_IN10 I P_IN9 VP_IN9 IOUT3 VOUT3 IOUT4 V OUT4 I OUT6 13 S_CS OUT6 24 14 S_SI GND 23 15 P_IN6 N.C. 22 IOUT10 16 P_IN7 OUT10 21 I OUT9 17 P_IN8 OUT9 20 18 GND GND 19 V OUT6 VOUT10 VOUT9 Top View Terms_TLE8110 .vsd Figure 4 Data Sheet Terms 9 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 2 Absolute Maximum Ratings 1) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Supply Voltages Digital Supply voltage VCC -0.3 – 5.5 V permanent P_4.1.1 Digital Supply voltage VCC -0.3 – 6.2 V t < 10s P_4.1.2 Analogue Supply voltage VDD -0.3 – 5.5 V permanent P_4.1.3 Analogue Supply voltage VDD -0.3 – 6.2 V t < 10s P_4.1.4 Load Current (CH 1 to 10) IDn – – IDSD(low) A – P_4.1.5 Reverse Current Output (CH 1- 10) IDn -IDSD(low) – - A – P_4.1.6 Total Ground Current IGND -20 – 20 A – P_4.1.7 Continuous Drain Source Voltage (Channel 1 to 10) VDSn -0.3 – 45 V – P_4.1.8 maximum Voltage for short circuit protection on Output VDSn – – 24 V one event on one single channel P_4.1.9 Single Clamping Energy Channel Group 1-4 EAS – – 29 mJ ID = 2.6A, 1 single pulse P_4.1.10 Single Clamping Energy Channel Group 5-6 EAS – – 31 mJ ID = 3.7A, 1 single pulse P_4.1.11 Single Clamping Energy Channel Group 7-10 EAS – – 11 mJ ID = 1.7A, 1 single pulse P_4.1.12 Input Voltage at all Logic Pin Vx -0.3 – 5.5 V permanent P_4.1.13 Input Voltage at all Logic Pin Vx -0.3 – 6.2 V t < 10s P_4.1.14 Input Voltage at Pin 27, 28 (IN9, 10) Vx -0.3 – 45 V permanent P_4.1.15 -40 – 150 o – P_4.1.16 max. 100hrs cumulative P_4.1.17 – P_4.1.18 Power Stages Clamping Energy - Single Pulse 2) 3) Logic Pins (SPI, INn, EN, RST) Temperatures Junction Temperature Tj C Junction Temperature Tj -40 – 175 o Storage Temperature Tstg -55 – 150 o C C ESD Robustness Data Sheet 10 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface General Product Characteristics Table 2 Absolute Maximum Ratings 1) (cont’d) Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Electro Static Discharge Voltage “Human Body Model - HBM” VESD -4 – 4 kV All Pins HBM, 4) 1.5KOhm, 100pF P_4.1.19 Electro Static Discharge Voltage “Charged Device Model - CDM” VESD -500 – 500 V All Pins CDM 5) P_4.1.20 Electro Static Discharge Voltage “Charged Device Model - CDM” VESD -750 – 750 V Pin 1, 18, 19, 36 (corner pins) CDM 5) P_4.1.21 1) 2) 3) 4) 5) Not subject to production test, specified by design. One single channel per time. Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse. ESD susceptibility, HBM according to EIA/JESD 22-A114-B. ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101-C. Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Table 3 Functional Range Functional Range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltages Analogue Supply Voltage VDD 4.5 – 5.5 V – P_4.2.1 Digital Supply Voltage VCC 3 – VDD V – P_4.2.2 Digital Supply Voltage VCC VDD – 5.5 V leakage Currents (ICC) might increase if VCC > VDD P_4.2.3 A resistive loads 1) P_4.2.4 150 o – P_4.2.5 175 o Power Stages Ground Current 9 IGND_typ Temperatures Junction Temperature Junction Temperature Tj Tj -40 -40 – – C C for 100hrs 1) P_4.2.6 1) Not subject to production test, specified by design Data Sheet 11 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface General Product Characteristics Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Table 4 Thermal Resistance Parameter Symbol Values Min. Junction to Soldering Point Junction to ambient RthJC Rth_JA Typ. Max. 1 1.50 21.5 22 Unit Note or Test Condition Number K/W Pvtot = 3W 1) 2) P_4.3.1 K/W 3) P_4.3.2 1) Not subject to production test, specified by design. 2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up. 3) Specified Rth_JAvalue is according to JEDEC JESD51 -5, -7 at natural convection on FR4 2s2p board; the product (chip and package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 μm, 2 x 35 μm CU). Data Sheet 12 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Supply 5 Power Supply 5.1 Description Power Supply The TLE8110ED is supplied by analogue power supply line VDD which is used for the analogue functions of the device, such as the gate control of the power stages. The digital power supply line VCC is used to supply the digital part and offers the possibility to adapt the logic level of the serial output pins to lower logic levels. RST VCC VDD VCC Under Voltage Monitor VDD Under Voltage Monitor or or EN input register Input and Serial Interface diagnosis register Logic control unit control register analogue control, diagnostic and protective functions OUTx Fault Detection Gate Control GND Block_diag_Supply_Reset.vsd Figure 5 Block Diagram Supply and Reset Description Supply The Supply Voltage Pins are monitored during the power-on phase and under normal operating conditions for under voltage. If during Power-on the increasing supply voltage exceeds the Supply Power-on Switching Threshold, the internal Reset is released after an internal delay has expired. In case of under voltage, a device internal reset is performed. The Switching Threshold for this case is the Power-on Switching threshold minus the Switching Hysteresis. In case of under voltage on the analogue supply line VDD the outputs are turned off but the content of the registers and the functionality of the logic part is kept alive. In case of under voltage on the digital supply VCC line, a complete reset including the registers is performed. After returning back to normal supply voltage and an internal delay, the related functional blocks are turned on again. For more details, refer to the chapter “Reset”. The device internal under-voltage set will set the related bits in SDS (Short Diagnosis and Device Status) to allow the micro controller to detect this reset. For more information, refer to the chapter “Control of the Device”. Data Sheet 13 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Supply 5.2 Table 5 Electrical Characteristics Power Supply Electrical Characteristics: Power Supply 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Digital Supply Voltage VCC 3 – 5.5 V – P_5.2.1 Digital Supply Current during Reset (VCC < VCCpo) ICCstb – 15 20 µA fSCLK = 0Hz, S_CS = VCC, Tj = 85°C, VCC = 2.0 V, VDD > VCC, P_5.2.2 a) Digital Supply and Power-on Reset 1) Digital Supply Current during Reset ( VRST > VRSTI) ICCstb – 20 40 µA fSCLK = 0Hz, S_CS = VCC, Tj = 150°C, VCC = 2.0V, VDD > VCC b) – 2 5 µA fSCLK = 0Hz, S_CS = VCC, Tj = 85°C, VDD > VCC, P_5.2.3 a) µA fSCLK = 0Hz, S_CS = VCC, Tj = 150°C, VDD > VCC b) mA fSCLK = 0Hz, T j= 150°C, all Channels ON, P_5.2.4 a) fSCLK= 5MHz, Tj = 150°C, all Channels ON, b) 1) Digital Supply Operating Current VCC = 3.3V ICC – 5 15 – 0.15 2 1) – 0.5 5 mA 1) 2) Digital Supply Operating Current VCC = 5.5V ICC – 0.25 2 mA fSCLK = 0Hz, Tj = 150°C, all Channels ON P_5.2.5 a) – 0.8 mA fSCLK = 5MHz, Tj = 150°C, all Channels ON, b) VCC increasing P_5.2.6 10 1) 2) Digital Supply Power-on Switching Threshold Data Sheet VCCpo 1.9 14 2.8 3 V Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Supply Table 5 Electrical Characteristics: Power Supply 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Digital Supply Switching Hysteresis VCChy 100 300 500 mV 1) P_5.2.7 Analogue Supply Voltage VDD 4.5 – 5.5 V – P_5.2.8 Analogue Supply Current during Reset (VDD < VDDpo ) IDDstb – 10 20 µA fSCLK = 0Hz, Tj = 85°C, VDD = 2V, P_5.2.9 a) Analogue Supply and Power-on Reset 1) Analogue Supply Current during Reset ( VEN < VENI) Analogue Supply Operating Current IDDstb – 15 40 µA fSCLK = 0Hz, Tj = 150°C, VDD = 2V b) – 1 5 µA fSCLK = 0Hz, Tj = 85°C, P_5.2.10 a) 1) IDD – 2 15 µA fSCLK = 0Hz, Tj = 150°C b) – 8 25 mA fSCLK = 0...5MHz, Tj = 150°C, all Channels ON, P_5.2.11 1) Analogue Supply Power-on Switching Threshold VDDpo 3 4.2 4.5 V VDD increasing P_5.2.12 Analogue Supply Switching Hysteresis VDDhy 100 200 400 mV 1) P_5.2.13 Analogue Supply Power-on Delay Time tVDDpo - 200 µs VDD increasing, 1) P_5.2.14 100 1) Parameter not subject to production test. Specified by design. 2) C = 50pF connected to S_SO. Data Sheet 15 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Reset and Enable Inputs 6 Reset and Enable Inputs 6.1 Description Reset and Enable Inputs The TLE8110ED contains one Reset- and one Enable Input Pin as can be seen in Figure 5. Description: Reset Pin [RST] is the main reset and acts as the internal under voltage reset monitoring of the digital supply voltage VCC: As soon as RST is pulled low, the whole device including the control registers is reset. The Enable Pin [EN] resets only the Output channels and the control circuits. The content of the all registers is kept. This functions offers the possibility of a “soft” reset turning off only the Output lines but keeping alive the SPI communication and the contents of the control registers. This allows the read out of the diagnosis and setting up the device during or directly after Reset. 6.2 Table 6 Electrical Characteristics Reset Inputs Electrical Characteristics: Reset Inputs 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Min. Typ. Max. Note or Number Test Condition Reset Input Pin [RST] Low Level of RST VRSTl -0.3 – V CC*0.2 V – P_6.2.1 High Level of RST VRSTh VCC*0.4 – VCC V – P_6.2.2 P_6.2.3 P_6.2.4 RST Switching Hysteresis VRSThy 20 100 300 mV 1) Reset Pin pull-down Current IRSTresh 20 40 85 µA VRST = 5V IRSTresl 2.4 – – µA VRST = 0.6 V, 1) tRSTmin 2 – – µs 1) P_6.2.5 Low Level of EN VENl -0.3 - V *0.2 VCC*0.2 – P_6.2.6 High Level of EN VENh VCC *0.4 - VCC V – P_6.2.7 EN Switching Hysteresis VENhy 20 60 300 mV 1) P_6.2.8 Enable Pin pull-down Current IENresh 5 35 85 µA VEN = 5V P_6.2.9 IENresl 2.4 – – µA VEN = 0.6V, 1) Enable Reaction Time (reaction of OUTx) tENrr – 4 – µs 1) P_6.2.10 Required Enable Duration time EN tENmin 2 – – µs 1) P_6.2.11 Required Reset Duration time RST Enable Input Pin [EN] 1) Parameter not subject to production test. Specified by design. Data Sheet 16 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Reset and Enable Inputs VDD t Enable not valid VEN VENh VENl OUTx Device OFF Enable valid T< Device ON VENhy tENmin t Enable of Output OUTx OFF t ENrr tVDDpo Device operating t External _reset.vsd Figure 6 Data Sheet Timing 17 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs 7 Power Outputs 7.1 Description Power Outputs The TLE8110ED is a 10 channel low-side powertrain switch. The power stages are built by N-channel power MOSFET transistors. The device is a universal multichannel switch but mostly suited for the use in Engine Management Systems [EMS]. Within an EMS, the best fit of the channels to the typical loads is: • Channel 1 to 4 for Injector valves or mid-sized solenoids with a nominal current requirement of 1.5A, • Channel 5 to 6 for mid-sized solenoids or Injector valves with nominal current requirement of 1.7A, • Channel 7 to 10 for small solenoids or relays with a nominal current requirement of 0.75A. Channel 1 to 10 provide enhanced clamping capabilities of typically 55V best suited for inductive loads such as injectors and valves. It is recommended in case of an inductive load, to connect an external free wheelingor clamping diode, where-ever possible to reduce power dissipation. All channels can be connected in parallel. Channels 1 to 4, 5 to 6 and 7 to 10 are prepared by matching for parallel connection with the possibility to use a high portion of the capability of each single channel also in parallel mode (refer to Chapter 7.4). Channel 5 and 6 have a higher current shut down threshold to allow to connect in parallel mode a load with high inrush-current, such as a lambda sensor heater. RST VCC VDD EN OUT1 IN1 IN2 gate control CH1 OUT2 gate control CH2 OUT4 OUT3 IN3 temperature sensor INx Serial and Parallel Input control (for details , see Chapter „Control of the device“ ) input register OUT5 OUT6 short circuit detection diagnosis register open load detection control register short to GND detection OUT7 OUT8 OUT9 OUT10 GND Block _diag_10ch_TLE8x10_Outputs.vsd Figure 7 Data Sheet Block Diagram of Control and Power Outputs 18 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs 7.2 Description of the Clamping Structure When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance intends to continue driving the current. The clamping voltage is necessary to prevent destruction of the device, see Figure 8 for the clamping circuit principle. Nevertheless, the maximum allowed load inductance is limited. Vbat OUT V ID L, RL VDS DScl GND OutputClamp.vsd Figure 8 Internal Clamping Principle Clamping Energy During demagnetization of inductive loads, energy has to be dissipated in the device. This energy can be calculated with following equation: RL ⋅ IL LL V DS ( CL ) – V BAT E = V DS ( CL ) ⋅ ------ ⋅ I L – ---------------------------------------- ⋅ ln æ 1 + ----------------------------------------ö è RL RL V DS ( CL ) – V BATø (7.1) The maximum energy, which is converted into heat, is limited by the thermal design of the component. Attention: It is strongly recommended to measure the load Energy and Current under operating conditions, example of measurement setup is shown in Figure 9. Load small-signal parameters might not reflect the real load behavior under operating conditions, see Figure 10. For more details please refer to the Application Note “Switching Inductive Loads”. Data Sheet 19 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs Temperature Chamber Oscilloscope T=TL OUT Active Clamping Low-Side Switch Inductive Load VCL DMOS Ctrl iL(t) RL LL vD(t) VBAT GND Load Measurement Setup Figure 9 ECL measurement setup Decreasing Inductance with IL Increasing Inductance with IL (Relays and some Valve types) Ctrl ON (Injectors, Valves) OFF Ctrl ON OFF vD, iL vD, iL VCL VCL IL ILm IL ILm VBAT VON VBAT VON t vD · iL R-Temp. Effect t calculated vD · iL R-Temp. Effect measured calculated measured ECL ECLm 0 ECL µ-increase Effect tF tFm L-Saturation Effect ECLm t 0 tFm tF t Deviation from measured values Figure 10 Data Sheet Deviation of calculation from measurement 20 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs 7.3 Electrical Characteristics Power Outputs Table 7 Electrical Characteristics: Power Outputs 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Min. Typ. Max. Note or Test Condition Number Output Channel Resistance On State Resistance Channel Group 1-4 On State Resistance Channel Group 5-6 On State Resistance Channel Group 7-10 RDSon RDSon RDSon – 0.3 – Ohm IDnom = 1.5A, Tj = 25°C 1) – 0.45 0.6 Ohm IDnom = 1.5A, Tj = 150°C – 0.25 – Ohm IDnom = 1.7A, Tj = 25°C 1) – 0.35 0.5 Ohm IDnom = 1.7A, Tj = 150°C – 0.6 – Ohm IDnom = 0.75A, Tj = 25°C 1) – 0.85 1.2 Ohm IDnom=0.75A, Tj = 150°C – – 11 mJ ID = 1.0A, 109 cycles – – 12 mJ ID = 2.1A, 104 cycles – – 15 mJ ID = 2.6A, 10 cycles 5) – – 13 mJ ID = 1.3A, 109 cycles – – 15 mJ ID = 2.7A, 104 cycles – – 20 mJ ID = 3.2A, 10 cycles 5) – – 4 mJ ID = 0.7A, 109 cycles – – 4 mJ ID = 1.4A, 104 cycles – – 5 mJ ID = 1.7A, 10 cycles 5) P_7.3.1 P_7.3.2 P_7.3.3 Clamping Energy - Repetitive1)2)3)4) Channel Group 1-4 Repetitive Clamping Energy EAR P_7.3.4 Channel 5-6 Repetitive Clamping Energy EAR P_7.3.5 Channel 7-10 Repetitive Clamping Energy Data Sheet EAR 21 P_7.3.6 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs Table 7 Electrical Characteristics: Power Outputs (cont’d) 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number P_7.3.7 Min. Typ. Max. Leakage Current – – 3 µA VDS = 13.5V, VDD = 5V, Tj = 85°C 1) – – 8 µA VDS = 13.5V, VDD = 5V, Tj = 150°C – – 6 µA VDS = 13.5V, VDD = 5V, Tj = 85°C1) – – 12 µA VDS = 13.5V, VDD = 5V, Tj = 150°C – – 2 µA VDS = 13.5V, VDD = 5V, Tj = 85°C1) – – 5 µA VDS = 13.5V, VDD = 5V, Tj = 150°C 45 55 60 V – P_7.3.10 fOUTx – – 20 kHz 1) P_7.3.11 Turn-on Time tdON – 5 10 µs VDS = 20% of Vbatt P_7.3.12 Vbatt = 13.5V, IDS1 to IDS6 = 1A, IDS7 to IDS10 = 0.5A, resistive load Turn-off Time tdOFF – 5 10 µs VDS = 80% of Vbatt P_7.3.13 Vbatt = 13.5V, IDS1 to IDS6 = 1A, IDS7 to IDS10 = 0.5A, resistive load Output Leakage Current in standby mode, Channel 1 to 4 Output Leakage Current in standby mode, Channel 5 to 6 Output Leakage Current in standby mode, Channel 7 to 10 IDoff IDoff IDoff P_7.3.8 P_7.3.9 Clamping Voltage Output Clamping Voltage, Channel 1 to VDScl 10 Timing Output Switching Frequency resistive load, duty cycle > 25% 1) Parameter is not subject to production test, specified by design. 2) Either one of the values has to be considered as worst case limitation. Cumulative scenario and wide range of operating conditions are treated in the Application Note “Switching Inductive Loads - TLE8110 addendum”. Data Sheet 22 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs 3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. 4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse. 5) Repetitive operation not allowed. Starting Tj must be kept within specs. In case of high energy pulse an immediate switch-off strategy is recommended. RDS_ON / Ohm 0,6 RON_vs_Tj_CH1-4,6.vsd RDS_ON vs. Tj : CH 1-4 (V DD=5V) 0,5 0,4 0,3 0,2 -40 Figure 11 -20 0 20 40 60 80 100 120 140 Tj/°C CH 1-4: typical behavior of RDS_ON versus the junction temperature Tj RDS_ON / Ohm 0,5 RON_vs_Tj_CH5-6.vsd R DS_ON vs. Tj: CH 5-6 (VDD=5V) 0,4 0,3 0,2 0,1 -40 -20 Figure 12 Data Sheet 0 20 40 60 80 100 120 140 Tj/°C CH5-6: typical behavior of RDS_ON versus the junction temperature Tj 23 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs RDS_ON / Ohm 1.2 RON_vs_Tj_CH7-10.vsd RDS_ON vs. T j: CH 7-10 (V DD=5V) 1.0 0.8 0.6 0.4 -40 Figure 13 -20 0 20 40 60 80 100 120 140 Tj/°C CH7-10: typical behavior of RDS_ON versus the junction temperature Tj VCL_vs_Tj_all_CH.vsd VCL / V VCLn vs. Tj: all Channels 57 56 55 54 53 -40 -20 Figure 14 Data Sheet 0 20 40 60 80 100 120 140 Tj/°C All Channels: typical behavior of the clamping voltage versus the junction temperature 24 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs VINx VINh VINl t VOUTx V BATT 80% 20% t t dON tdOFF Timing_Power_Outx _res1.vsd Figure 15 7.4 Timing of Output Channel switching (resistive load) Parallel Connection of the Power Stages The TLE8110ED is equipped with a structure which improves the capability of parallel-connected channels. The device can be “informed” via the PMx.PMx - bits (see chapter “Control of the device”) which of the channels are connected in parallel. The input channels can be mapped to the parallel connected output channels in order to apply the PWM signals. This feature allows a flexible adaptation to different load situations within the same hardware setup. In case of overload the ground current and the power dissipation is increasing. The application has to take into account that all maximum ratings are observed (e.g. operating temperature TJ and total ground current IGND, see Maximum Ratings). In case of parallel connection of channels with or w/o PM-bit set, the defined maximum clamping energy must not be exceeded. All stages are switched on and off simultaneously. The µC has to ensure that the stages which are connected in parallel have always the same state (on or off). The PM-bit should be set according to the parallel connected power stages in order to achieve the best possible performance. The PM-bit is set to its default value in case of a Reset event (Reset pin Low or at Digital Supply undervoltage), that means the improved Parallel Mode is no longer active. In the event of reset the channels will be switched off causing the clamping energy to be dissipated with low performance of the current sharing as without PMbit set, for more details please refer to the Application Note Switching Inductive Loads - TLE8110 addendum. The performance during parallel connection of channels is specified by design and not subject to the production test. All channels at the same junction temperature level. ON-Resistance The typical ON-Resistance RDSsum(typ) of parallel connected channels is given by: 1 1 R DSsum ( typ ) = ----------------------------- + ------------------------------------R DSon, n ( typ ) R DSon, n + 1 ( typ ) Data Sheet –1 (7.2) 25 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs Table 8 Performance 1) 2) 3) 4) in case of Parallel Connection of Channels: related PM-Bit set Parameter Symbol Channels in Parallel 2x 3x 4x Unit Conditions Number P_7.4.1 Channel Group 1-4 Maximum overall current before reaching lower limit threshold IDsum(low) 5.1 7.6 10.1 A Maximum overall Repetitive Clamping Energy EARsum 37 – – mJ ID = 1.0A, 109 cycles 17 38 69 mJ ID = 1.75A, 109 cycles – 23 42 mJ ID = 2.5A, 109 cycles – – 33 mJ ID = 3.0A, 109 cycles P_7.4.2 Channel Group 5-6 Maximum overall current before reaching lower limit threshold IDsum(low) 7.2 – – A – P_7.4.3 Maximum overall Repetitive Clamping Energy EARsum 43 – – mJ ID = 1.3A, 109 cycles P_7.4.4 21 – – mJ ID = 2.2A, 109 cycles Channel Group 7-10 Maximum overall current before reaching lower limit threshold IDsum(low) 3.3 5.0 6.6 A – P_7.4.5 Maximum overall Repetitive Clamping Energy EARsum 15 – – mJ ID = 0.7A, 109 cycles P_7.4.6 6 15 30 mJ ID = 1.2A, 109 cycles – 9 18 mJ ID = 1.6A, 109 cycles – – 11 mJ ID = 2.1A, 109 cycles 1) The performance during parallel connection of channels is specified by design and not subject to the production test. 2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up. 3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. 4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse. Data Sheet 26 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Power Outputs Table 9 Performance 1) 2) 3) 4) in case of Parallel Connection of Channels: related PM-Bit NOT set Parameter Symbol Channels in Parallel 2x 3x 4x Unit Conditions Number P_7.5.1 Channel Group 1-4 Maximum overall current before reaching lower limit threshold IDsum(low) 5.1 7.6 10.1 A Maximum overall Repetitive Clamping Energy EARsum 18 – – mJ ID = 1.0A, 109 cycles 8 13 19 mJ ID = 1.75A, 109 cycles – 8 11 mJ ID = 2.5A, 109 cycles – – 9 mJ ID = 3.0A, 109 cycles P_7.5.2 Channel Group 5-6 Maximum overall current before reaching lower limit threshold IDsum(low) 7.2 – – A – P_7.5.3 Maximum overall Repetitive Clamping Energy EARsum 22 – – mJ ID = 1.3A, 109 cycles P_7.5.4 11 – – mJ ID = 2.2A, 109 cycles Channel Group 7-10 Maximum overall current before reaching lower limit threshold IDsum(low) 3.3 5.0 6.6 A – P_7.5.5 Maximum overall Repetitive Clamping Energy EARsum 7 – – mJ ID = 0.7A, 109 cycles P_7.5.6 3 4 7 mJ ID = 1.2A, 109 cycles – 3 4 mJ ID = 1.6A, 109 cycles – – 3 mJ ID = 2.1A, 109 cycles 1) The performance during parallel connection of channels is specified by design and not subject to the production test. 2) Homogenous power distribution over all channels (all power stages equally heated), dependent on cooling set-up. 3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. 4) Triangular Pulse Shape (inductance discharge): ID(t) = ID(0)·(1 - t / tpulse); 0 < t < tpulse. Data Sheet 27 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Diagnosis 8 Diagnosis 8.1 Diagnosis Description The TLE8110ED provides diagnosis information about the device and about the load. Following diagnosis flags have been implemented for each channel: Diagnosis 1) Symbol DRn[1:0]x Device reaction Confirmation Procedure 3) Short to Ground SCG 00B - - No Fault OK 11B - - Open Load OL 01B - Chapter 8.1.1 Overcurrent/ Overtemperature OCT 10B Switch-off of related channel Chapter 8.1.2 2) 1) No priority scheme is implemented for the diagnosis detection, any new diagnosis entry will override the previous one. 2) Diagnosis Register (A/B banks) bit configuration, see Chapter 12.3.2.1. 3) For some diagnosis a confirmation procedure is required for a safe operation of the device, refer to Figure 16. Updating of the Diagnosis is based on a filter-dependent standard delay time (td) of 220µs max. This value is set as a default. Refer to Figure 17 for details. If SCG or OL condition is asserted and before the Diagnosis Delay Time (td) is elapsed a condition change occurs, OL-to-SCG or SCG-to-OL, filter timer is not reset and latest condition before td expiration will be stored into the diagnosis register. • Application Hint: It is recommended to avoid OFF periods of the channel shorter than td(max) (220µs) in order to ensure the filter time is expired and the correct diagnosis information is stored. • Application Hint: In specific application cases - such as driving Uni-Polar Stepper Motor - it might be possible, that reverse currents flow for a short time, which possibly can disturb the diagnosis circuit at neighboring channels and cause wrong diagnosis results of those channels. To reduce the possibility, that this effect appears in a certain timing range, the filter time of Channels 7 to 10 can be extended to typ. 2.5ms or typ. 5ms by setting the “Diagnosis Blind Time” - Bits (DBTx). If Channels 7 to 10 are used for driving loads causing reverse currents, they influence each other and additionally might affect Channels 5 and 6. It is recommended to use the channels 7 + 8 and 9 + 10 as pairs for anti-parallel control signals, such as for the stepper motors. For logic setting details, see chapter “Control of the Device”. 8.1.1 Open Load diagnosis If an OL is read out of the Diagnosis Register, the following procedure is required in order to confirm the channel status and ensure a safe operation of the device: After reading the OL [01B] in the diagnosis register (Chapter 12.3.2) 1. Switch-OFF for t ≥ td(max) the related channel (via serial or direct control, see (Chapter 12.3.3) and (Chapter 12.3.4), 2. Read again the diagnosis register a) If OL is confirmed Then take actions according to system implementation, 3. Continue normal operation. Data Sheet 28 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Diagnosis Refer to Figure 16 for the procedure flow-chart. 8.1.2 Overcurrent / Overtemperature diagnosis After an OCT assertion the related channel is switched OFF for safety reasons. If an OCT is read out of the Diagnosis Register, the following procedure is required in order to confirm the channel status and ensure a safe operation of the device: After reading the OCT [10B] in the diagnosis register (Chapter 12.3.2 ) 1. Set related bit DEVS.DCCx = 0 to disable OFF-diagnosis, see (Chapter 12.3.6), 2. Clear the Diagnosis issuing a DCC.DRxCL command, see (Chapter 12.3.2), 3. Switch-ON for t ≥ tOFFcl_l(max) the related channel, 4. Read again the diagnosis register a) If OCT is confirmed Then take actions according to system implementation, 5. Set related bit DEVS.DCCx = 1 to enable OFF-diagnosis, 6. Continue normal operation. Refer to Figure 16 for the procedure flow-chart. DCC.DRx (read diagnosis) OK ? yes SCG ? yes OL ? yes no actions no take SCG action no wait t d(max) with Channel OFF no DCC.DRx (read Diagnosis) yes OL ? take OL action no OCT ? yes DEVS.DCCx=0 (disable OFF-diag) no DCC.DRxCL (clear diagnosis) wait tOFFcl _l(max) with Channel ON DCC.DRx (read Diagnosis) OCT ? yes take OCT action no DEVS.DCCx=1 (enable OFF-diag) Diagnosis Confirmation Figure 16 Data Sheet Diagnosis Confirmation procedure 29 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Diagnosis VDD Diagnosis Register IDSsg MUX 00 01 10 OUTn Latch IDSpd Latch VDSsg VDSol Temp. Sensor gate control n OR Latch protective functions n GND Diagnosis-serial.vsd Figure 17 8.2 Table 10 Block Diagram of Diagnosis Electrical Characteristics Diagnosis Electrical Characteristics: Diagnosis 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Open load detection threshold voltage VDSol 2.00 2.60 3.20 V – P_8.2.1 Output pull-down diagnosis current per channel (low level) IDpd 50 Open Load Diagnosis Delay Time (all channels) td Open Load Diagnosis Channel 7-10: td Open Load Diagnosis Delay Time “Diagnosis Blind Time” see chapter “Control of the device”,Figure 18, Figure 19 90 150 µA VDS = 13.5 V P_8.2.2 100 – 220 µs DEVS.DBT1 = 0 DEVS.DBT2 = 1 or 0 P_8.2.3 1.65 2.5 3.45 ms DEVS.DBT1 = 1 DEVS.DBT2 = 0 3.3 7.3 DEVS.DBT1 = 1 DEVS.DBT2 = 1 P_8.2.4 a) b) 5 ms Short to GND Diagnosis Short to ground detection threshold voltage VDSsg 1.00 1.50 2.00 V – P_8.2.5 Output diagnosis current for short to ground per channel (low level) IDsg -150 -100 -50 µA VDS = 0V P_8.2.6 Short to GND Diagnosis Delay Time td 100 – µs DEVS.DBT1 = 0 DEVS.DBT2 = 1 or 0 P_8.2.7 Data Sheet 30 220 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Diagnosis Table 10 Electrical Characteristics: Diagnosis 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Channel 7-10: Short to GND Diagnosis Delay Time. “Diagnosis Blind Time” see chapter “Control of the device”,Figure 18, Figure 19 td 1.65 2.5 3.45 ms DEVS.DBT1 = 1 DEVS.DBT2 = 0 3.3 7.3 DEVS.DBT1 = 1 DEVS.DBT2 = 1 P_8.2.8 a) b) 5 ms Diagnosis Blind Time [DBT] activation DBT is triggered by Open Load [OL] or Short-to-Ground [SG] -detection during OFF-condition of CH7-10. DBT is activated by DEVS.DBT1, DEVS.DBT2 (see „Control of the device“). INx Signal Channel 7 - 10 OFF OL, SG -Diagnosis active ON Output Voltage Incident - e.g. temporal „short to GND“ [SG] Diagnosis Blind Time [DBT] triggered by Diagnostic Incident Diagnosis Blind Time [DBT] active DBT „Blind“ window finishes as soon as the error disappears within the DBT 1 1 Figure 18 Data Sheet t err < tDBT 1 1 t err< tDBT terr > t DBT 1 1 Diagnostic Register Entry, because Failure present after ending DBT Diagnosis Register : 11: No Error 10: Over Load 01: Open Load 00: Short to Ground 0 0 DBT.vsd Diagnosis Blind Time 31 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Diagnosis Channel OFF YES OL, SGError present? YES OL, SGError detected DBT Counter SET 0 = tDBT Decrement DBT Counter OL, SGError present? No Reset Counter (finish DBTframe) Yes No Counter t > tDBT Yes Failure detected => Register Entry DBT_Flow. vsd Figure 19 Data Sheet Diagnosis Blind Time - Logic Flow 32 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Parallel Inputs 9 Parallel Inputs 9.1 Description Parallel Inputs There are 10 input pins available are on TLE8110ED to control the output stages. Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1, IN2 controls OUT2, etc. A “Low”-Signal at INx switches the related Output Channel off. The zener diode protects the input circuit against ESD pulses. For details about the Boolean operation, refer to the chapter “Control of the device”, for details about timing refer to Figure 11. 9.2 Table 11 Electrical Characteristics Parallel Inputs Electrical Characteristics: Parallel Inputs 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. – Unit Note or Number Test Condition Parallel Inputs Low Level of parallel Input pin VINxl -0.3 High Level of Parallel Input pin VINxh VCC*0.4 – VCC*0.2 V – P_9.2.1 VCC V – P_9.2.2 P_9.2.3 P_9.2.4 a) b) Parallel Input Pin Switching Hysteresis VINxhy – 15 60 300 mV 1) Input Pin pull-down Current IINxh 20 40 85 µA VINx = 5V IINxl 2.4 – – µA VINx = 0.6V 1) 1) Parameter not subject to production test. Specified by design. Data Sheet 33 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Protection Functions 10 Protection Functions The device provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this Document. Fault conditions are considered “outside” the normal operating range. Protection functions are not designed for continuous repetitive operation. There is an over load and over temperature protection implemented in the TLE8110ED. If a protection function becomes active during the write cycle of Diagnosis Information into the Diagnosis Register, the information is latched and stored into the diagnosis register after the write process. In order to achieve a maximum protection, the affected channel with over current or over temperature (OCT) is switched and latched OFF, channel can be turned ON again after the diagnosis register is cleared (Chapter 12.3.2). For the failure condition of Reverse Currents, the device contains a “Reverse Current Protection Comparator” [RCP]. This RCP can optionally be activated by setting the DEVS.RCP Bit. In case the comparator is activated, it detects a reverse current and switches ON the related output channel. The channel is kept ON up to a reverse current channel dependent threshold IRCP_off. This threshold is defined by regulators target value to keep the output voltage at >/~-0.3V. If the current exceeds a defined value, the comparator switches OFF and other protection functions are protecting the circuit against reverse current. That means that at higher currents / or in case RCP is de-activated / not activated, the reverse current is flowing through the body diode of the DMOS. In that case, the voltage drops to typically -0.6V according the voltage of the body diode. In case the comparator threshold has been exceeded and the RCP has been switched OFF, the functions remains OFF until the reverse current arrives back to zero reverse current. Only then, the comparator can be activated again after a delay time tRCP_on_delay. This function reduces the un-wanted influence of a reverse current to the analogue part of the circuit (such as the diagnosis). For more details about the functionality, see Figure 22 and Figure 23 and concerning the settings and the related registers, refer to Chapter “Control of the Device”. RCP Logic Ctrl. temperature sensor Ref. -300mV OUTx T gate control Serial control short circuit detection Block_diag_Protection.vsd Figure 20 Data Sheet Block Diagram Protection Functions 34 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Protection Functions IDS tOFFcl _l tOFFcl_h switch-off after t OFFcl_h (short) with I >IDSD(high) switch-off after t OFFcl_l (long) if I falls below IDSD(high) before t OFFcl_h I DSD(high) switch-off after t OFFcl_l (long) with I >I DSD(low) immediate switch-off if I= IDSD(high) after t OFFcl_h IDSD(low) no switch-off with I I DSD(high) • at t =tOFFcl _l if IDSD(low) < I < I DSD(high) Overload shutdown thresholds and delay times Figure 21 10.1 Table 12 Overload shutdown thresholds and delay times Electrical Characteristics Overload Protection Function Electrical Characteristics: Overload Protection Function 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Number Min. Typ. Unit Note or Test Condition Max. 5 Over Current Protection Output Current Shut-down Threshold Low (Channel 1 to 4) IDSD(low) 2.6 Output Current Shut-down Threshold Low (Channel 5 to 6) IDSD(low) Output Current Shut-down IDSD(low) Threshold Low (Channel 7 to 10) 3.8 A – P_10.1.1 3.70 4.85 6.00 A – P_10.1.2 1.7 2.9 A – P_10.1.3 2.3 Output Current Shut-down Threshold High (Channel 1 to 4) IDSD(high) – 1.5 * IDSD (low) – A 1) P_10.1.4 Output Current Shut-down Threshold High (Channel 5 to 6) IDSD(high) – 1.5 * IDSD (low) – A 1) P_10.1.5 Output Current Shut-down IDSD(high) – Threshold High (Channel 7 to 10) 1.5 * IDSD (low) – A 1) P_10.1.6 21 µs valid for “Output P_10.1.7 Current Threshold High” 1) Short Overload shutdown Delay Time (all Channels) Data Sheet tOFFcl_h 5 40 35 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Protection Functions Table 12 Electrical Characteristics: Overload Protection Function (cont’d) 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Long Overload shutdown Delay Time (all Channels) Symbol tOFFcl_l Values Min. Typ. Unit Note or Test Condition Max. 10 70 µs valid for “Output P_10.1.8 Current Threshold Low” 205 °C 1) P_10.1.9 P_10.1.10 40 Number Over Temperature Protection Thermal Shut Down Temperature TjSD 175 190 TjSDh 10 – 20 K 1) Reverse Current Comparator Switch-off Current level CH 1 - 4 IRCP_off – -0.9 – A DEVS.RCP = 1, Tj = 25°C 1) P_10.1.11 Reverse Current Comparator Switch-off Current level CH 5 - 6 IRCP_off – -0.6 – A DEVS.RCP = 1, Tj = 25°C 1) P_10.1.12 Reverse Current Comparator IRCP_off Switch-off Current level CH 7 - 10 – -0.45 – A DEVS.RCP = 1, Tj = 25°C 1) P_10.1.13 Reverse Current Comparator switch on delay time – 24 – µs DEVS.RCP = 1, Tj = 25°C 1) P_10.1.14 Thermal Shut Down Hysteresis Reverse Current Protection tRCP_on_ delay 1) Parameter not subject to production test. Specified by design. Data Sheet 36 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Protection Functions ID Leakage (neighbour channel) RCP not active RCP active Reverse Current Comparator Switch-off Current level IRCP_off Reverse Current ID 0 t Reverse Current Comparator Switch-off Current level IRCP_off Maximum Rating -IDSD(low) VD VBatt 0 t ~ - 300mV tRCP_on_delay RCP active: RCP not active: Regulation to ID through Body VD ~ - 300mV; Diode of DMOS -ID through DMOS Figure 22 Data Sheet RCP.vsd Reverse Current Protection Comparator 6 37 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Protection Functions -40 -20 0 20 40 60 80 100 120 140 Tj / °C -0.1 CH7-10 -0.3 -0.5 CH1-6 -0.7 -0.9 -1.1 -1.3 -1.5 IRCP_off /A Figure 23 Data Sheet IRCP_OFF_TC_12_ch.vsd Reverse Current Protection Comparator (typical behavior vs. junction temperature) 38 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface 16 bit SPI Interface 11 16 bit SPI Interface 11.1 Description 16 bit SPI Interface The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: S_SO, S_SI, S_CLK and S_CS. Data is transferred by the lines S_SI and S_SO at the data rate given by S_CLK. The falling edge of S_CS indicates the beginning of a data access. Data is sampled in on line S_SI at the falling edge of S_CLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of S_CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle not a multiple of 8 bits have been counted, the data frame is ignored. The interface provides daisy chain capability. S_SO MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S_SI MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB LSB S_CS S_CLK time SPI.vsd Figure 24 16 bit SPI Interface The SPI protocol is described in Chapter “Control of the device”. Concerning Reset of the SPI, please refer to the chapter “Reset”. 11.2 Timing Diagrams t CS lead t CSlag t S_CS t CStd SCLKp 0.7Vdd 0.2Vdd t SCLKh t SCLKl 0.7Vdd 0.2Vdd S_CLK t SIsu t SIh 0.7Vdd S_SI 0.2Vdd tSO(en) t SOv t SOdis 0.7Vdd S_SO 0.2Vdd Timing SPI.vsd Figure 25 Data Sheet SPI timing diagram 39 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface 16 bit SPI Interface 11.3 Electrical Characteristics 16 bit SPI Interface Table 13 Electrical Characteristics: 16 bit SPI Interface 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. -0.3 – Unit Note or Test Condition Number Input Characteristics (CS, SCLK, SI) L level of pin S_CS, S_CLK, S_SI, H level of pin S_CS, S_CLK, S_SI, VS_CSI VS_CLKl VS_SIl VS_CSh VS_CLKh VS_SIh VCC* 0.4 – VCC* 0.2 V – P_11.3.1 VCC V – P_11.3.2 Hysteresis Input Pins VS_CShy 20 VS_CLKhy VS_SIhy 100 300 mV – P_11.3.3 Input Pin pull-down Current S_CLK, S_SI IS_CLKh IS_Slh 20 40 85 µA VIN = 5V IS_CLKl IS_Slh 2.4 – – µA VIN = 0.6V 1) P_11.3.4 a) b) IS_CSh -4 – – µA VS_CS = 2V, VCC = 5V IS_CSl -20 -40 -85 µA VS_CS = 0 V, VCC = 5V L level output voltage VS_SOl 0 – 0.4 V IS_SO = -2 mA P_11.3.6 H level output voltage VS_SOh Vcc 0.4 V – Vcc – IS_SO = 1.5 mA P_11.3.7 Output tristate leakage current IS_SOoff -10 – 10 µA VS_SO = Vcc P_11.3.8 Serial clock frequency fS_CLK 0 – 5 MHz CL = 50 pF 1) Serial clock period tS_CLK(P) 200 – – ns 1) P_11.3.10 ns 1) P_11.3.11 P_11.3.12 Input Pin pull-up Current S_CS P_11.3.5 a) b) Output Characteristics (SO) Timings Serial clock high time tSCLK(H) 50 – – P_11.3.9 50 – – ns 1) Enable lead time (falling CS to rising tCS(lead) SCLK) 250 – – ns 1) P_11.3.13 Enable lag time (falling SCLK to rising tCS(lag) CS) 250 – – ns 1) P_11.3.14 tCS(td) 250 – – ns 1) P_11.3.15 Serial clock low time Transfer delay time (rising CS to falling CS) Data Sheet tSCLK(L) 40 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface 16 bit SPI Interface Table 13 Electrical Characteristics: 16 bit SPI Interface (cont’d) 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Data setup time (required time SI to falling SCLK) tSI(su) 20 – – ns 1) Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1) Number P_11.3.16 P_11.3.17 1) P_11.3.18 Output enable time (falling CS to SO tSO(en) valid) – – 200 ns CL = 50 pF Output disable time (rising CS to SO tri-state) tSO(dis) – – 200 ns CL = 50 pF 1) P_11.3.19 Output data valid time with capacitive load tSO(v) – – 100 ns CL = 50 pF 1) P_11.3.20 Diagnosis Clear-to-Read Idle Time tDidle 16 – – µs 1) P_11.3.21 µs 1) P_11.3.22 Diagnosis Overcurrent-to-Clear Idle Time tOCidle 12 – – 1) Not subject to production test, specified by design. Data Sheet 41 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12 Control of the device This chapter describes the SPI-Interface signals, the protocol, registers and commands. Reading this chapter allows the Software Engineer to control the device. The chapter contains also some information about communication safety features of the protocol. 12.1 Internal Clock The device contains an internal clock oscillator. Table 14 Electrical Characteristics: Internal Clock 3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. - 500 - Unit Note or Number Test Condition kHz 1) Parallel Inputs internal clock oscillator frequency fint_osc 1) Parameter not subject to production test. Specified by design. 12.2 SPI Interface. Signals and Protocol 12.2.1 Description 16 bit SPI Interface Signals S_CS - Chip Select: The system micro controller selects the TLE8110ED by means of the S_CS pin. Whenever the pin is in low state, data transfer can take place. When S_CS is in high state, any signals at the S_CLK and S_SI pins are ignored and S_SO is forced into a high impedance state. S_CS High to Low transition: • The information to be transferred loaded into the shift register (16-bit Protocol). S_CS Low to High transition: • Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3...) of eight S_CLK signals have been detected. (See Modulo-8 Counter: Chapter 12.2.4.2). S_CLK - Serial Clock: This input pin clocks the internal shift register. The serial input (S_SI) transfers data is shifted into register on the falling edge of S_CLK while the serial output (S_SO) shifts the information out on the rising edge of the serial clock. It is essential that the S_CLK pin is in low state whenever chip select CS makes any transition. S_SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. The bit at the S_SI Pin is read on the falling edge of S_CLK. S_SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. S_SO is in high impedance state until the S_CS pin goes to low state. The next bits will appear at the S_SO is in high impedance state until the S_CS goes to low state. The next bits will appear at the S_SO pin following the rising edge of S_CLK. Data Sheet 42 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.2.2 Daisy Chain The SPI-Interface of TLE8110ED provides daisy chain capability, see Chapter 12.2.3.4 for more details. In this configuration several devices are activated by the same S_CS signal. The S_SI line of one device is connected with the S_SO line of another device (see Figure 26), which builds a chain. The ends of the chain are connected with the output and input of the master device, S_SO and S_SI respectively. The master device provides the master clock CLK, which is connected to the S_CLK line of each device in the chain. By each clock edge on S_CLK, one bit is shifted into the S_SI. The bit shifted out can be seen at SO. After 16 S_CLK cycles, the data transfer for one device has been finished. In single chip configuration, the S_CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been shifted in to device 2. Example: When using three devices in daisy chain, three times 16 bits have to be shifted through the devices. After that, the S_CS line must go high (see Figure 26). SI SO SO device 3 SO device 2 SO device 1 SI device 3 SI device 2 SI device 1 CS CLK time SPI_DasyChain2.emf Figure 26 Principle example for Data Transfer in Daisy Chain Configuration Note: Due to the integrated modulo 8 counter, 8 bit and 16 bit devices can be used in one daisy chain. 12.2.3 SPI Protocol The device contains two protocol styles which are applied dependent of the used commands. There is the standard 16-bit protocol and the 2x8-bit protocol. Both protocols can appear also be mixed. 12.2.3.1 16-bit protocol Each cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned at the same time by the S_SO. The content of the S_SO frame is dependent on the previous command which has been sent to S_SI. Read Command (R/W = R) returns one cycle later the content of the address register (see Figure 27). R ADR / DATA W ADR / DATA R ADR / DATA S_SO dept. of previous R/W Register * dependent on ADR; In case CMD or DCC is addressed, related content. Figure 27 Data Sheet Short Diagnosis* SPI_Protocol_Normal_ Mode.vsd 16-bit protocol 43 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 16-bit protocol S_SI Serial Input 15 14 13 12 11 10 9 8 7 ADDR W/R 14 PAR 13 5 4 3 2 1 0 Reset value: xxxx xxxx xxxx xxxxB1) 7 6 5 4 3 2 1 0 DATA/CMD S_SO Serial Output 15 6 12 11 10 9 8 ADDR DATA 1) after reset a Short Diagnosis and Device Status CMD_CSDS response is sent, see Chapter 12.3.1.2. Bit description Field Bits Type Function S_SI Serial Input W/R 15 Write/Read 0 Write register: The register content of the addressed register will be updated after CS low → high transition. After sending a WRITE command, the device returns data according the addressed register, 1 Read register: The register content of the addressed register will be sent in the next frame. ADDR [14:12] ADDR - Address Pointer to register for read and write command. DATA/CMD [11:0] DATA_CMD - Data / Command Data written to or read from register selected by address ADDR. S_SO Serial Output PAR 15 PAR - Parity Bit 0 Even number of ‘1’ in data and address field, 1 Odd number of ‘1’ in data and address field. ADDR [14:12] Address Address which has been addressed. DATA [11:0] Data Content of Address or feedback data. Note: Data Sheet Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. 44 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.2.3.2 2x8-bit protocol Each Cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned at the same time by the S_SO. The content of the S_SO frame is dependent of the previous command which has been sent to S_SI and the content of the actual content of S_SI: The first Upper Byte send to S_SI controls the content of the Lower Byte actual returned by S_SO. The Lower Byte send to S_SI controls the Lower Byte in S_SO of the next frame (see Figure 28). S_CS S_SI S_SO DMSx OPSx Upper Byte Lower Byte Upper Byte Lower Byte Upper Byte DO OPF Lower Byte Upper Byte Lower Byte SPI_Protocol_Short_Mode.vsd Figure 28 2x8-bit protocol 2x8-bit protocol S_SI Serial Input 15 14 13 12 11 10 9 8 7 Upper Byte 14 13 12 11 5 4 3 2 1 0 Reset value: xxxx xxxx xxxx xxxxB1) 7 6 5 4 3 2 1 0 Lower Byte S_SO Serial Output 15 6 10 9 8 Upper Byte Lower Byte 1) after reset a Short Diagnosis and Device Status CMD_CSDS response is sent, see Chapter 12.3.1.2. Bit description Field Bits Type Function S_SI Serial Input Upper Byte [15:8] Upper Byte Contains the command, which is performed after sending 8 bit to S_SI. The action out of this command is affecting the Lower Byte of S_SO of the actual communication frame. Lower Byte [7:0] Lower Byte Containsthe command and data, which is performed at the end of the actual communication frame. The action out of this command is affection the Upper Byte of S_SO of next communication frame. Data Sheet 45 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Bit description Field Bits Type Function S_SO Serial Output Upper Byte [15:8] Upper Byte Contains the data according the command and data in the Lower Byte of the previous communication frame. Lower Byte [7:0] Lower Byte Contains the data according the command in the Upper Byte of the actual communication frame. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. 12.2.3.3 16- and 2x8-bit protocol mixed The 16-bit and 2x8-bit protocols are mixed according the used commands (see Chapter 12.3.1). Special care should be taken,changing from the 16-bit protocol to the 2x8-bit protocol. In this case, it is important to send a NOP command to S_SI. Otherwise, by sending instead a Command, a collision between the S_SO data in the following frame and the Lower Byte of the 2x8-bit protocol will happen (see Chapter 12.2.3.2). Protocol Change from2x8-bit to 16-bit S_CS S_SI S_SO Upper Byte Lower Byte Upper Byte Lower Byte CMD CMD Upper Byte 0 NOP Upper Byte Lower Byte Upper Byte Lower Byte Data 0 Lower Byte Upper Byte Lower Byte Data Protocol Change from16-bit to 2x8-bit S_CS S_SI S_SO Critical Protocol Change from16-bit to 2x8-bit S_CS 2x8-bit protocol is dominant S_SI CMD Upper Byte Lower Byte Upper Byte Lower Byte Data Data... Lower Byte Upper Byte Lower Byte S_SO collission Figure 29 Data Sheet SPI_Protocol_ 16_2x8bit_mixed.vsd 16-bit protocol and 8bit protocol mixed 46 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.2.3.4 Daisy-Chain and 2x8-bit protocol when using the TLE8110ED in a daisy-chain connection with other devices (TLE8110ED and non) special care has to be taken to avoid interference of 2x8-bit protocol with normal communication. Few simplifed rules must be followed for a safe SPI communication in daisy-chain environment: 1. All TLE8110ED devices have to be routed at the beginning of the chain, other devices than TLE8110ED afterward. 2. compactCONTROL commands (2x8-bit protocol) must not be addressed to TLE8110ED. 3. The SPI frame of the daisy-chain must be extended of additional 8-bit (all zeros 00H) at befinning of the frame. 4. When a Read/Clear Diagnosis Register A command(DRA, DRACL) is addressed to TLE8110ED, a NOP command must be sent to the next TLE8110ED on the chain. 5. When a Read/Clear Diagonosis Register A command (DRA, DRACL) is addressed to TLE8110ED, response of the next device on the chain must be ignored in the next SPI cycle. Details in Figure 30 and Figure 31. Critical Communication with first 8-bit interpreted as compactCONTROL (2x8-bit protocol ) SPI daisy-chain word S_CS first 8-bit that could interfere with compacCONTROL of device 1 S_SI to dev.n to dev.1 from dev.n from dev.1 S_SO lower-byte from dev.n affected by the reaction of dev.1 to compactCONTROL t Safe Communication with first all zeros 8-bit extension SPI daisy-chain word S_CS all zeros 8-bit extension S_SI 00 H to dev.n to dev.1 S_SO from dev.n from dev.1 last 8-bit to be ignored t Daisy-Chain and 2x8-bit protocol Figure 30 Data Sheet Daisy-Chain and 2x8-bit protocol 47 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Critical Communication with dev.n+1 response altered by dev .n response to previous DRA /DRACL SPI daisy-chain word SPI daisy-chain word S_CS S_SI x-command DRA/DRACL to dev.n+1 to dev.n from dev.n+1 from dev.n to dev.n+1 to dev.n S_SO from dev.n+1 response to x-command from dev.n response to DRA-/CL 8-bit altered by dev.n response to DRA-/CL t Safe Communication with NOP command send to dev .n+1 and ignored response SPI daisy-chain word SPI daisy-chain word S_CS S_SI NOP DRA/DRACL to dev.n+1 to dev.n to dev.n+1 from dev.n+1 from dev.n from dev.n+1 to dev.n S_SO no response expected ignored from dev.n response to DRA-/CL t DRA, DRACL to dev .n and NOP command to dev .n+1 Figure 31 12.2.4 DRA, DRACL to dev.n and NOP command to dev.n+1 safeCOMMUNICATION The device contains some safety features, which are improving the protection of the application against malfunction in case of disturbance of the communication between the Micro Controller and the Device: 12.2.4.1 Encoding of the commands The Commands are encoded. In case other bit-patterns, then the defined once are received, the commands are ignored and the communication error can be read out with the command CMD_RSDS (see Chapter 12.3.1.2). 12.2.4.2 Modulo-8 Counter The modulo is the integral remainder in integral division. In data communications, a modulo based approach is used to ensure that user information in SPI protocols is in the correct order. The device has a receiver-side counter, and a defined counter size. The modulo counter specifies the number of subsequent numbers available. In case of TLE8110ED Modulo 8 counter specifies 8 serial numbers. The modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. If in one transfer cycle not a multiple of Data Sheet 48 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 8 bits have been counted, the data frame is ignored and a Communication Error is indicated in the CMD_RSDS - Feedback (see Chapter 12.3.1.2). 12.3 Register and Command - Overview This chapter describes the Registers and Commands. The commands allow to carry through some actions, such as reading out or clearing the diagnosis or reading out the Input Pins. Specially highlighted here should be the encoded CMD_DMSx/OPSx commands - compactCONTROL -, a highly efficient command-set to set a part of the output pins and read out the diagnosis at the same time. Included in this command set is the possibility to check, if the communication works well as also the possibility to readout some of the parallel Input Pins INx. Using this compact command set can reduce the workload of the micro-controller during run-time significantly. CMD_RSD is preformed and short diagnostics [SD] is returned after each Write Cycle to any of the writable registers. After start-up of the device, the registers are loaded with the default settings as described below in the register descriptions. The Registers are cleared and set back to the default values, when a low signal is applied to the pin RST or an under-voltage condition appears at the supply pin VCC what causes an under-voltage reset. If a low signal at pin EN is applied or an under-voltage condition appears at pin VDD, the Registers are not cleared. Table 15 Command Overview Name Type Addr. Short Description see: W 1) 000B Commands Chapter 12.3.1 DCC W 1) 001B Diagnosis Registers and Compact Control Chapter 12.3.2 OUTx W/R 010B Output Control Register CHx Chapter 12.3.3 DEVS W/R 011B Device Settings Chapter 12.3.6 MSCS W/R 100B Reserved - ISAx W/R 101B Input or Serial Mode Register CHx Bank A Chapter 12.3.4 ISBx W/R 110B Input or Serial Mode Register CHx Bank B Chapter 12.3.4 PMx W/R 111B Parallel Mode Control of CHx with CHy Chapter 12.3.5 CMD 1) if a read command is sent, the command is ignored and S_SO returns a frame with ’0’. Table 16 Nam e Register Overview Addr 11 . 10 9 8 7 1 1 1 Command CMD W 2) 000B 0 DCC W 2) 001B Command 010B 1 1 DEVS W/R 011B RCP DBT2 DBT1 0 MSCS W/R 100B Reserved ISAx 101B IS6 Data Sheet 5 4 3 2 1 0 def. 1) - OUTx W/R W/R 6 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT C00H 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 DCC 10 DCC 9 DCC 18 007H 000H IS5 IS4 IS3 49 IS2 IS1 AAAH Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Table 16 Nam e Register Overview Addr 11 . 10 9 8 7 ISBx W/R 110B 0 0 0 0 IS10 PMx W/R 111B 0 0 0 0 PM 910 6 5 4 IS9 PM 89 PM 78 3 2 IS8 PM 56 0 1 0 IS6 PM 34 PM 23 def. 1) 0AAH PM 12 000H 1) Default values after Reset. 2) if a read command is sent, the command is ignored and S_SO returns a frame with ’0’. Data Sheet 50 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device IS1[1:0]: AND IN/Serial-Mod0 = 11 IN-Mode = 10 Serial-Mode OUT1=1 = 01 Serial-Mode OUT1=0 = 00 DC18[0]: Diagn. current off = 0 Diagn. Current on = 1 IS1[1:0] OUT1 11 IN1 10 0x OUT1 IS2[1:0] 11 IN2 OUT2 PM12=1 10 PM12=0 0x OUT2 OUT3 PM23=1 IN3 PM23=0 OUT6 CH5 IN4 PM56=1 PM56=0 OUT7 OUT8 PM78=1 PM78=0 IS10[1:0] 11 IN10 10 0x OUT10 CH9 PM910=1 PM910=0 OUT 10 Logic_Output_Control_CORE10.vsd Figure 32 Data Sheet Logic Output Control Block Diagram TLE8110ED 51 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.1 CMD - Commands By using the Address Range CMD[14:12] = ’000’ commands can be send to the device. The feedback of the commands is provided in the next SPI SO frame. Details about the Feedback on each command is described in the Chapter 12.3.1.1. It is possible to perform per each Communication Frame ONE command out of Group-A (see following description of the commands) and ONE command out of Group-B at the same time. Performing more then one Command of one Group is not possible. For the case, this happens, the commands are ignored. Overview Commands CMD Command Register S_SI Serial Input CMD 11 10 9 8 7 6 5 4 3 2 1 0 RSD RSDS RPC RINx CSDS NOP 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 Command description Field Command Type Function Command Bits Group-B (Bits [7:4]). All other bit combinations are not valid. Command will be ignored then. NOP 0000 W NOP - no operation A frame with 0000H will be returned. CMD_CSDS 0001 W CMD_CSDS - Command: Clear Short Diagnosis and Device Status Clear the Device Status information. Performing this Clear Command clears the Information in the Reset and Communication Error Information as long as the incident is not present anymore. If the incident is still present, the related Bits remain setted. Performing this command does NOT clear the Diagnosis Registers. The Diagnosis Information is cleared by the Clear Diagnosis Commands (see Chapter 12.3.2). SO returns a Frame with 0000H after performing CMD_CSDS or in case this command is carried out together with a command out of Group-A, the feedback is according the Group-A command. Command Bits Group-A (Bits [3:0]). All other bit combinations are not valid. Command will be ignored then. CMD_NOP 0000 W NOP - no operation A frame with 0000H will be returned. CMD_RINx 1000 W CMD_RINx - Command: Return Input Pin INx -Status See Chapter 12.3.1.4. CMD_RPC 0100 W CMD_PRC - Command: Return Pattern Check See Chapter 12.3.1.3. Data Sheet 52 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Command description Field Command Type Function CMD_RSDS 0010 W CMD_RSDS - Command: Return Short Diagnosis and Device Status See Chapter 12.3.1.2. CMD_RSD 0001 W CMD_RSD - Command: Return Short Diagnosis See Chapter 12.3.1.1. 12.3.1.1 CMD_RSD - Command: Return Short Diagnosis The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis within one SO Feedback Frame. The data to be send is latched at the end of the command frame. CMD_RSD S_CS S_SI W CMD_RSD xxxx R/W xxxx R/W S_SO dept. of previous R/W SD xxxx SPI_Protocol_ CMD_RSD.vsd Figure 33 SPI Feedback on CMD_RSD CMD_RSD S_SO Serial Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR 0 0 0 0 0 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 Response description Field Bits Type Description - - - SD1-10 Short Diagnosis 0 Normal Operation, 1 Each SD-Bit contains the NAND-operated Diagnosis Error of each related Channel. Details can be read in diagnosis registers. SD is returned after each Write Cycle to any of the writable registers. Data Sheet 53 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.1.2 CMD_RSDS - Command: Return Short Diagnosis and Device Status The Command CMD_RSD offers the possibility to read out the OR-operated “short”-Diagnosis and the device Status - such as Reset-Information and Communication Error - within one SO Feedback Frame. The data to be send is latched at the end of the command frame. CMD_RSDS S_CS S_SI W CMD_RSDS R/W xxxx R/W xxxx S_SO dept. of previous R/W SDS xxxx SPI_Protocol_CMD_RSDS.vsd Figure 34 Data Sheet SPI Feedback on CMD_RSDS 54 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Behaviour of SDS 3 and SDS 4 in relation to RST , EN, VDD, VCC and CMD .CSDS SDS3 VCC or... RST SDS4 EN=1 SDS3 0 1 0 CMD.CSDS VCC or... RST SDS4 0 1 0 CMD.CSDS VDD SDS4 0 SDS4 EN=0 1 1 0 CMD.CSDS VCC or... RST SDS4 0 0 0 CMD.CSDS VDD SDS4 0 0 0 SDS4 EN=01 0 CMD.CSDS EN SDS4 0 1* CMD.CSDS 0 * During EN = 0, the device internal VDD supply is disabled in order to fulfill low quiescent current requirements. After the transition from EN=0 to 1, the SDS4 will detect under voltage (it is set SDS4=1) until the clear command CMD.CSDS it sent (SDS4=0). SDS3_4_behaviour.vsd Figure 35 Data Sheet Behaviour of SDS3, 4 55 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device CMD_RSDS S_SO Serial Output 15 14 13 12 11 10 9 8 PAR 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 SDS8 SDS7 SDS6 SDS5 SDS4 SDS3 SDS2 SDS1 Response description Field Bits Type Description - [7:0] - SDS - Short Diagnosis and Device Status - 0 - SDS1 - Diagnosis Error in Channel 1 to 6 0 Normal Operation, 1 Diagnosis failure. - 1 - SDS2 - Diagnosis Error in Channel 7 to 10 0 Normal Operation, 1 Diagnosis failure. - 2 - SDS3 - Under Voltage on VCC (Digital Supply Voltage) See Figure 35. - 3 - SDS4 - Under Voltage on VDD (Analogue Supply Voltage) See Figure 35. - 4 - SDS5 - Modulo Error Counter 0 Normal Operation, 1 Diagnosis failure. - 5 - SDS6 - Previous Communication Error - Encoded Command Ignored 0 Normal Operation, 1 Previous Communication Error - Encoded Command ignored. - 6 - SDS7 - not used = ’0’ Always ‘0’. - 7 - SDS7 - not used = ’0’ Always ‘0’. 12.3.1.3 CMD_RPC - Command: Return Pattern Check The Command CMD_RPC offers the possibility to get returned the previous Command to check if the communication works well. The data to be send is latched at the end of the command frame. Data Sheet 56 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device CMD_RPC S_CS S_SI W CMD_RPC xxxx R/W xxxx R/W S_SO dept. of previous R/W CMD_RPC xxxx SPI_Protocol_CMD_RPC.vsd Figure 36 SPI Feedback on CMD_RPC CMD_RPC S_SO Serial Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR =0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 Response description Field Bits Type Description - - - CMD_RPC is returned 12.3.1.4 CMD_RINx - Command: Return Input Pin (INx) - Status The Command CMD_RINx offers the possibility to read out the actual status of the Input Pins. This command allows to check the correct communication on the INx Pins. The data to be send is latched at the end of the command frame. Data Sheet 57 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device CMD_RINx S_CS S_SI W CMD_RINx R/W xxxx R/W xxxx S_SO dept. of previous R/W INx xxxx SPI_Protocol_CMD_RINx.vsd Figure 37 Data Sheet SPI Feedback on CMD_RINx 58 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device OUT1 Control Logic IN1 OUT2 IN2 OUTn INx Temporal INx Register latched by CMD_PINx and CS High-to-Low transition Latch on CS Transfer on CS to SPI-SO-Register CS CMD_RINx SI RINx SO Figure 38 INx_readout.vsd Read-out of INx Pins CMD_RINx S_SO Serial Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR 0 0 0 0 0 IN10 IN9 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 Data Sheet 59 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Response description Field Bits Type Description - - - INx Input Pin Status The Status of the INx Pins is read out at the moment of CS High-toLow transition. Details see Figure 38. 0 INx = Low corresponding OFF 1 INx = High corresponding ON 12.3.2 DCC - Diagnosis Registers and compactCONTROL The DCC - Diagnosis and Compact Control Set allows to read out and clear the Diagnosis Registers. Additionally this Command set offers the possibility to proceed with a compactCONTROL Mode using DMS Diagnosis Mode Set and OPS - Output Pin Set Commands. This compactCONTROL Mode offers the possibility to Control the device with lowest work load on the micro controller side. If any other pattern then the defined commands is recieved on S_SI, the command is ignored and rated as a Communication Error. In this case, this incident is reported in SDS (Chapter 12.3.1.2). If an Error in the Output Channels is detected by the diagnosis circuit, the result is latched in the diagnosis registers related to each channel. The Diagnosis Register is not deleted, when it is just read out. The Diagnosis Register byte can only be cleared by using the appropriated command. In this case, the complete Register Bank is cleared. When issuing a Diagnosis Register Clear command (DRxCL or DMSCL), the idle time tDidle needs to elapse, from the CS low-to-high transition of the clear command, before the register content is effectively cleared (Figure 39); This time has to be taken into account when trying to read the Diagnosis register content after a clear, see Chapter 11.3 for tDidle defintion. After an overcurrent entry is stored in the diagnosis register (OC), the idle time tOCidle needs to elapse before a clear command can effectively clear the entry; if trying to clear the Diagnosis register after an OCT entry is read (Figure 39), this time has to be taken into account starting from the CS high-to-low transition of the previous read command, see (Chapter 11.3) for tOCidle defintion. Data Sheet 60 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Diagnosis Clear-to-Read idle time (tDidle) tDidle S_CS t > tDidle S_SI DRxCL/DMSCL DRx Clear Diagnosis Read Diagnosis Cleared diagnosis can be read Diagnosis gets cleared t Diagnosis Overcurrent -to-Clear idle time ( tOCidle ) tOCidle S_CS t > tOCidle S_SI DRx DRxCL/DMSCL Read Diagnosis Clear Diagnosis Effective Diagnosis Clear OCT detected OCT can be cleared t Diagnosis Idle Times Figure 39 Diagnosis idle times DCC Diagnosis Registers and Compact Control S_SI Serial Input DCC 11 10 9 8 7 6 5 4 3 2 1 0 DRA DRB DRACL DRBCL DMSCL/OPSx DMS1/OPSx DMS2/OPSx DMS3/OPSx DMSx/OPS1 DMSx/OPS2 DMSx/OPS3 DMSx/OPS4 DMSx/OPS5 DMSx/OPS6 DMSx/OPS7 DMSx/OPS8 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 DMSx DMSx DMSx DMSx DMSx DMSx DMSx DMSx 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Data Sheet OPSx OPSx OPSx OPSx 0 0 0 0 0 0 0 1 61 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Command description Field Bits Type Function DCC_DRA [11:0] W DRA - Diagnosis Register A (see Chapter 12.3.2.1) Read out Diagnosis Register A. Return the contents in the next SPI frame (see Chapter 12.3.2.2). DCC_DRB [11:0] W DRB - Diagnosis Register A (see Chapter 12.3.2.1) Read out Diagnosis Register B. Return the contents in the next SPI frame (see Chapter 12.3.2.2). DCC_DRACL [11:0] W DRACL - Diagnosis Register A Clear Clear the contents of the Diagnosis Register A. Return the content present before the clear in the next SPI Frame. If the Diagnosis Error Remains, the Information remains (see Chapter 12.3.2.2). DCC_DRBCL [11:0] W DRBCL - Diagnosis Register B Clear Clear the contents of the Diagnosis Register B. Return the content present before the clear in the next SPI Frame. If the Diagnosis Error Remains, the Information remains (see Chapter 12.3.2.2). DCC_DMSCL [11:8] W DMSCL/OPSx - Diagnosis Mode Set, Clear / Output Pins Set On sending this command, the diagnosis registers DRA, DRB as well as the “virtual” Diagnosis Output Registers DO[7:0] (see Chapter 12.3.2.3) are cleared. Output Pin Settings are done according the content of OPSx. Returns the contents of cleared DR2 on SO in the 2nd byte of the actual communication frame and the Output Pin Feedback in the 1st Byte of the next frame (see Chapter 12.3.2.3). DCC_DMS1 [11:8] W DMS1/OPSx - Diagnosis Mode Set, Register1 / Output Pins Set On sending this command, the diagnosis registers DR1 is selected. Output Pin Settings are done according the content of OPSx. Returns the contents of DR1 on SO in the 2nd byte of the actual communication frame and the Output Pin Feedback in the 1st Byte of the next frame (see Chapter 12.3.2.3). DCC_DMS2 [11:8] W DMS2/OPSx - Diagnosis Mode Set, Register2 / Output Pins Set On sending this command, the diagnosis registers DR2 is selected. Output Pin Settings are done according the content of OPSx. Returns the contents of DR2 on SO in the 2nd byte of the actual communication frame and the Output Pin Feedback in the 1st Byte of the next frame (see Chapter 12.3.2.3). DCC_DMS3 [11:8] W DMS3/OPSx - Diagnosis Mode Set, Register3 / Output Pins Set On sending this command, the diagnosis registers DR3 is selected. Output Pin Settings are done according the content of OPSx. Returns the contents of DR3 on SO in the 2nd byte of the actual communication frame and the Output Pin Feedback in the 1st Byte of the next frame (see Chapter 12.3.2.3). Data Sheet 62 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Command description Field Bits Type Function DCC_DMSx/ OPSx [7:0] W DMSx/OPS1 - Diagnosis Mode Set x/ Output Pins Set Command 1 On sending this command, the diagnosis register is selected according DMSx. The Output Pins of Channel 7-10 are set according the following definitions. The OPSx are commands, no register. The commands are controlling the contents of ISA, ISB and OUTx. OPS[7:0] - Output Pin Set: 0000 0001: CH7 input select, 1: parallel* / 0: Serial 0000 0010: CH8 input select, 1: parallel* / 0: Serial 0000 0100: CH9 input select, 1: parallel* / 0: Serial 0000 1000: CH10 input select, 1: parallel* / 0: Serial 0001 0000: CH7 output set, 1: ON / 0: OFF 0010 0000: CH8 output set, 1: ON / 0: OFF 0100 0000: CH9 output set, 1: ON / 0: OFF 1000 0000: CH10 output set, 1: ON / 0: OFF (*parallel controlled by INx) Sending OR operated combinations of above listed options (only OPSx) are possible in order to control more then one channel at the same time. If parallel mode Mode is selected (in “input select”), the serial settings (in “output select”) are ignored. In parallel Mode, the selected Channels are controlled via INx Pins. The default setting of ISB corresponds the command OPS[7:0] = xxxx 1111b. (parallel mode, status of the Outputs according signal on INx). Returns the contents the selected DRx register on SO in the 2nd byte of the actual communication frame and the Output Pin Feedback [OPF] in the 1st Byte of the next frame (see Chapter 12.3.2.3). 12.3.2.1 DRx - Diagnosis Registers Contents DRA[1:0]x / DRB[1:0]x Diagnosis Register CHx Bank A and Bank B 11 10 9 8 Reset value 0000 0000 0000B = 000H 7 6 5 4 3 2 1 0 DRA[1]6 DRA[0]6 DRA[1]5 DRA[0]5 DRA[1]4 DRA[0]4 DRA[1]3 DRA[0]3 DRA[1]2 DRA[0]2 DRA[1]1 DRA[0]1 11 10 9 8 0 0 0 0 Data Sheet 7 6 5 4 3 2 1 0 DRB[1]10 DRB[0]10 DRB[1]9 DRB[0]9 DRB[1]8 DRB[0]8 DRB[1]7 DRB[0]7 63 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Field Bits Type Function DRA[1:0]x / DRB[1:0}x [1:0] R DRA[1:0]x / DRB[1:0]x DRn[1]x/DRn[0]x = 11 no Error DRn[1]x/DRn[0]x = 10 Over Load, Shorted Load, Over temperature in ON-Mode DRn[1]x/DRn[0]x = 01 Open Load in OFF-Mode DRn[1]x/DRn[0]x = 00 Short to GND in OFF-Mode default DRx[1:0] = 11B A new error on the same channel will overwrite older information. The diagnosis information which is returned by SO is latched when CS makes a High-to-Low transistion of the frame which sends out the register. 12.3.2.2 DRx - Return on DRx Commands x_DRx S_CS S_SI W x_DRx xxxx R/W xxxx R/W S_SO dept. of previous R/W DRx xxxx SPI_Protocol_x_DRx.vsd Figure 40 SPI Feedback on x_DRx commands DRx Return on DRx Commands S_SO Serial Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAR 0 0 1 DRx [1]x DRx [0]x DRx [1]x DRx [0]x DRx [1]x DRx [0]x DRx [1]x DRx [0]x DRx [1]x DRx [0]x DRx [1]x DRx [0]x Response description Field Bits Type Description - - - DRx contents 0 no diagnosis error 1 diagnosis error Data Sheet 64 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.2.3 DMSx/OPSx - Diagnosis Mode Set / Output Pin Set Commands Protocol Each Cycle where a serial data or command frame is sent to the Serial Input [SI] of the SPI interface, a data frame is returned immediately by the Serial Output [SO]. The content of the SO frame is dependent of the previous command which has been sent to SI and the content of the actual content of SI: The first Byte send by S_SI controls the content of the second byte actual returned by S_SO. The second Byte send by S_SI controls the first byte in S_SO of the next frame (see Figure 41). S_CS S_SI S_SO DMSx OPSx Upper Byte Lower Byte Upper Byte Lower Byte Upper Byte DO OPF Lower Byte Upper Byte Lower Byte SPI_Protocol_Short_Mode.vsd Figure 41 Data Transfer in diagnosis and Compact Control DMSx/OPSx Diagnosis Mode Set/ Output Pin Set Commands S_SI Serial Input 15 14 13 12 11 10 9 8 7 Diagnosis Mode Set DMS [4:0] Data Sheet 0 0 1 5 4 Serial mode selected - - 3 2 1 0 Output Pin Set OPS[7:0] - 0 6 - - Parallel or Serial mode CH10: CH9: CH8: CH7: 0= 0= 0= CH10: CH9: CH8: CH7: 0 = 1:ON 1:ON 1:ON 1:ON serial serial serial serial 1= 1= 1= 0:OFF 0:OFF 0:OFF 0:OFF 1 = par. par. par. par. 65 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device DMSx/OPSx Diagnosis Mode Set/ Output Pin Set Commands S_SO Serial Output 15 14 13 12 11 10 9 8 7 6 Output Pin Set Feedback OPF[7:0] 5 4 3 2 1 0 1 0 Diagnosis Output DO[7:0] Diagnosis Output Registers DO[7:0] 7 Diag Register-1 Diag Register-2 6 5 4 3 2 DR4[1] DR4[0] DR3[1] DR3[0] DR2[1] DR2[0] DR1[1] DR1[0] DR1NA DR3NA 1 1 DR6[1] DR6[0] DR5[1] DR5[0] DR10 DR10 [1] [0] DR9[1] DR9[0] DR8[1] DR8[0] DR7[1] DR7[0] Diag Register-3 Field Bits Type Description DO[7:0] [7:0] R DO[7:0] - Diagnosis Output Contents according settings of DMS[4:0]. Returned within the same frame as the pointer is send. DRx[1:0] definitions: see Chapter 12.3.2.1. DO[7:6]Diag [7:6] Register-2 R DO1NA: NAND-operated diagnosis of Diag Register-1 DO3NA: NAND-operated diagnosis of Diag Register-3 0 no diagnosis error is stored in the related Diag Register, 1 at least one diagnosis error is stored in the related Diag Register. Output Pin Feedback OPF[7:0] 15 14 13 12 11 10 9 8 OPF[7] OPF[6] OPF[5] OPF[4] OPF[3] OPF[2] OPF[1] OPF[0] Data Sheet 66 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device Field Bits Type Description OPF[7:0] [15:8] R OPF[7:0] - Output Pin Feedback Principally, OPF can return the previously send OPS word and the IN 10:7 -pin settings, dependent serial/ parallel-setting of OPS: • If Serial Mode is selected by one or more OPS[3:0]-bits, the related OPF[7:4]-bits are returning the settings of OPS[7:4], send at the previous frame, • if Parallel Mode is selected by one or more OPS[3:0]-bits, the related OPF[7:4]-bits are returning the condition available at the related IN 10:7 Pins at the moment of S_CS high-to-low transition. A mix of both modes is possible and depends on the channel related settings. Data Sheet 67 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.3 OUTx - Output Control Register CHx The Output Control Register OUTx consists of 10 Bits to control the Output Channel. Each Bit switches ON/OFF the related Channel. OUTx becomes only active when ISx[1:0] = 0x. For details refer to Chapter 12.3.4. OUTx DATA Output Control Register CHx 11 10 9 8 7 6 1 1 OUT10 OUT9 OUT8 OUT7 Reset value 1100 0000 0000B = C00H 5 4 3 2 OUT6 OUT5 OUT4 OUT3 1 0 OUT2 OUT1 Field Bits Type Description OUTx[9:0] [9:0] R/W Data - OUTx[9:0] OUTx = 0 According Channel is switched OFF, OUTx = 1 According Channel is switched ON. Default (all channels OFF) OUT[9:0] = 00 0000 0000B = 000H. R/W Data - OUTx[11:10] Bits are set to OUT[11:10] = 1. OUTx[11:10] [11:10] Data Sheet 68 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.4 ISx - INPUT or Serial Mode Control Register, Bank A and Bank B The INPUT or Serial Control Register [ISx[1:0] ] allows to define the way of controlling the Output Channels. There are 4 setting options possible. 1. Standard Serial Control: The related Output Channel is set according the content of the OUTx Register. (Chapter 12.3.3). 2. A further possibilty is the control by the Input Pins. 3. The settings of the Parallel Mode Register PMx[0] (see Chapter 12.3.5). 4. Additionally possible is the AND operation between the setting of the OUTx register and the PWM signal at the INPUT Pin. ISAx Command INPUT or Serial Mode Control Register Bank A 11 10 9 IS6 8 7 IS5 Reset Value: 1010 1010 1010B = AAAH 5 4 3 2 6 IS4 IS3 1 IS2 0 IS1 Field Bits Type Description ISx[1:0] [11:0] R/W Command - ISx[1:0] 0x: Serial Mode - The Channel is set ON/OFF by OUTx, 10: INPUT Mode - CHx ON/OFF according INx, 11: AND operate Mode INx with OUTx -> CHx ON if OUTx & INx = 1, Default all channels ISx[1:0] = 10B. ISBx Command INPUT or Serial Mode Control Register Bank B 11 10 9 8 0 0 0 0 7 Reset Value: 0000 1010 1010B = 0AAH 5 4 3 2 6 IS10 IS9 IS8 1 0 IS7 Field Bits Type Description ISx[1:0] [7:0] R/W Command - ISx[1:0] 0x: Serial Mode - The Channel is set ON/OFF by OUTx, 10: INPUT Mode - CHx ON/OFF according INx, 11: AND operate Mode INx with OUTx -> CHx ON if OUTx & INx = 1, Default all channels ISx[1:0] = 10B. Data Sheet 69 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.5 PMx - Parallel Mode Register CHx The Parallel Mode Register PMx[1] allows to “inform” the device about externally parallel connected output channels. If a PMx bit is set, the “lower” related Input Channel controls the indicated Output Channels to achieve best possible matching and according to that highest efficiency of both channels. Additionally to that, the CLAMPsafe feature allows high matching during clamping. PMx Command Parallel Mode Register CHx; Reset Value: 0000 0000 0000B= 000H 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 PM910 PM89 PM78 PM56 0 PM34 PM23 PM12 Field Bits Type Description PMx [11:8] R/W 0 PMx [7:0] R/W PMx - Parallel Mode Bit 0 Direct Mode, 1 Parallel Mode of Channel 1 with x+1. Default PMx[0] = 0. Controlling Parallel Mode is possible between Channel 1 to 4, 5 to 6, 7 to 10. In between the groups, no parallel mode is supported but possible. In case Parallel Mode is chosen and a diagnosis error at only one of the channels is detected, the according diagnosis bit is set. This information mismatch can be caused by tolerance related inbalance of the channels connected together in parallel mode. The diagnosis bits should be or-operated by the Micro Controller side. Data Sheet 70 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.3.6 DEVS - Device Settings The Register allows additional Device settings. For details refer also to the Chapter “Electrical Characteristics”. The Diagnosis Current Control register allow to select between different Diagnosis Modes. The Diagnosis Currents can be switched off to avoid glowing of any connected LEDs. DEVS Command Device Settings 11 10 9 8 7 6 RCP DBT2 DBT1 0 0 0 Reset Value: 0000 0000 0111B = 007H 5 4 3 2 0 0 0 DCC10 1 0 DCC9 DCC18 Field Bits Type Description RCP 11 R/W RCP - Reverse Current Protection 0 disabled, 1 reverse current comp is enabled (valid for all Channels). Default RPC = 0. DBT[2:1] [10:9] R/W DBT2,1 - Diagnosis Blind Time Channel 7 to 10 0,0 standard Filter Time of typ. 150μs, 1,0 standard Filter Time of typ. 150μs, 0,1 OFF-state diagnosis Blind Time of typ. 2.5ms, 1,1 OFF-state diagnosis Blind Time of typ. 5ms. DEVS[7:5] [7:5] R/W not used. Set to 0. DEVS[4:3] [4:3] R/W 0 DCCx [2:0] R/W DCCx - Diagnosis Current Control DCC18 switching ON/OFF diagnosis current of CH1-8, DCC9 switching ON/OFF diagnosis current of CH9, DCC10 switching ON/OFF diagnosis current of CH10. 0 OFF-State Diagnosis (Detection of open load and short to GND) of CHx is switched OFF. ON state diagnosis (over current and over temperature detection) is still active. Diagnosis Current is switched OFF. 1 OFF-State (Detection of open load and short to GND) and ONState (over current and over temperature detection) Diagnosis of CHx switched ON, Diagnosis Current is switched ON. Default DCC = 1. Data Sheet 71 Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Package Outlines 13 Figure 42 Package Outlines PG-DSO-36-72 Exposed Pad Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a Green Product. Green Products are RoHS compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Floating Expose pad The expose pad of TLE8110ED is floated. It is highly recommended to connect the expose pad to GND pins externally. For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 72 Dimensions in mm Rev. 1.1 2021-04-30 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Revision History 14 Table 17 Revision History Revision History TLE8110ED Revision History: 2021-04-30 , Rev. 1.1 Rev. 1.1 Rev. 1.0 Data Sheet • P_4.3.2: Parameter Junction to ambient added • P_8.2.2/P_8.2.6: Diagnosis current units updated (mA to µA) • Chapter 13, Package Outlines: Figure 42 updated Final Datasheet 73 Rev. 1.1 2021-04-30 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-04-30 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? 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