OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Features
•
•
•
•
•
•
•
•
•
Integrated PMOS and NMOS complementary output bridge with 2.5 A
current capability
Integrated gate drivers
Single control input with an integrated dead time logic for optimized
control and high efficiency
Output current sensing
Output current limitation
Overtemperature protection
Low quiescent current
No external dead time adjustment required
Green Product (RoHS compliant)
Potential applications
Companion for the OPTIREG™ PMIC TLF3558xxxx for core voltage regulation of AURIX™ TC3xx microcontroller in:
• Electric power steering
• Battery management
• Inverter applications
• Engine management
• Domain control
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The OPTIREG™ PMIC TLF11251LD is a 2.5 A half bridge with integrated driver and level shifter. It also contains
a high side P-channel MOSFET and a low side N-channel MOSFET in a single package. The integrated level
shifting stage allows for conversion of the input logic signals to the supply voltage level of the gate drivers. The
input signal levels are CMOS compatible. The level shifter and the gate driver provide a dead time generation
to simplify the interface with the embedded core voltage regulator of the AURIX™ TC3xx microcontroller. The
low propagation delay allows for use in closed loop control applications with limited requirements for timing.
The output stage allows for a high switching frequency. The TLF11251LD integrates protection features against
overcurrent at the high side MOSFET and at the low side MOSFET as well as against overtemperature events.
Internal power-on reset releases the digital logic and ensures its operation for the supply voltage within the
specified range.
Datasheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com/OPTIREG-PMIC
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Description
Type
Package
Marking
TLF11251LD
PG-TSON-10
11251
Datasheet
2
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
3.3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.2.1
4.4.2.2
4.4.3
4.4.3.1
4.4.3.2
Block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logical inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional description control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical characteristics control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional description output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical performance characteristics output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Functional description undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical characteristics undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional description overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional description overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Electrical characteristics overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
5.1
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Datasheet
3
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Table of contents
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Datasheet
4
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block diagram
1
Block diagram
Figure 1
Block diagram
Datasheet
5
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Pin configuration
2
Pin configuration
2.1
Pin assignment
Figure 2
Datasheet
SW
1
10
VS
SW
2
9
VS
PGND
3
8
PGND
GND
4
7
VCC
LSCON
5
6
PWM
Heat sink
Pin configuration
6
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Pin configuration
2.2
Pin definitions and functions
Pin
Symbol
Function
1, 2
SW
Switch node:
Half bridge drains; typically connected to the input of the LC filter in buck circuits
3, 8
PGND
Power ground:
Half bridge low side source
4
GND
Ground;
Logical ground
5
LSCON
Bridge control scheme:
Defines the low side state during PWM input "high".
Switch to "high" enables synchronous control of high side and low side, based on PWM
input state.
Switch to "low" disables low side control.
6
PWM
Control input:
Input for the logical signal that controls the state of the half bridge transistors. Switch to
"high" opens the high side switch and closes the low side switch. Switch to "low" closes
the high side switch and opens the low side switch.
7
VCC
Supply voltage input:
Supply voltage for the PWM and LSCON inputs; typically the same as the supply of
microcontroller output pins.
9, 10
VS
Supply voltage input:
Supply to gate drivers, connected to half bridge high side source.
–
Heat sink
Connect to heat sink area.
Connect to GND and to PGND.
Datasheet
7
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise
specified).
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or condition
Number
Max.
Voltages
Supply voltage VS
VS
-0.3
–
7.0
V
–
P_3.1.1
Supply voltage VCC
Vcc
-0.3
–
7.0
V
–
P_3.1.2
Switch node SW
VSW
-0.3
–
7.0
V
–
P_3.1.3
Input PWM
VPWM
-0.3
–
7.0
V
–
P_3.1.4
Input LSCON
VLSCON
-0.3
–
7.0
V
–
P_3.1.5
Continuous drain current high
side
IDHS
-2.5
–
–
A
PWM = off
P_3.1.6
Continuous drain current low
side
IDLS
–
–
2.5
A
PWM = on
P_3.1.7
Pulsed drain current high side
IDHS
-4.4
–
–
A
Valid during active
P_3.1.8
overcurrent protection
Pulsed drain current low side
IDLS
–
–
4.4
A
Valid during active
P_3.1.9
overcurrent protection
Junction temperature
Tj
-40
–
150
°C
–
P_3.1.10
Storage temperature
Tstg
-55
–
150
°C
–
P_3.1.11
ESD susceptibility all pins
VESD
-2
–
2
kV
2) HBM
P_3.1.12
ESD susceptibility all pins
VESD
-500
–
500
V
3) CDM
P_3.1.13
V
3) CDM
P_3.1.14
Currents
Temperatures
ESD susceptibility
ESD susceptibility (corner pins)
VESD
-750
–
750
Notes:
1
2
3
Not subject to production test, specified by design.
ESD susceptibility, Human Body Model (HBM) according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF).
ESD susceptibility, Charged Device Model (CDM) according to JEDEC JESD22-C101.
Datasheet
8
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
General product characteristics
1.
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods of time may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions
are not designed for continuous repetitive operation.
2.
3.2
Functional range
Table 2
Functional range
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or condition
Number
Max.
Supply voltage range VS
VS,nom
3.5
–
7.0
V
–
P_3.2.1
Supply voltage range VCC
VCC,nom
2.35
–
7.0
V
–
P_3.2.2
-120
–
120
V/ms
4)
P_3.2.3
Supply voltage VCC
transient slew rate
dVCC/dt -120
–
120
V/ms
4)
P_3.2.4
Junction temperature
Tj
-40
–
150
°C
–
P_3.2.5
Supply current total,
normal operation
IC,norm
–
–
35
mA
PWM input @
1.8 MHz
P_3.2.9
Supply current total, no
switching
IC,ns
–
200
–
µA
VS < 5.8 V;
Vcc < 5.1 V;
Tj < 85°C
P_3.2.10
Supply voltage VS transient dVS/dt
slew rate
Note:
4
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the electrical characteristics
table.
Not subject to production test, specified by design.
Datasheet
9
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
General product characteristics
3.3
Thermal resistance
Table 3
Thermal resistance5)
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
condition
Number
Max.
Junction to case top, high side
RthJCT(HS)
51.6
–
57.0
K/W
–
P_3.3.1
Junction to case top, low side
RthJCT(LS)
64.5
–
71.2
K/W
–
P_3.3.2
Junction to case bottom, high
side
RthJCB(HS)
6.3
–
6.9
K/W
–
P_3.3.3
Junction to case bottom, low side RthJCB(LS)
9.4
–
10.4
K/W
–
P_3.3.4
Junction to ambient
–
54.5
–
K/W
6)
P_3.3.5
Note:
5
6
RthJA
This thermal data was generated in accordance with JEDEC JESD51 standards. For more information
visit www.jedec.org.
Not subject to production test, specified by design.
Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the
product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers
(2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first
inner copper layer.
Datasheet
10
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4
Block description and electrical characteristics
The device simplifies the interface of microcontroller control outputs to the half bridge.
4.1
Logical inputs
A single PWM input controls the state of the half bridge MOSFETs. The inverted logical scheme translates the
PWM input state to the gate signal shifted to the output supply level, thus the device switches the high side
MOSFET off during PWM logical on-state, and it switches them on during PWM logical off state. The built-in
dead time control circuitry prevents a shoot-through condition over the MOSFET bridge and improves system
efficiency while used in buck power conversion circuits. No external dead time adjustment is required.
In addition to the PWM input, the LSCON input determines the low side MOSFET control scheme and allows
for both synchronous as well as asynchronous operation in buck converter applications. Logical off state at the
LSCON input switches off the low side MOSFET independently of the PWM input signal, so that the device only
controls the high side MOSFET.
A permanent logical on state at the LSCON input allows both high side and low side operation according to PWM
input state with the internal dead time generation. If such operation is required, then the LSCON input can be
pulled-up or connected directly to the VCC supply rail.
The device interprets a toggling input signal at LSCON as a control request for synchronous low side and
high side MOSFET switching. In this case the device generates dead time internally in accordance with
the PWM input timing. Frequency detection at LSCON inputs detect toggling input signals within the
acceptable range referred to as tdet.
Table 4
Switching states
LSCON
PWM
High side MOSFET
Low side MOSFET
On
7) On
Off
On
On
8) Off
On
Off
Off
On
Off
Off
Off
Off
On
Off
Toggling between on and off9)
On
Off
On
Off
On
Off
Toggling between on and off
stopped10)
(< tfil)
On
Off
On
Off
On
Off
Toggling between on and off
stopped
(> tfil); LSCON: on
On
Off
On
Toggling between on and off
stopped
Off
On
Off
7
8
9
10
On: "high"
Off: "low"
Toggling between on and off: The device detects switching on and off at a frequency corresponding to the
detection range tdet at the LSCON input.
Toggling between on and off stopped: After the toggling between on and off, the device detects a
permanent on or off state.
Datasheet
11
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
Table 4
Switching states (continued)
LSCON
PWM
High side MOSFET
Low side MOSFET
Toggling between on and off
stopped
(> tfil); LSCON: off
On
Off
Off
Toggling between on and off
stopped
(> tfil); LSCON: off
Off
On
Off
(> tfil); LSCON: on
The switching states in Table 4 are only valid for device input supplies within the operational range and if no
protection feature is active.
If the PWM pin is not connected, then the integrated weak pull-up ensures a defined level.
If an AURIX™ TC3xx microcontroller controls the device, then place an additional pull-down resistor at the
LSCON input to keep the low side MOSFET switched off during power-down, see Application information.
Datasheet
12
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.2
Control parameters
4.2.1
Functional description control parameters
The device provides a high frequency switching capability with a low propagation delay. The input stage and
the drivers can react to fast changing PWM signals and provide a tres resolution to the on-time of the input signal
with a pulse duration longer than tpulse. The "low" state pulse duration is limited to tpulse, min.
The total propagation time tprop is the time from the "low" to "high" edge transition or from the "high"
to "low" edge transition at the PWM input to the SW output level transitions to 10% or 90% of VS supply
level accordingly. The internal dead time generation provides optimal efficiency during switching phases and
performs the state change of the switching node SW within the specified propagation delay.
The device is optimized for a switching frequency in a buck converter application from 0.3 MHz to 2 MHz.
PWM Input
Test circuit
Vs
VIH
tpulse
VIL
Min accepted pulse:
tpulse,min=65ns
15..25 Ohm
PWM
DUT
SW
15..25 Ohm
SW output
GND
PGND
tprop,fe
0.9*Vs
0.1*Vs
Figure 3
Datasheet
tpulse ± |tres|
tprop,re
Control timing diagram
13
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.2.2
Electrical characteristics control parameters
Table 5
Electrical characteristics control parameters
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Unit Note or condition
Number
Max.
Propagation time, PWM
falling edge
tprop,fe
–
–
60
ns
High side drain
connected to
resistive load;
VCC > 3.0 V;
VS > 4.5 V
P_4.2.1
Propagation time, PWM
rising edge
tprop,re
–
–
60
ns
Low side drain
connected to
resistive load;
VCC > 3.0 V;
VS > 4.5 V
P_4.2.2
Minimum pulse width input
tpulse,
65
–
–
ns
11)
P_4.2.3
–
–
3
ns
11)
P_4.2.4
P_4.2.5
P_4.2.6
min
Pulse resolution time
tres
Dead time "high" to "low"
tdead,hl
–
15
–
ns
11)
Dead time "low" to "high"
tdead,lh
–
18
–
ns
11)
LSCON frequency detector
frequency range
fdet,lscon 0.72
–
–
MHz –
LSCON frequency detector
filter time
tfil,lscon
3
–
–
µs
11)
P_4.2.8
Input voltage "high"
VIH
0.67 × Vcc –
–
V
CMOS function
P_4.2.9
Input voltage "low"
VIL
–
–
0.33 × Vcc V
CMOS function
P_4.2.10
Input voltage hysteresis
VIHYS
0.05
–
–
V
–
P_4.2.11
Input capacitance
CIN
–
10
–
pF
11)
P_4.2.12
P_4.2.7
Logic inputs
11
Not subject to production test, specified by design.
Datasheet
14
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.3
Output stage
4.3.1
Functional description output stage
The P-N-channel output half bridge of the device can operate at a switching frequency up to 2 MHz nominal
range, providing very low power dissipation in synchronous buck converter topology. The P-channel MOSFET
used as high side switch eliminates the need for a charge pump circuitry and improves the EMI performance.
The output stage delivers a minimum output current of 2.5 A within the specified voltage and temperature
range.
4.3.2
Electrical characteristics output stage
Table 6
Electrical characteristics output stage
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
On-state resistance high side RONHS
Typ.
Unit
Note or
condition
Number
Max.
–
–
100
mΩ
Tj ≤ 150°C;
Id = -2 A;
Vs = 5.8 V
P_4.3.1
–
–
70
mΩ
12) T
P_4.3.2
j ≤ 85°C;
Id = -2 A;
Vs = 5.8 V
On-state resistance low side
RONLS
–
–
105
mΩ
Tj ≤ 150°C;
Id = 2 A;
Vs = 5.8 V
P_4.3.3
–
–
75
mΩ
12) T
P_4.3.4
j ≤ 85°C;
Id = 2 A;
Vs = 5.8 V
Body diode forward voltage
high side
VDFHS
–
0.67
0.95
V
Ifw = 2 A
P_4.3.5
Body diode forward voltage
low side
VDFLS
–
0.72
0.91
V
Ifw = 2 A
P_4.3.6
12
Not subject to production test, specified by design.
Datasheet
15
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.3.3
Typical performance characteristics output stage
Maximum on-state resistance high side RONHS
(PWM = "low") versus Tj = -40°C, 25°C, 150°C
Datasheet
Maximum on-state resistance low side RONLS
(PWM = "high") versus Tj = -40°C, 25°C, 150°C
16
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.4
Protection functions
The following integrated protection functions prevent the device and the output circuitry from destruction as
well as from operation under unspecified conditions:
•
High side and low side overcurrent detection and limitation
•
Undervoltage shutdown
•
Overtemperature protection
The device reacts within the time specified for each protection feature. This is related to the state change of the
half bridge MOSFETs independent from the PWM input signal. The device performs the input logic reset release
at VS voltage exceeding the minimum functional limit of 3.5 V, where protection functions are also operational.
For the VCC voltage below VCCUV, the output half bridge MOSFETs remain in the off-state and the output switch
node SW is floating.
4.4.1
Undervoltage shutdown
4.4.1.1
Functional description undervoltage shutdown
The device monitors the input supply VCC for undervoltage conditions. If the output voltage drops below the
Vccuv limit, then the device switches off the high side MOSFET and the low side MOSFET, so that the device is
only operational within the specified supply limits. The voltage hysteresis circuitry Vccuvh protects from noise
conditions.
4.4.1.2
Electrical characteristics undervoltage shutdown
Table 7
Electrical characteristics undervoltage shutdown
VS = 3.5 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless
otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
condition
Number
Max.
Undervoltage limit at VCC
supply
Vccuv
1.95
–
2.28
V
VCC falling
P_4.4.2.1
Undervoltage detector
hysteresis
Vccuvh
0.05
–
0.1
V
–
P_4.4.2.2
Undervoltage detector
reaction time
Vuvr
–
–
3
µs
13)
P_4.4.2.3
13
Not subject to production test, specified by design.
Datasheet
17
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.4.2
Overcurrent protection
4.4.2.1
Functional description overcurrent protection
The overcurrent protection works in a cycle-by-cycle limitation mode. If the sensed input drain current exceeds
the peak current limit Ioc, lim during a switching cycle, then the device switches off the high side MOSFET and
the switch node SW current decreases. If the overcurrent protection circuitry is active, then the device limits the
PWM input duty cycle for each cycle.
During startup or with VCC supply power cycle after the logic reset is released, the overcurrent protection
remains inactive for the number of PWM pulses npwm,st to avoid accidental activation due to startup current
overshoot.
Figure 4
Datasheet
Overcurrent protection example
18
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.4.2.2
Electrical characteristics overcurrent protection
Table 8
Electrical characteristics overcurrent protection
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
condition
Number
Max.
Overcurrent sensing limit
Ioc, lim
-4.4
–
-2.6
A
–
P_4.4.3.1
Startup protection inactive,
number of PWM pulses
npwm,st
–
–
5500
–
VCC rising above
VCC,min
P_4.4.3.2
Datasheet
19
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Block description and electrical characteristics
4.4.3
Overtemperature protection
4.4.3.1
Functional description overtemperature protection
If an overtemperature condition TjOT occurs, then the integrated temperature sensor disables the device by
switching off the high side and low side MOSFETs. Only if both the temperature decreases by the hysteresis
temperature dTj and the temperature falls below TjSO, then the MOSFETs resume operation.
4.4.3.2
Electrical characteristics overtemperature protection
Table 9
Electrical characteristics overtemperature protection14)
VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current
flowing into pin (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Unit
Note or
condition
Number
Max.
Overtemperature shutdown
TjOT
175
–
200
°C
–
P_4.4.4.1
Switch-on temperature
TjSO
–
–
165
°C
–
P_4.4.4.2
Overtemperature switch-on
hysteresis
dTj
–
15
–
°C
–
P_4.4.4.3
14
Not subject to production test, specified by design.
Datasheet
20
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Application information
5
Note:
5.1
Application information
The following information is given as an example for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the
device.
Application diagram
In the target application scenario the device is the counterpart for an AURIX™ TC3xx microcontroller for core
voltage generation with the system power supply TLF35584. The device configuration allows connectivity with
the half bridge control output of the microcontroller’s embedded voltage regulator core (EVRC) converter,
which generates the core voltage Vdd. The device only supports power supply topologies that use different
sources for the microcontroller supply domain Vext and the EVRC input VS, expecting different voltage levels. VS
must exceed VCC during startup, in normal operation and during power-down.
Figure 5
Note:
Application diagram
This figure is a simplified example of an application circuit. The function must be verified in the
application.
As soon as VS voltage reaches 3.5 V during power-up, the device releases the internal logic reset. During this
phase the central function logic is operational. Only if VCC is within the specified range, then the device reacts
to the input signals LSCON and PWM as specified. However, the operational VCC voltage minimum is specified at
2.35 V, which allows for early device readiness, even if the microcontroller is not yet operational.
The VGATEP output of the microcontroller controls the PWM signal, while the VGATEN output is connected
to LSCON. The microcontroller typically starts in an open loop mode, controlling only VGATEP and allowing
for fast Vdd voltage ramp-up and startup. After ramp-up time, the EVRC starts to control the high side and
low side MOSFETs of the half bridge. The LSCON input detects this phase with the frequency detector. If the
Datasheet
21
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Application information
microcontroller is switched into power-down mode and if the high side and low side control signals are off,
then the frequency detector recognizes it as a request to set the SW output floating. Therefore add a pull-down
resistor for the LSCON signal in order to limit its possible variation during the power-down phase after the
supply voltage reaches the hard reset limit of the microcontroller.
Figure 6
Start-up and ramp-down example
Table 10 shows the required nominal values of the discrete components for proper operation.
Table 10
Nominal values of discrete components
Component name
Nominal value
Acceptable variation
Note
CVS
10 µF
±30%
Input capacitor
CVDD
22 µF
±30%
Output capacitor
LVDD
3.3 µH
±30% (@ 1.8 MHz)
Output inductor
RLSCON
6.2 kΩ
±20%
LSCON input pull-down
Datasheet
22
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Package information
0.36±0.1
2.58±0.1
1±0.1
3.3±0.1
INDEX MARKING
1.48±0.1
3.3±0.1
0.05
0.5
0.07 MIN.
INDEX MARKING
0.53±0.1
0.25±0.1
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
Figure 7
0.55±0.1
0..0.05
STANDOFF
Package information
0.2±0.1
6
]
PG-TSON-10
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a Green Product. Green Products are RoHS compliant (Pb-free
finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Information on alternative packages
Please visit www.infineon.com/packages.
Datasheet
23
Rev. 1.02
2021-02-05
OPTIREG™ PMIC TLF11251LD
2.5 A half bridge with integrated driver and level shifter
Revision history
Revision history
Revision
Date
Changes
1.02
2021-02-05
Editorial changes
1.01
2021-01-14
Editorial changes
1.0
2020-01-23
Datasheet created
Datasheet
24
Rev. 1.02
2021-02-05
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2021-02-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2021 Infineon Technologies AG
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-Z8F80033844
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event be regarded as a guarantee of conditions or
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With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
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