OPTIREG™ linear TLS850F0TAV50
Low dropout li near voltage regulator
Features
•
Wide input voltage range from 3.0 V to 40 V
•
Fixed output voltage 5 V
•
Output voltage precision ≤ ±2 %
•
Output current capability up to 500 mA
•
Ultra low current consumption typ. 40 µA
•
Very low dropout voltage typ. 70 mV@100 mA
•
Stable with ceramic output capacitor of 1 µF
•
Delayed reset at power-on: 16.5 ms
•
Adjustable reset threshold down to 2.50 V
•
Watchdog with fixed timing and current dependent deactivation: 96 ms, activated at IQ > 5.5 mA
•
Enable, undervoltage reset, overtemperature shutdown
•
Output current limitation
•
Wide temperature range
•
Green product (RoHS compliant)
Potential applications
•
Automotive general ECUs
•
Dashboard and cluster supplies
•
Powertrain and EPS applications
•
Microcontroller supply for safety applications
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The OPTIREG™ linear TLS850F0TAV50 is a high performance very low dropout linear voltage regulator for 5 V
supply in a PG-TO263-7 package.
With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly
suitable for automotive or any other supply systems connected to the battery permanently. The
TLS850F0TAV50 provides an output voltage accuracy of 2 % and a maximum output current up to 500 mA.
Datasheet
www.infineon.com/OPTIREG-linear
1
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
The new loop concept combines fast regulation and very good stability while requiring only one small ceramic
capacitor of 1 µF at the output. At currents below 100 mA the device will have a very low typical dropout
voltage of only 70 mV. The operating range starts already at input voltages of only 3 V (extended operating
range). This makes the TLS850F0TAV50 also suitable to supply automotive systems that need to operate
during cranking condition.
The device can be switched on and off by the enable feature as described in Chapter 4.5.
The output voltage is supervised by the reset feature, including undervoltage reset, delayed reset at power-on
and an adjustable lower reset threshold. More details can be found in Chapter 4.7.
In addition, a watchdog circuit with fixed timing is integrated to monitor the microcontroller‘s operation.
Internal protection features like output current limitation and overtemperature shutdown are implemented
to protect the device against immediate damage due to failures like output short circuit to GND, over-current
and over-temperatures.
External components
An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for
the stability of the regulating circuit. TLS850F0TAV50 is designed to be also stable with low ESR ceramic
capacitors.
Type
Package
Marking
TLS850F0TAV50
PG-TO263-7
850F0V50
Datasheet
2
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin assignment TLS850F0TAV50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions TLS850F0TAV50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical performance characteristics voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical performance characteristics current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical performance characteristics enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical performance characteristics reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standard watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Typical performance characteristics standard watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Datasheet
3
6
6
7
8
32
32
32
32
32
33
34
34
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block diagram
1
Block diagram
I
Q
Current
Limitation
Reset
EN
RADJ
Enable
WI
RO/WO
Bandgap
Reference
Temperature
Shutdown
Watchdog
GND
Figure 1
Datasheet
Block diagram TLS850F0TAV50
4
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Pin configuration
2
Pin configuration
2.1
Pin assignment TLS850F0TAV50
1 2 3 45 6 7
Q
WI
RADJ
GND
RO/WO
EN
I
Figure 2
Pin configuration
2.2
Pin definitions and functions TLS850F0TAV50
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences. See also
Chapter 5.2.1
2
EN
Enable (integrated pull-down resistor)
Enable the IC with high level input signal;
Disable the IC with low level input signal;
3
RO/WO
Reset output / watchdog output (integrated pull-up resistor to Q)
Open collector output;
Leave open if the reset and watchdog function are not needed
4
GND
Ground
5
RADJ
Reset threshold adjustment
Connect to GND to use standard value;
Connect an external voltage divider to adjust reset threshold
6
WI
Watchdog input (integrated pull-down resistor)
Serve Watchdog with trigger input signal (usable for microcontroller monitoring)
7
Q
Output voltage
Connect output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in “Functional range” on Page 7
Heat
Slug
–
Heat slug
Connect to heatsink area;
Connect to GND
Datasheet
5
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
General product characteristics
3
General product characteristics
3.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Number
Test Condition
-0.3
–
45
V
–
P_4.1.1
-0.3
–
7
V
–
P_4.1.3
Input I, Enable EN
Voltage
VI, VEN
Output Q, Reset/watchdog output RO/WO
Voltage
VQ, VRO/WO
Watchdog input WI, Reset threshold adjustment RADJ
Voltage
VWI, VRADJ
-0.3
–
7
V
–
P_4.1.5
Junction temperature
Tj
-40
–
150
°C
–
P_4.1.7
Storage temperature
Tstg
-55
–
150
°C
–
P_4.1.8
VESD
-2
–
2
kV
2)
HBM
P_4.1.9
CDM
P_4.1.10
CDM
P_4.1.12
Temperatures
ESD absorption
ESD susceptibility to GND
ESD susceptibility to GND
VESD
ESD susceptibility pin 1, 7 (corner pins) VESD1,7
to GND
-500
–
500
V
3)
-750
–
750
V
3)
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Note:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Datasheet
6
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
General product characteristics
3.2
Table 2
Functional range
Functional range
Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Min.
Input voltage range
VI
Typ.
VQ,nom + Vdr –
Max.
Unit Note or
Test Condition
40
V
1)
–
P_4.2.1
2)
–
P_4.2.3
Extended input voltage range
VI,ext
3.0
–
40
V
Enable voltage range
VEN
0
–
40
V
–
P_4.2.5
Output capacitor’s
requirements for stability
CQ
1
–
–
µF
3)4)
ESR
ESR(CQ)
–
–
100
Ω
3)
Junction temperature
Tj
-40
–
150
°C
–
1)
2)
3)
4)
Number
–
–
P_4.2.6
P_4.2.7
P_4.2.9
Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.
When VI is between VI,ext,min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
Not subject to production test, specified by design.
The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
Note:
Datasheet
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
table.
7
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
General product characteristics
3.3
Thermal resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 3
Thermal resistance
Parameter
Symbol
Values
Min.
Typ.
Max.
–
3
–
Unit
Note or
Test Condition
Number
K/W
1)
P_4.3.6
K/W
1)2)
2s2p board
P_4.3.7
1)3)
Package version PG-TO263-7
Junction to case
Junction to ambient
RthJC
RthJA
–
21
–
–
Junction to ambient
RthJA
–
75
–
K/W
1s0p board,
footprint only
P_4.3.8
Junction to ambient
RthJA
–
42
–
K/W
1)3)
1s0p board,
300 mm2 heatsink
area on PCB
P_4.3.9
Junction to ambient
RthJA
–
34
–
K/W
1)3)
P_4.3.10
1s0p board,
600 mm2 heatsink
area on PCB
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Datasheet
8
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4
Block description and electrical characteristics
4.1
Voltage regulation
The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal
voltage reference and the pass transistor is driven accordingly.
The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the
internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent
series resistor (ESR) requirements given in “Functional range” on Page 7 have to be maintained. For details,
also see the typical performance graph “Output capacitor series resistor ESR(CQ) versus output current
IQ” on Page 13. As the output capacitor also has to buffer load steps, it should be sized according to the
application’s needs.
An input capacitor CI is recommended to compensate line influences. In order to block influences like pulses
and HF distortion at input side, an additional reverse polarity protection diode and a combination of several
capacitors for filtering should be used. Connect the capacitors close to the component’s terminals.
In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures
almost no output voltage overshoots during start-up, mostly independent from load and output capacitance.
Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is
limited and the output voltage decreases.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions
(e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the
regulator restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed.
However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly
reduce the IC’s lifetime.
S upply
II
I
Q
Current
Lim itation
Reset
EN
CI
WI
RO /W O
RADJ
E nable
VI
B andgap
Reference
Tem perature
S hutdown
Regulated
O utput V oltage
IQ
C
VQ
ES R
LO A D
CQ
W atchdog
G ND
Figure 3
Datasheet
Voltage regulation
9
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
V
VQ,nom
VI,ext,min
VI
Vdr
VQ
t
Figure 4
Datasheet
Output voltage vs. input voltage
10
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Table 4
Electrical characteristics voltage regulator 5 V version
Tj = -40°C to 150°C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note or Test Condition
Number
Output voltage precision
VQ
4.9
5.0
5.1
V
0.05 mA < IQ < 500 mA
5.95 V < VI < 28 V
P_5.1.3
Output voltage precision
VQ
4.9
5.0
5.1
V
0.05 mA < IQ < 200 mA
5.44 V < VI < 40 V
P_5.1.4
Output voltage start-up
slew rate
dVQ/dt
3.0
7.5
18
V/ms VI > 18 V/ms
CQ = 1 µF
0.5 V < VQ < 4.5 V
Output current limitation
IQ,max
501
650
1100 mA
0 V < VQ < 4.8 V
P_5.1.9
Load regulation
steady-state
ΔVQ,load -20
-1.5
5
mV
IQ = 0.05 mA to 500 mA
VI = 6 V
P_5.1.11
Line regulation
steady-state
ΔVQ,line
-25
0
25
mV
VI = 8 V to 32 V
IQ = 5 mA
P_5.1.13
Dropout voltage
Vdr = VI - VQ
Vdr
–
175
425
mV
1)
IQ = 250 mA
P_5.1.16
Dropout voltage
Vdr = VI - VQ
Vdr
–
70
170
mV
1)
IQ = 100 mA
P_5.1.17
Power supply ripple rejection
PSRR
–
59
–
dB
2)
fripple = 100 Hz
Vripple = 0.5 Vpp
P_5.1.18
Overtemperature shutdown
threshold
Tj,sd
151
–
200
°C
2)
Tj increasing
P_5.1.19
Overtemperature shutdown
threshold hysteresis
Tj,sdh
–
15
–
K
2)
Tj decreasing
P_5.1.20
P_5.1.7
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Datasheet
11
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.2
Typical performance characteristics voltage regulator
Typical performance characteristics
Output voltage VQ versus
junction temperature Tj
Dropout voltage Vdr versus
junction temperature Tj
350
IQ = 100 mA
IQ = 100mA
5.15
IQ = 250 mA
300
5.1
250
Vdr [mV]
VQ [V]
5.05
5
200
150
4.95
100
4.9
50
4.85
0
−40
4.8
0
50
Tj [°C]
100
150
Load regulation ΔVQ,load versus
output current change IQ
0
50
Tj [°C]
100
150
Line regulation ΔVQ,line versus
input voltage VI
8
0
Tj = −40 oC
IQ = 5 mA
−2
Tj = 25 oC
6
Tj = 150 oC
−4
4
2
−8
ΔVQ,line [mV]
ΔVQ,load [mV]
−6
−10
−12
0
−2
−14
VI = 6 V
−4
−16
Tj = −40 oC
−18
Tj = 25 oC
−6
o
Tj = 150 C
−20
0
Datasheet
100
200
300
IQ [mA]
400
−8
500
12
10
15
20
VI [V]
25
30
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Output voltage VQ versus
input voltage VI
Power supply ripple rejection PSRR versus
ripple frequency f
80
6
Tj = −40 °C
Tj = 25 oC
Tj = 25 °C
70
Tj = 150 °C
5
IQ = 100 mA
60
4
PSRR [dB]
VQ [V]
50
3
40
30
2
20
1
IQ = 10 mA
CQ = 1 μF
Vripple = 0.5 Vpp
10
0
0
1
2
3
VI [V]
4
5
0
−2
10
6
−1
0
10
1
10
10
2
10
3
10
f [kHz]
Output capacitor series resistor ESR(CQ) versus
output current IQ
Maximum output current IQ versus
input voltage VI
3
1200
10
Unstable Region
1000
2
10
800
10
Stable Region
IQ,max [mA]
ESR(CQ) [Ω]
1
0
600
10
400
VQ = 0 V
−1
10
CQ = 1 μF
−2
10
0.05
Datasheet
Tj = −40 oC
200
Tj = 25 oC
Tj = 150 oC
Tj = 25 oC
1
10
IQ [mA]
100
0
500
13
0
10
20
VI [V]
30
40
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Dropout voltage Vdr versus
output current IQ
500
Tj = 25 oC
450
400
350
Vdr [mV]
300
250
200
150
100
50
0
0
Datasheet
100
200
300
IQ [mA]
400
500
14
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.3
Table 5
Current consumption
Electrical characteristics current consumption
Tj = -40°C to 150°C, VI = 13.5 V (unless otherwise specified)
Typical values are given at Tj = 25 °C
Conditions of other pins: WI = GND
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Current consumption
Iq = II
Iq,off
–
1.3
5
µA
VEN = 0 V; Tj < 105 °C
P_5.3.1
Current consumption
Iq = II
Iq,off
–
–
8
µA
VEN = 0.4 V; Tj < 125 °C
P_5.3.3
Current consumption
Iq = II - IQ
Iq
–
40
52
µA
IQ = 0.05 mA
Tj = 25 °C
Watchdog disabled
P_5.3.4
Current consumption
Iq = II - IQ
Iq
–
62
77
µA
IQ = 0.05 mA
Tj < 125 °C
Watchdog disabled
P_5.3.7
Current consumption
Iq = II - IQ
Iq
–
62
82
µA
1)
P_5.3.11
IQ = 500 mA
Tj < 125 °C
Watchdog enabled
1) Not subject to production test, specified by design
Datasheet
15
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.4
Typical performance characteristics current consumption
Typical performance characteristics
Current consumption Iq versus
output current IQ
Current consumption Iq versus
input voltage VI
200
100
Tj = −40 °C
Tj = 25 oC
90
180
70
140
60
120
Iq [uA]
Iq [μA]
Tj = 150 °C
160
80
50
80
30
60
20
40
10
20
0
Datasheet
100
200
300
IQ [mA]
400
0
500
16
VEN = 5 V
IQ = 50 uA
100
40
0
Tj = 25 °C
5
10
15
20
25
VI [V]
30
35
40
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.5
Enable
The TLS850F0TAV50 can be switched on and off by the enable feature: connect a HIGH level as specified below
(e.g. the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to
shut it down. The enable has a built in hysteresis to avoid toggling between ON/OFF state, if signals with slow
slopes are applied to the EN input.
Table 6
Electrical characteristics enable
Tj = -40°C to 150°C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test Condition Number
High level input voltage
VEN,H
2
–
–
V
VQ settled
P_5.5.1
Low level input voltage
VEN,L
–
–
0.8
V
VQ ≤ 0.1 V
P_5.5.2
Enable threshold hysteresis
VEN,Hy
100
–
–
mV
–
P_5.5.3
High level input current
IEN,H
–
–
3.5
µA
VEN = 3.3 V
P_5.5.4
High level input current
IEN,H
–
–
22
µA
VEN ≤ 18 V
P_5.5.6
Enable internal pull-down
resistor
REN
0.95
1.5
2.6
MΩ
–
P_5.5.7
Datasheet
17
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.6
Typical performance characteristics enable
Typical performance characteristics
Enable input current IEN versus
enable input voltage VEN
Input current IIN versus
input voltage VIN (condition: VEN = 0 V)
50
30
Tj = −40 °C
25
Tj = −40 °C
45
Tj = 25 °C
Tj = 150 °C
Tj = 25 °C
Tj = 150 °C
40
VEN = 0V
35
20
IEN [uA]
IIN [uA]
30
15
25
20
10
15
10
5
5
0
0
10
20
VIN [V]
30
0
40
0
10
20
VEN [V]
30
40
Output voltage VQ versus
time (EN switched ON)
6
5
VQ, VEN [V]
4
3
2
IQ = 100 mA
Tj = −40 °C
Tj = 25 °C
1
Tj = 150 °C
VEN
0
0
Datasheet
500
1000
t [us]
1500
2000
18
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.7
Reset
The TLS850F0TAV50’s output voltage is supervised by the reset feature, including undervoltage reset, delayed
reset at power-on and an adjustable reset threshold.
The undervoltage reset function sets the pin RO/WO to LOW, in case VQ is falling for any reason below the reset
threshold VRT,low.
When the regulator is powered on, the pin RO/WO is held at LOW for the duration of the power-on reset delay
time trd.
I
Q
CQ
RRO /WO,int
Control
RO/WO
S
Reference
OR
R
VDD
optional
Supply
Reset
IRO/WO
Q
RADJ ,1
OR
MicroController
RADJ
IRADJ
opti onal
Timer
GND
RADJ ,2
Figure 5
GND
Block diagram reset circuit
Reset delay time
The reset delay time trd is fix defined according to Table 7.
Table 7
Reset delay time
Reset delay timing
trd
fix
16.5 ms
Power-on reset delay time
The power-on reset delay time is defined by the parameter trd and allows a microcontroller and oscillator to
start up. This delay time is the time period from exceeding the upper reset switching threshold VRT,high until the
reset is released by switching the reset output “RO/WO” from “LOW” to “HIGH”.
Undervoltage reset delay time
The undervoltage reset delay time is defined by the parameter trd. It is the time interval from exceeding the
reset switching threshold VRT,high until the reset is released by switching the reset output from low to high.
Reset blanking time
The reset blanking time trr,blank avoids that short undervoltage spikes trigger an unwanted reset “low” signal.
Datasheet
19
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Reset reaction time
In case the output voltage of the regulator drops below the output undervoltage lower reset threshold VRT,low,
the reset output “RO/WO” is set to low, after the delay of the internal reset reaction time trr,int. The reset
blanking time trr,blank is part of the reset reaction time trr,int.
Reset output “RO/WO”
The reset output “RO/WO” is an open collector output with an integrated pull-up resistor. In case a lowerohmic “RO/WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the
maximum “RO/WO” sink current is limited, the minimum value of the optional external resistor “RRO/WO,ext” is
given in Table “Reset output / watchdog output RO/WO” on Page 22.
Reset output “RO/WO” low for VQ ≥ 1 V
In case of an undervoltage reset condition reset output “RO/WO” is held “low” for VQ ≥ 1 V, even if the input “I”
is not supplied and the voltage VI drops below 1 V. This is achieved by supplying the reset circuit from the
output capacitor.
Reset adjust function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by
connecting an external voltage divider (RADJ1, RADJ2) at pin “RADJ”. For selecting the default threshold connect
pin “RADJ” to GND. The reset adjustment range for the TLS850F0TAV50 is given in Reset threshold
adjustment range.
When dimensioning the voltage divider, take into consideration that there will be an additional current
constantly flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows
(neglecting the Reset adjust pin current IRADJ):
VRT,lo,new = VRADJ,th × (RADJ,1 + RADJ,2) / RADJ,2
(4.1)
with
•
VRT,lo,new: Desired undervoltage reset switching threshold.
•
RADJ,1, RADJ,2: Resistors of the external voltage divider, see Figure 5.
•
VRADJ,th: Reset adjust switching threshold given in Reset adjustment switching threshold.
Datasheet
20
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
VI
t
VQ
t < trr,blank
VRH
VRT,high
VRT,lo w
1V
t
VRO/WO
trd
trr,int
trd
trr,int
trd
trr,int
trd
VRO/WO,low
1V
t
Thermal
Shutdown
Figure 6
Datasheet
Input
Voltage Dip
Undervoltage
Spike at
output
Over load
Typical timing diagram reset
21
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Table 8
Electrical characteristics reset
Tj = -40°C to 150°C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note or Test Condition Number
Min. Typ. Max.
Output undervoltage reset 5V version only
Output undervoltage reset upper
switching threshold
VRT,high
4.6
4.7
4.8
V
VQ increasing
P_5.7.1
Output undervoltage reset lower
switching threshold - default
VRT,low
4.5
4.6
4.7
V
VQ decreasing
RADJ = GND
P_5.7.2
Output undervoltage reset
switching hysteresis
VRT,hy
60
100
–
mV
RADJ connected to GND P_5.7.3
Output undervoltage reset
headroom VQ - VRT
VRH
200
400
–
mV
RADJ = GND
P_5.7.4
VRADJ,th
1.15
1.20
1.25
V
–
P_5.7.9
2.5
–
4.4
V
for VQ,nom = 5 V
P_5.7.10
0.2
0.4
V
1 V ≤ VQ ≤ VRT;
RRO/WO ≥ 5.1 kΩ
P_5.7.16
20
36
kΩ
internally connected to P_5.7.17
Q
–
–
kΩ
1 V ≤ VQ ≤ VRT;
VRO/WO ≤ 0.4 V
P_5.7.18
Reset threshold adjustment
Reset adjustment switching
threshold
Reset threshold adjustment range VRT,range
Reset output / watchdog output RO/WO
Reset output / watchdog output
low voltage
VRO/WO,low –
Reset output / watchdog output
internal pull-up resistor
RRO/WO,int
Reset output / watchdog output
external pull-up resistor to VQ
RRO/WO,ext 5.1
10
Reset delay timing
Reset delay time
trd
13.2
16.5
19.8
ms
Fixed Timing
P_5.7.39
Reset blanking time
trr,blank
–
7
–
µs
1)
P_5.7.46
Internal reset reaction time
trr,int
–
10
33
µs
for VQ,nom = 5 V
for VQ,nom = 5 V
P_5.7.36
1) Not subject to production test, specified by design.
Datasheet
22
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.8
Typical performance characteristics reset
Typical performance characteristics
Undervoltage reset threshold VRT versus
junction temperature Tj
Power-on reset delay time trd versus
junction temperature Tj
25
5
4.9
4.8
20
4.7
trd [ms]
VRT [V]
4.6
4.5
15
4.4
4.3
IQ = 1 mA
VQ = 5 V
RADJ set to GND
4.2
10
VRT, high
4.1
VRT, low
4
0
50
Tj [°C]
100
5
−40
150
0
50
Tj [°C]
100
150
Internal reset reaction time trr,int versus
junction temperature Tj
20
18
16
14
trr,int [μs]
12
10
8
6
4
2
0
−40
Datasheet
0
50
Tj [°C]
100
150
23
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
4.9
Standard watchdog
The TLS850F0TAV50 features a load dependent watchdog function. The watchdog function monitors a
microcontroller, including time base failures. In case of a missing falling edge within a certain pulse repetition
time, the watchdog output “RO/WO” is set to “low”.
The watchdog uses an internal oscillator as timebase. The effective trigger window is derived from the
watchdog timebase.
The watchdog output signal is provided by a combined reset output / watchdog output “RO/WO” pin.
I
Q
VDD
CQ
RRO /WO,int
RO/WO
Control
optional
Supply
Reset
IRO/WO
Reference
MicroController
WD core
WI
Control
IWI
GND
Figure 7
GND
Block diagram watchdog circuit
Watchdog timing
Figure 8 shows the state diagram of the watchdog (WD) and the mode selection. After power-on, the reset
output signal at the “RO/WO” pin (microcontroller reset) is kept LOW for the reset delay time trd. With the LOW
to HIGH transition of the signal at “RO/WO” the device starts the watchdog ignore time tWI.i. Next, the WD starts
the watchdog trigger time (time frame within a trigger at WI must occur).
From now on, the timing of the signal on WI from the microcontroller must fit to the WD-trigger time tWI,tr. A retrigger of the WD-trigger time is done with a HIGH-to-LOW transient at the WI-pin within the active tWI,tr.
Watchdog output “RO/WO”
The watchdog output “RO/WO” is an open collector output with an integrated pull-up resistor. In case a lowerohmic “RO/WO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the
maximum “RO/WO” sink current is limited, the minimum value of the optional external resistor “RRO/WO,ext” is
given in Table “Reset output / watchdog output RO/WO” on Page 22. A HIGH to LOW transition of the
watchdog trigger signal on pin WI is taken as a trigger. A watchdog signal is generated (“RO/WO” goes LOW), if
there is no trigger pulse during the watchdog trigger time.
Datasheet
24
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
VI
t
VQ
VRT,high
VRT,low
t
IQ
I Q,W,act
I Q,W,deact
t
Current Controlled
WD-turn off
Trigger
trd
16.5ms typ.
Ignore Time
tWI,i
(WD-trigger time tWI,tr )
96ms *)
VWI
VRO/WO
t
NO WD Trigger
WD Trigger
WD Trigger
Don’t care WI
during t WO,low and
ignore time
Don’t care WI
during t rd and ignore time
trd
96ms *)
96ms *)
96ms *)
96ms
WD Trigger
tWO,low
Normal operation
WD Trigger
Don’t care WI
during WD-off
and ignore time
No WO assertion during
Current shut down
Normal operation
t
Power
Fail
trr,int
t
*) watchdog trigger time interrupted by correct WI signal serving the watchdog
Figure 8
Typical watchdog timing diagram, watchdog and reset modes
Watchdog input “WI”
The watchdog is triggered by a falling edge at the watchdog input pin “WI”. The amplitude and slope of this
signal has to comply with the specification (Table “Watchdog input WI” on Page 26). For details regarding
test pulses, see Figure 9 “Test pulses watchdog input WI” on Page 25.
VWI
tWI,ph
VWI,high
tWI,pl
VWI,low
Figure 9
Datasheet
dVWI / dt
t
Test pulses watchdog input WI
25
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Table 9
Electrical characteristics watchdog
Tj = -40°C to 150°C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Watchdog timing
Watchdog ignore time
tWI,i
12.8
16
19.2
ms
–
P_5.9.1
Watchdog trigger time
tWI,tr
76.8
96
115.2 ms
–
P_5.9.2
Watchdog output low time
tWO,low
6.4
8
9.6
ms
–
P_5.9.6
–
–
5.5
mA
for VQ,nom = 5 V:
VI > 5.95 V;
high current condition
must be applied at least
for the time of tW,filter,max
P_5.9.42
Watchdog deactivation current IQ,W,deact
threshold
1
–
–
mA
for VQ,nom = 5 V:
VI > 5.95 V;
low current condition
must be applied at least
for the time of tW,filter,max
P_5.9.43
Watchdog deactivation current IQ,W,hy
hysteresis
0.35
–
–
mA
for VQ,nom = 5 V:
VI > 5.95 V;
P_5.9.44
Watchdog minimum filter time tW,IQ,filter,min 100
state transition by current
–
–
µs
1)
– see Page 27
P_5.9.14
Watchdog maximum filter time tW,IQ,filter,max –
state transition by current
–
500
µs
1)
– see Page 27
P_5.9.15
Load dependent watchdog activation
Watchdog activation current
threshold
IQ,W,act
Watchdog input WI
Watchdog input
low signal valid
VWI,low
–
–
0.8
V
2)
–
P_5.9.16
Watchdog input
high signal valid
VWI,high
2.0
–
–
V
2)
–
P_5.9.17
Watchdog input
high signal pulse length
tWI,ph
1
–
–
µs
2)
VWI ≥ VWI,high
P_5.9.19
Watchdog input
low signal pulse length
tWI,pl
1
–
–
µs
2)
VWI ≤ VWI,low
P_5.9.20
Watchdog input
signal slew rate
dVWI/dt
1
–
–
V/µs
2)
VWI,low < VWI < VWI,high
P_5.9.21
High level input current
IWI,H
–
–
3.5
µA
VWI = 3.3 V
P_5.9.22
Watchdog input internal
pull-down resistor
RWI
0.9
1.5
2.6
MΩ
–
P_5.9.23
Datasheet
26
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
Table 9
Electrical characteristics watchdog (cont’d)
Tj = -40°C to 150°C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified)
Typical values are given at Tj = 25 °C
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
1.15
–
1.40
V
P_5.9.48
for VQ,nom = 5 V:
VI > 5.95 V;
signal must be applied for
> tW,filter,max to deactivate
and activate the
watchdog
Watchdog minimum filter time tWI,filter,min
state transition by WI
100
–
–
µs
3)
– see Page 29
P_5.9.25
Watchdog maximum filter time tWI,filter,max
state transition by WI
–
–
500
µs
3)
– see Page 29
P_5.9.26
Watchdog disable threshold
WI signal value
VWI,dis
Reset output / watchdog output RO/WO is defined in chapter Reset output / watchdog output RO/WO
–
–
–
–
–
–
–
1) Not subject to production test, specified by design.
2) For details on applied test pulse, see Figure 9
3) Not subject to production test, specified by design.
Watchdog trigger time
The watchdog trigger time tWI,tr is fixed to a static value according to Table 10.
Table 10
Watchdog trigger time
Watchdog trigger timing
tWI,tr,typ
fix to
96 ms
Watchdog deactivation by current control
The watchdog is load dependent inactive. This ensures, that if the microcontroller is in a power save mode
(IQ ≤ IQ,W,deact) and not able to provide a correct watchdog trigger signal at pin “WI”, no watchdog signal
“RO/WO = low” is generated. The transition from an active to an inactive state will be performed after a dead
time of tW,IQ,filter,max, when output current keeps below the deactivation threshold. This protects against an
unintended entering of the watchdog deactivation state caused by short dynamic current drops. In case of
very short current drops up to the time of tW,IQ,filter,min, the activation state will definitely be kept. These
scenarios are also valid for the transition from deactivation to activation state. For details see also
Datasheet
27
Rev. 1.1
2022-02-11
OPTIREG™ linear TLS850F0TAV50
Low dropout linear voltage regulator
Block description and electrical characteristics
IQ
IQ
>tWO,low
Scenario „D“
IQ,W,act
IQ,W,act
IQ,W,deact
IQ,W,deact
tWO,low
VWI,dis.high
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