74LCXH162374MEX

74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs February 2001 Revised October 2001 74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs General Description The LCXH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LCXH162374 is designed for low voltage (2.5V or 3.3V) VCC applications. The LCXH162374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 26Ω series resistor in the output helps reduce output overshoot and undershoot. The LCXH162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant control inputs and outputs s 2.3V–3.6V VCC specifications provided s 7.0 ns tPD max (VCC = 3.3V), 20 µA ICC max s Power down high impedance inputs and outputs s ±12 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Equivalent 26Ω series resistors on output s Bushold on inputs eliminates the need for external pull-up/pull-down resistors s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LCXH162374GX (Note 1) 74LCXH162374MEA 74LCXH162374MEX (Note 2) 74LCXH162374MTD 74LCXH162374MTX (Note 2) Package Number BGA54A (Preliminary) MS48A MS48A MTD48 MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBES] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1: BGA package available in Tape and Reel only. Note 2: U se this order number to receive devices in Tape and Reel. Logic Symbol GTO is a trademark of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation DS500446 www.fairchildsemi.com 74LCXH162374 Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Descriptions Pin Names OEn CPn I0–I15 O0–O15 NC Description Output Enable Input (Active LOW) Clock Pulse Input Inputs (Bushold) Outputs No Connect FBGA Pin Assignments 1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15 Truth Tables Inputs Pin Assignment for FBGA CP1 Outputs I0–I7 H L X X O0–O7 H L O0 Z Outputs I8–I15 H L X X O8–O15 H L O0 Z OE1 L L L H Inputs CP2   L X   L X OE2 L L L H (Top Thru View) H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com 2 74LCXH162374 Functional Description The LCXH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LCXH162374 Absolute Maximum Ratings(Note 3) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature I0 - I15 OEn, LEn Value Conditions Units V V 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC V mA mA mA mA mA −0.5 to +7.0 −0.5 to VCC + 0.5 −0.5V to 7.0V −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 °C Recommended Operating Conditions (Note 5) Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current in IOH/IOL HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V TA Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 VCC VCC 5.5 Units V V V ±12 ±8 ±4 −40 0 85 10 mA °C ns/V ∆t/∆V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = −100 µA IOH = −4 mA IOH = −4mA IOH = −6 mA IOH = −8 mA IOH = −12 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 4 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II Input Leakage Current Data Control VI = VCC or GND 0V ≤ VI ≤ 5.5V Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 2.3 − 3.6 2.3 2.7 3.0 2.7 3.0 2.3 − 3.6 2.3 2.7 3.0 2.7 3.0 2.3 − 3.6 2.3 − 3.6 VCC − 0.2 1.8 2.2 2.4 2.0 2.0 0.2 0.6 0.4 0.55 0.6 0.8 ±5.0 ±5.0 µA V V TA = −40°C to +85°C Min 1.7 2.0 0.7 0.8 Max V V Units www.fairchildsemi.com 4 74LCXH162374 DC Electrical Characteristics Symbol II(HOLD) Parameter Bushold Input Minimum Drive Hold Current (Continued) VCC (V) VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 2.3 3.0 2.7 3.6 2.3 − 3.6 0 2.3 − 3.6 2.3 − 3.6 2.3 − 3.6 TA = −40°C to +85°C Min 45 −45 75 −75 300 −300 450 −450 ±5.0 10 20 ±20 500 µA µA µA µA µA µA Max Conditions Units II(OD) Bushold Input Over-Drive Current to Change State (Note 7) (Note 8) (Note 7) (Note 8) IOZ IOFF ICC ∆ICC 3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input VO = VCC or GND VI = VIH or VIL VO = VCC VI = VCC or GND 3.6V ≤ VO ≤ 5.5V (Note 6) VIH = V CC −0.6V Note 6: Outputs disabled or 3-STATE only. Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW. AC Electrical Characteristics TA = −40° to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V CL = 50 pF Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 9) Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable time 170 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 1.0 1.0 7.0 7.0 6.9 6.9 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 7.3 7.3 7.1 7.1 6.2 6.2 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 8.4 8.4 9.0 9.0 7.2 7.2 Max VCC = 2.7V CL = 50 pF Min Max VCC = 2.5V ± 0.2V CL = 30 pF Min Max MHz ns ns ns ns ns ns ns Units Note 9: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. 5 www.fairchildsemi.com 74LCXH162374 Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25°C Typical 0.35 0.25 −0.35 −0.25 Units V V Capacitance Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF www.fairchildsemi.com 6 74LCXH162374 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V trise and tfall 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74LCXH162374 Schematic Diagram Generic for LCXH Family (with Bushold) www.fairchildsemi.com 8 74LCXH162374 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74LCXH162374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A www.fairchildsemi.com 10 74LCXH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com