FAN6751MRMY

www.fairchildsemi.com AN-6073 FAN6751 — Highly Integrated Green-Mode PWM Controller Introduction This application note describes a detailed design strategy for a high-efficiency, compact flyback converter. Design considerations and mathematical equations are presented as well as guidelines for a printed circuit board layout. The highly integrated FAN6751 series of PWM controllers provides several features to enhance the performance for LCDM/TV, NB, and adapters. The green-mode function includes off-time modulation and burst mode to reduce the PWM frequency at light-load and in no-load conditions. To avoid acoustic noise problems, the minimum PWM frequency is set above 18KHz. This greenmode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. Built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary external line compensation ensures constant output power limit over a wide AC input voltage range, from 90VAC to 264VAC. FAN6751 provides many protection functions, as shown in Table 1. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. Internal Open-loop Protection GATE Output Maximum Voltage Clamp: 18V VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Internal Recovery Circuit (OVP, OLP) Internal Sense Short-Circuit Protection External Constant Power Limit (Full AC Input Range) Internal OTP Sensor with Hysteresis Built-in 5ms Soft-Start Function Built-in VIN Pin Pull HIGH (> 4.7V) Recovery Function for Second-Side Output OVP Brownout Protection with Hysteresis Applications General-purpose, switch-mode power supplies and flyback power converters, including: Power Adapters Open-frame SMPS LCD Monitor/TV SOP-8 GND FB NC HV 1 2 3 4 8 7 6 5 GATE VDD SENSE VIN Features High-Voltage Startup Low Operating Current: 4mA Linearly Decreasing PWM Frequency to 18KHz Fixed PWM Frequency: 65KHz Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Table 1. Protection Functions of FAN6751 Series Figure 1. Pin Configuration (Top View) Part Number FAN6751MRMY FAN6751HLMY OVP (VDD) Recovery Latch OLP (FB) Recovery Latch Pull-High Protection (VIN) Recovery Latch OTP (Internal) Recovery Recovery SCP (SENSE) Recovery Recovery PWM Frequency 65KHz 100KHz www.fairchildsemi.com © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 AN-6073 APPLICATION NOTE Typical Application BD1 CBulk R1 RHV RSn2 CSn2 RSn1 CSn1 D2 T1 CO Cp VO Lp D1 DSn 7 VDD 4 HV CVDD EMI Filter Fuse N L C2 AC INPUT R2 RFB 5 Rd VIN GATE 8 Rg Q1 PC817 R1 C1 R3 KA431 R2 2 FB SENSE 6 RLF CLF RS CFB NC 3 GND 1 Figure 2. Typical Application Block Diagram Figure 3. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 www.fairchildsemi.com 2 AN-6073 APPLICATION NOTE Internal Block Operation Startup and Soft-Start Circuitry When power is turned on, the internal high-voltage startup current (typically 2mA) charges the hold-up capacitor C1 through startup resistor RHV. RHV can be directly connected by VBULK to the HV pin. The built-in 5ms soft-start circuit starts when the VDD pin reaches the start threshold voltage VDD-ON. Soft-start helps reduce the inrush current, the startup current spike, and output voltage overshoot during the startup period, as shown in Figure 4. When VDD reaches VDD-ON, the internal high-voltage startup current is switched off and the supply current is drawn from the auxiliary winding of the main transformer, as shown in Figure 5. VDD Soft Driver S R 6 Soft Start Sense Q Figure 6. UVLO Specification Under-Voltage Lockout (UVLO) The FAN6751 has a voltage detector on the VDD pin to ensure that the chip has enough power to drive the MOSFET. Figure 7 shows a hysteresis of the turn-on and turn-off threshold levels and an open-loop-release voltage. 8 GATE Figure 4. Soft-start Circuit Figure 5. Startup Circuit for Power Transfer Figure 7. UVLO Specification If a shorter startup time is required, a two-step startup circuit, as shown Figure 6, is recommended. In this circuit, a smaller capacitor C1 can be used to reduce startup time. The energy supporting the FAN6751 after startup is mainly from a larger capacitor C2. If a shorter releasing latch mode time is required, a DHV and RHV can be directly connected by VAC to the HV pin. When the supply current is drawn from the transformer, it draws a leakage current of about 1µA from HV pin. The maximum power dissipation of the RHV is: PRHV = IHV − LC (Typ.)2 × RHV = IμA2 × 100KΩ ≅ 0.1μW The turn-on and turn-off thresholds are internally fixed at 16.5V and 10.5V. During startup, the VDD’s capacitor must be charged to 16.5V to enable the IC. The capacitor continues to supply the VDD until the energy can be delivered from the auxiliary winding of the main transformer. The VDD must not drop below 10.5V during the startup sequence. To further limit the input power under a short-circuit or open-loop condition, a special two-step UVLO mechanism prolongs the discharge time of the VDD capacitor. Figure 8 shows the traditional UVLO method along with the special two-step UVLO method. In the two-step UVLO mechanism, an internal sinking current, IDD-OLP, pulls the VDD voltage toward the VDD-OLP. This sinking current is disabled after the VDD drops below VDD-OLP; after which, the VDD voltage is again charged towards VDD-ON. With the addition of the twostep UVLO mechanism, the average input power during a short-circuit or open-loop condition is greatly reduced. As a result, over-heating does not occur. www.fairchildsemi.com 3 (1) where IHV-LC is the supply current drawn from HV pin, and RHV is 100KΩ. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 AN-6073 APPLICATION NOTE down at no load. The value of the biasing resistor Rb is determined as: Vo − VD − VZ • K ≥ 1.5mA Rb where: VD is the drop voltage of photodiode, approximately 1.2V; VZ is the minimum operating voltage, 2.5V of the shunt regulator; and K is the current transfer rate (CTR) of the opto-coupler. For an output voltage VO=5V with CTR=100%, the maximum value of Rb is 860Ω. (3) Green Mode Operation Green mode includes off-time modulation and burst mode to reduce the PWM frequency at light-load and in no-load conditions. The feedback voltage of the FB pin is taken as a reference. When the feedback voltage is lower than VFB-N, the PWM frequency decreases. Because most losses in a switching-mode power supply are proportional to the PWM frequency, the off-time modulation reduces the power consumption of the power supply at light-load and no-load conditions. Figure 10 is the PWM frequency is 65KHz at nominal load and decreases to 18KHz at light load. Frequency Figure 8. UVLO Effect FB Input The FAN6751 is designed for peak-current-mode control. A current-to-voltage conversion is done externally with a current-sense resistor RS. Under normal operation, the FB level controls the peak inductor current: VFB − 0.6 (2) 4 where VFB is the voltage on FB pin and 4 is an internal divider ratio. VSENSE = I pk × RS = Fosc:65KHz PWM Frequency When VFB is less than 0.6V, the FAN6751 terminates the output pulses. Fosc:18KHz VFB-ZDC VFB-G VFB-N Figure 10. PWM Frequency vs. FB Voltage Figure 9. Feedback Circuit Figure 9 is a typical feedback circuit consisting mainly of a shunt regulator and an opto-coupler. R1 and R2 form a voltage divider for the output voltage regulation. R3 and C1 are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 100Ω, CFB= 1nF) placed on the FB pin to the GND can further increase the stability. The maximum sourcing current of the FB pin is 1.5mA. The phototransistor must be capable of sinking this current to pull FB level © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 The power supply enters “burst mode” in no-load conditions. As shown in Figure 11 and Figure 12, when VFB drops below VFB-ZDC, the PWM output is shuts off and the output voltage drops at a rate dependent on load current. This causes the feedback voltage to rise. Once VFB exceeds VFB-ZDC, the internal circuit starts to provide switching pulse. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the MOSFET, reducing the switching losses in standby mode. www.fairchildsemi.com 4 AN-6073 APPLICATION NOTE larger ripple current ratings are required. DCM operation also results in a higher output voltage spike. A large LC filter is added. Therefore, a flyback converter in CCM achieves better performance with lower component cost. Despite the above advantages of CCM operation, there is one concern—stability. In CCM operation, the output power is proportional to the average inductor current, while the peak current remains controlled. This causes sub-harmonic oscillation when the PWM duty cycle exceeds 50%. Adding slope compensation (reducing the current-loop gain) is an effective way to prevent oscillation. The FAN6751 introduces a synchronized positive-going ramp (VSLOPE) in every switching cycle to stabilize the current loop. Therefore, the FAN6751 can be used to design a costeffective, highly efficient, compact flyback power supply operating in CCM without additional external components. The positive ramp added is: VSLOPE = VSL • D Figure 11. FAN6751HL Burst-mode Operation (4) where VSL = 0.33V and D = duty cycle. VO VFB 1.1 Ids Vds Figure 13. Synchronized Slope Compensation Over-Power Compensation time Switching Switching Switching Switching Disabled Disabled Disabled Disabled Figure 12. FAN6751MR Burst-Mode Operation Built-in Slope Compensation A flyback converter can be operated in either discontinuous current mode (DCM) or continuous current mode (CCM). There are many advantages when operating the converter in CCM. With the same output power, a converter in CCM exhibits a smaller peak inductor current than in DCM. Therefore, a small-sized transformer and a low-rated MOSFET can be applied. On the secondary side of the transformer, the RMS output current of DCM can be twice that of CCM. Larger wire gauge and output capacitors with © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 5 The maximum output power of a flyback converter can generally be designed by the current-sense resistor RS. When the load increases, the peak inductor current increases accordingly. As the current-sense signal of the SENSE pin exceeds the internal limit VSENSE, 0.83V typically, as VIN=1V, FAN6751 stops the PWM pulse immediately. The output power of a flyback power supply in DCM is calculated as follows: POUT = 1 • LP • IPK 2 • fS • η 2 (5) where: Lp is the transformer primary-side inductance; IPK is the peak inductor current; fS is the PWM frequency; and η is the conversion efficiency. www.fairchildsemi.com AN-6073 APPLICATION NOTE If the conversion efficiency remains unchanged for a wide input voltage range, the maximum output power would be the same for a fixed IPK, which is limited by the internal current limiting threshold voltage VTH and RS. However, due to the time delay from the comparator to output stage inside the FAN6751, the maximum output power with high-line input is always higher than with low line. A 30% error is common for the universal input voltage range if the converter is operated in DCM. In CCM operation, the deviation becomes even larger. For the purpose of constant output power limit, the peak current limit VTH must be adjustable according to the VIN pin, which is proportional to input voltage. VIN=1V and VSENSE=0.83V at low line; VIN=3V and VSENSE=0.7 at high line. or Latched (for HL). OVP condition is usually caused by feedback open loops. Overload Protection (OLP) If the secondary output short circuits or the feedback loop is open, the FB pin voltage rises rapidly toward the open-loop voltage, VFB-OPEN. If the FB voltage remains above VFB-OLP and lasts for tD-OLP, the FAN6751 stops emitting output pulses and enters Recovery Mode (for FAN6751MR) or latched-up mode (for FAN6751HL), as shown in Figure 17. Vds Power On OVP occurs Removed AC line Power On VDD 26V 16.5V Figure 14. Universal Line Voltage Compensation for Constant Output Power Limit 10.5V 7.5V 5V Protection Functions FAN6751 has protection functions in two categories: some enter Latch Mode and the others enter Recovery Mode. The Latch Mode can only be restart if VDD falls below 5V, as shown Figure 15. The Recovery Mode lets VDD decrease to UVLO mechanism until the fault condition removed, as shown Figure 16. Both modes prevent the SMPS from destructive states. Table 2 shows the relationship between protection functions and part numbers. Table 2. Protection Functions Normal Latch mode operation Without any switching Remove Latch mode Normal operation Figure 15. VDD OVP Protection Waveforms for FAN6751HL, Latch Off Protection Functions VDD Over-Voltage Protection (OVP) Overload Protection (OLP) Pull-High Protection Function by VIN > 4.7V Internal Over Temperature Protection(OTP) SENSE Pin Short-Circuit Protection Brownout Protection FAN6751MR FAN6751HL Recovery Recovery Recovery Recovery Recovery Recovery Latch Latch Latch Recovery Recovery Recovery VDD Over-Voltage Protection (OVP) VDD OVP has protection prevents damage due to overvoltage conditions. When the VDD voltage exceed 26V due to abnormal conditions, PWM output is turned off until the VDD voltage drops below UVLO then starts again (for MR) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 Figure 16. VDD OVP Protection Waveforms for FAN6751MR, Recovery www.fairchildsemi.com 6 AN-6073 APPLICATION NOTE SENSE Pin Short-Circuit Protection The FAN6751 provides a safety protection for power supply production. When the sense resistor is shorted by soldering during production, the pulse-by-pulse current limiting loses efficiency for the purpose of providing over-power protection of the unit. The unit may be damaged when the loading is larger than the original maximum load. To protect against a short circuit across the current-sense resistor, the controller immediately shuts down if a continuously low voltage (~0.15V/150µs) on the SENSE pin is detected. Brownout Protection Since the VIN pin is connected through a resistive divider to the rectified AC input line voltage, it can also be used for brownout protection. If the VIN voltage is less than 0.7V, the PWM output is shut off. As the VIN voltage reaches 0.92V, the PWM output is turned on again. The hysteresis window for ON/OFF is around 0.22V. The recommended values for RBo1, RBo2, and CBo1 are 10M (5M+5M), 100K, and 2.2µF. Using these values in the test board, the power supply is turned off at 66V (maximum load) and recovered at 70V. Figure 17. Overload Protection Waveforms Pull-HIGH Protection Function in VIN Pin The pull-high protection function is also included in the VIN pin. When VIN is higher than 4.7V, FAN6751 latches up and stops regulating. Figure 18 shows the external latch circuit for secondary-side output OVP. If the output voltage (VO) is higher than VZ (Zener diode voltage), VDD passes through the RRESTRICT to VIN pin (there are three Zener diodes to clamp this over-voltage at 6V) to achieve the latch mode. Figure 19. Circuit for Brownout Leading-Edge Blanking (LEB) A voltage signal proportional to the MOSFET current develops on the current-sense resistor RS. Each time the MOSFET is turned on, a spike induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, appears on the sensed signal. Inside the FAN6751, a leading-edge blanking time of about 350ns helps avoid premature termination of MOSFET by the spike. Therefore, only a small-value RC filter (e.g. 100Ω + 470pF) is required between the SENSE pin and RS. Still, a noninductive resistor for the RS is recommended. Figure 18. External Circuit for Second OVP Internal Over-Temperature Protection (OTP) The FAN6751 has a built-in temperature sensing circuit to shut down PWM output once the junction temperature exceeds 135°C. While PWM output is shut down, the VDD voltage gradually drops to the UVLO voltage (around 7.5V). Then VDD is charged up to the startup threshold voltage of 16.5V through the startup resistor until PWM output is restarted. This “hiccup” mode protection continues as long as the temperature remains above 130°C. The temperature hysteresis window for the OTP circuit is 25°C. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 www.fairchildsemi.com 7 AN-6073 APPLICATION NOTE Output Driver / Soft Driving The FAN6751’s output stage is a fast totem-pole gate driver capable of directly driving an external MOSFET. An internal Zener diode clamps the driver voltage under 18V to protect the MOSFET against over-voltage. By integrating special circuits to control the slew rate of switch-on rising time, the external resistor Rg may not be necessary to reduce switching noise, improving EMI performance. Figure 20. Turn-On Spike Figure 21. Gate Driver © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 www.fairchildsemi.com 8 AN-6073 APPLICATION NOTE Printed Circuit Board Layout Current/voltage/switching frequency makes printed circuit board layout and design a very important issue. Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge/ESD tests. The following are some general guidelines: To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor Cbulk first, then to the switching circuits. The high-frequency current loop is found in Cbulk – Transformer – MOSFET – RS – Cbulk. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4→1) short, direct, and wide. High-voltage drain traces related to the MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, it is recommended to ground the heatsink. As indicated by 3, the control circuit’s ground should be connected first, then to other circuitry. As indicated by 2, the area enclosed by the transformer auxiliary winding, D1, and C1, should be kept small. Place C1 close to the FAN6751 for good decoupling. Two suggestions with different pros and cons for ground connections are recommended. GND3→2→4→1: Possible method for circumventing the sense signals common impedance interference. GND3→2→1→4: Potentially better for ESD testing where a ground is not available for the power supply. The charges for ESD discharge path go from the secondary through the transformer stray capacitance to the GND2 first. Then, the charges go from GND2 to GND1 and back to the mains. Control circuits should not be placed on the discharge path. Point discharge for common choke can decrease high-frequency impedance and help increase ESD immunity. Should a Y-cap between primary and secondary be required, the Y-cap should be connected to the positive terminal of the Cbulk (VDC). If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of the Cbulk (GND1) directly. Point discharge of the Y-cap also helps with ESD. However, according to safety requirements, the creepage between the two pointed ends should be at least 5mm. BD1 CBulk Common mode choke VIN C2 R2 FB RFB CFB GND GATE R1 RHV D1 CVDD HV VDD Rg SENSE RLF CLF RS CFB Figure 22. Layout Considerations © 2008 Fairchild Semiconductor Corporation Rev. 1.0.0 • 9/26/08 www.fairchildsemi.com 9 AN-6073 APPLICATION NOTE Typical Application Circuit Application LCD Monitor Power Supply Output Power 44W Input Voltage Range Universal Input (90-264VAC) Output Voltage/Maximum Current 12V/2A 5V/4A Features High-Voltage Startup Built-in 5ms Soft-Start Function Built-in VIN Pin Pull-High (> 4.7V) Recovery Function for Second-Side Output OVP Brownout Protection with Hysteresis Low Standby Mode Power Consumption (Input Wattage