MB39A106PFT-E1

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27235-2E ASSP For Power Supply Applications (General Purpose DC/DC Converter) 2-Channel DC/DC Converter IC with Overcurrent Protection Symmetrical-Phase Type MB39A106 ■ DESCRIPTION The MB39A106 is a symmetrical-phase type of two-channel, DC/DC converter IC using pulse width modulation (PWM) , incorporating an overcurrent protection circuit (requiring no current sense resistor) and an overvoltage protection circuit. Providing high output driving capabilities, the MB39A106 is suitable for down-conversion. The MB39A106 adopts both synchronous rectification to provide high efficiency and symmetrical phasing (two anti-phase triangular waves) which contributes to making the input capacitor small. The MB39A106 contains a Bootstrap diode resulting in a reduced number of components used. It also contains a variety of protection features which output the protection status upon detection of an overvoltage or overcurrent while reducing the number of external protective devices required. The result is an ideal built-in power supply for driving products with high speed CPU’s such as home TV game devices and notebook PC’s. ■ FEATURES • • • • • • • • • • • • • • • • • Built-in bootstrap diode Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor) Built-in timer-latch overvoltage protection circuit Synchronous rectification system providing high efficiency Power supply voltage range: 6.5 V to 18 V PWRGOOD terminals (open-drain) to output the protection status Symmetrical-phase system reducing the input capacitor loss Built-in channel control function One type of package (TSSOP-30pin : 1 type) Reference voltage: 3.5 V ± 1 % Error amplifier threshold voltage: 1.23 V ± 1 % (Ta = 0 °C to + 85 °C) Support for frequency setting using an external resistor (Frequency setting capacitor integrated) Oscillation frequency range: 100 kHz to 500 kHz Standby current : 0 µA (Typ) Built-in circuit for load-independent soft-start and discharge control Built-in totem-pole output for N-ch MOS FET One type of package (TSSOP-30 pin : 1 type) ■ APPLICATION • Home Video Game • IP phone • Printer etc. Copyright©2002-2006 FUJITSU LIMITED All rights reserved MB39A106 ■ PIN ASSIGNMENT (TOP VIEW) −INE1 : 1 FB1 : 2 CS1 : 3 NC : 4 RT : 5 CTL : 6 SGND : 7 VREF : 8 CTL1 : 9 CTL2 : 10 CSCP : 11 PWRGOOD : 12 CS2 : 13 FB2 : 14 −INE2 : 15 30 : CB1 29 : OUT1-1 28 : VS1 27 : OUT2-1 26 : PGND1 25 : ILIM1 24 : VCC 23 : ILIM2 22 : VB 21 : NC 20 : PGND2 19 : OUT2-2 18 : VS2 17 : OUT1-2 16 : CB2 (FPT-30P-M04) 2 MB39A106 ■ PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 Symbol −INE1 FB1 CS1 NC RT CTL SGND VREF CTL1 I/O I O ⎯ ⎯ ⎯ I ⎯ O I CH1 error amp output terminal CH1 soft-start capacitor connection terminal No connection Triangular waveform oscillation frequency setting resistor connection terminal Power supply control terminal “H” level : IC operating mode “L” level : IC Standby mode Ground terminal Reference voltage output terminal CH1 control terminal “H” level : CH1 ON state “L” level : CH1 OFF state and protection status reset CH2 control terminal “H” level : CH2 ON state “L” level : CH2 OFF state and protection status reset Timer-latch short-circuit protection capacitor connection terminal CH1, CH2 protection status output terminal CH2 soft-start capacitor connection terminal CH2 error amp output terminal CH2 error amp inverted input terminal CH2 boot capacitor connection terminal Connect a capacitor between the CB2 and VS2 terminals. CH2 totem-pole output terminal (External main-side FET gate drive) CH2 external main-side FET source connection terminal CH2 totem-pole output terminal (External synchronous-rectification-side FET gate drive) Ground terminal No connection Output circuit bias output terminal CH2 overcurrent detection resistor connection terminal Reference voltage, control circuit power supply terminal CH1 overcurrent detection resistor connection terminal Ground terminal CH1 totem-pole output terminal (External synchronous-rectification-side FET gate drive) CH1 external main-side FET source connection terminal CH1 totem-pole output terminal (External main-side FET gate drive) CH1 boot capacitor connection terminal Connect a capacitor between the CB1 and VS1 terminals. 3 Descriptions CH1 error amp inverted input terminal 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CTL2 CSCP PWRGOOD CS2 FB2 −INE2 CB2 OUT1-2 VS2 OUT2-2 PGND2 NC VB ILIM2 VCC ILIM1 PGND1 OUT2-1 VS1 OUT1-1 CB1 I ⎯ O ⎯ O I ⎯ O ⎯ O ⎯ ⎯ O I ⎯ I ⎯ O ⎯ O ⎯ MB39A106 ■ BLOCK DIAGRAM VCC 24 6V VB Reg. FB1 2 L priority L priority 22 VB CH1 Dead Time Modulation 1 PWM + Comp.1 + − Max Duty 81% Dtr ± 6% 30 CB1 Drv 1-1 29 OUT1-1 28 VS1 Drv 2-1 27 OUT2-1 26 PGND1 Current Protection Logic H: at OCP − + 118 µA 25 ILIM1 −INE1 1 CS1 3 VREF 3 µA 100 kΩ Buff CTL1 9 Open : CH1 ON CTL1 = H L : CH1 OFF 6 kΩ VTH = 1.4 V − + + 1.23 V OVP + Comp.1 − 1.38 V Error Amp1 FB2 14 L priority L priority −INE2 15 CS2 13 VREF 3 µA 100 kΩ Buff CTL2 10 Open : CH2 ON CTL2 = H L : CH2 OFF 6 kΩ VTH = 1.4 V Error Amp2 − + + 1.23 V OVP + Comp.2 − 1.38 V Dead Time Modulation 2 PWM Comp.2 + + − Max Duty 81% Dtr ± 6% CH2 16 CB2 Drv 1-2 17 OUT1-2 18 VS2 Drv 2-2 OCP Comp.2 − + 118 µA 19 OUT2-2 20 PGND2 Current Protection Logic H: at OCP 23 ILIM2 H: priority SCP Comp. + + − H: at OVP H: at UVLO release 3.1 V H: at OVP H: at OVP H: at OCP H: at SCP Latch1 SQ L: at protection operation CTL CTL1 CTL2 10 µA CTL CTL1 CTL2 SR Latch Latch2 R PWRGOOD 12 Protection control signal CSCP 11 VREF UVLO OSC 45 pF 3.0 V CT1 1.8 V 3.0 V CT2 1.8 V 4 NC to Error amp reference 1.23 V bias VREF 3.5 V VCC 21 NC 6 CTL Power VR1 ON/OFF CTL 7 SGND 5 RT 8 VREF H : ON (Power On) L : OFF (Standby mode) VTH = 1.4 V 4 MB39A106 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power-supply voltage Boot voltage Output current Peak output current Power dissipation Storage temperature Symbol VCC VCB IO IOP PD TSTG Condition ⎯ CB terminal ⎯ Duty ≤ 5% (t = 1 / fOSC × Duty) Ta ≤ +25 °C ⎯ Rating Min ⎯ ⎯ ⎯ ⎯ ⎯ −55 Max 20 25 120 800 1390* +125 Unit V V mA mA mW °C * : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 5 MB39A106 ■ RECOMMENDED OPERATING CONDITIONS Parameter Power-supply voltage Boot voltage Reference voltage output current Bias output current Input voltage Output voltage Output current Peak output current Oscillation frequency Timing resistor Boot capacitor Reference voltage output capacitor Bias output capacitor Soft-start capacitor Short-circuit detection capacitor Overcurrent detection setting resistor Operating ambient temperature Symbol VCC VCB IOR IOB VIN VCTL VPG IO IOP fOSC RT CB CREF CVB CS CSCP RLIM Ta Condition ⎯ CB terminal VREF terminal VB terminal −INE terminal CTL1, CTL2 terminal CTL terminal PWRGOOD terminal ⎯ Duty ≤ 5% (t = 1 / fOSC × Duty) ⎯ ⎯ ⎯ VREF terminal VB terminal ⎯ ⎯ ⎯ ⎯ Value Min 6.5 ⎯ −1 −1 0 0 0 0 − 100 − 700 100 30 ⎯ ⎯ 1.0 ⎯ ⎯ 0.1 − 30 Typ 12 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 300 47 0.1 0.1 4.7 0.1 0.01 1 + 25 Max 18 24 0 0 VCC − 1.8 VREF VCC 15 +100 +700 500 130 1.0 1.0 10 1 1 10 + 85 Unit V V mA mA V V V V mA mA kHz kΩ µF µF µF µF µF kΩ °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB39A106 ■ ELECTRICAL CHARACTERISTICS (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C) Parameter Symbol Pin No. 8 8 8 8 8 22 Conditions Ta = + 25 °C Ta = 0 °C to + 85 °C VCC = 6.5 V to 18 V VREF = 0 mA to − 1 mA VREF = 0 V ⎯ Value Min 3.465 ⎯ ⎯ ⎯ − 40 5.88 270 ⎯ 2.6 Typ 3.500 0.5* 1 3 − 20 6.00 300 1* 2.8 0.2* 2.1 0.70 − 10 118 1* 1.38 −110 ⎯ Max 3.535 ⎯ 10 10 − 10 6.12 330 ⎯ 3.0 ⎯ 2.5 0.75 −6 130 ⎯ 1.41 ⎯ 40 Unit VREF Reference Voltage Block [REF] Output voltage ∆VREF/ VREF Input stability Load stability Short-circuit output current Bias Voltage Block [VB] Triangular Waveform Oscillator Block [OSC] Output voltage Oscillation frequency Frequency/ temperature variation Line Load IOS VB fOSC V % mV mV mA V kHz % V V V V µA µA mV V nA µA 17, 29 RT = 47 kΩ ∆fOSC/ 17, 29 Ta = 0 °C to + 85 °C fOSC VTH VH VRST VTH ICSCP ILIM VIO VTH IB 8 8 8 11 11 23, 25 RT = 47 kΩ 23, 25 1, 15 −INE = 1, 15 −INE = 0 V 12 PWRGOOD = 5 V ⎯ VREF = ⎯ ⎯ VREF = ⎯ Threshold Undervoltage voltage (VCC) Hysteresis Lockout Circuit width Block [UVLO] Reset voltage Short-circuit Protection Circuit Block [SCP] Overcurrent Protection Circuit Block [OCP] ⎯ 1.7 0.65 − 14 106 ⎯ 1.35 −730 ⎯ Threshold voltage Input source current ILIM terminal input current Offset voltage Threshold voltage Input bias current Output leakage current Output “L” level voltage Charge current Overvoltage Protection Circuit Block [OVP] Protection Status Output Circuit Block [PWRGOOD] ILEAK VOL 12 PWRGOOD = 1 mA ⎯ ⎯ − 4.2 0.1 − 3.0 0.4 − 1.8 V µA Soft-start Circuit Block [CS] ICS 3, 13 (Continued) 7 MB39A106 (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C) Parameter Symbol Pin No. 1, 15 1, 15 Conditions FB = 2.4 V, Ta = + 25 °C FB = 2.4 V, Ta = 0 °C to + 85 °C Value Min 1.221 1.218 − 730 60 ⎯ Typ 1.230 1.230 − 110 100 1.5* 3.4 40 −2 250 1.8 2.86 Max 1.239 1.242 ⎯ ⎯ ⎯ ⎯ 200 −1 ⎯ ⎯ 3.00 Unit Threshold voltage Input bias current Error Amp Block [Error Amp] Voltage gain Frequency bandwidth Output voltage Output source current Output sink current PWM Comparator Block [PWM Comp.] Dead Time Control Block [DTC] VTH1 VTH2 IB AV BW VFBH VFBL V V nA dB MHz 1, 15 −INE = 0 V 2, 14 DC 2, 14 AV = 0 dB 2, 14 2, 14 ⎯ ⎯ 3.2 ⎯ ⎯ 150 1.7 ⎯ V mV mA µA V V % ISOURCE 2, 14 FB = 2.4 V ISINK VTL 2, 14 FB = 2.4 V 2, 14 Duty cycle = 0 % 2, 14 Duty cycle = Dtr 17, 29 RT = 47 kΩ OUT1 = 12 V, CB = 17 V, VS = 12 V, 17, 29 Duty ≤ 5 % (t = 1/ fOSC × Duty) OUT1 = 17 V, CB = 17 V, VS = 12 V, 17, 29 Duty ≤ 5 % (t = 1/ fOSC × Duty) 17, 29 17, 29 OUT1 = − 100 mA, CB = 17 V, VS = 12 V OUT1 = 100 mA, CB = 17 V, VS = 12 V OUT2 = 0 V, (t = 1/ fOSC × Duty) Threshold voltage VTH Maximum duty cycle Dtr 75 81 87 ISOURCE1 ⎯ − 700* ⎯ mA Output current (main side) ISINK1 ⎯ VCB − 2.5 ⎯ ⎯ 900* VCB − 0.9 VS + 0.9 − 750* ⎯ mA Output Block [Drive] Output voltage (main side) VOH1 VOL1 ⎯ VS + 1.4 ⎯ V V mA Output current (synchronous rectification side) ISOURCE2 19, 27 Duty ≤ 5 % ISINK2 OUT2 = 6 V, 19, 27 Duty ≤ 5 % (t = 1/ fOSC × Duty) ⎯ 900* ⎯ mA (Continued) 8 MB39A106 (Continued) Parameter Output voltage (synchronous rectification side) Output Block [Drive] Diode voltage Symbol Pin No. (VCC = 12 V, VB = 0 mA, VREF = 0 mA, Ta = + 25 °C) Value Unit Conditions Min Typ Max 3.5 ⎯ ⎯ 40 − OUT1 : 60 − OUT2 : ⎯ ⎯ ⎯ ⎯ CTL = 5 V CTL = 0 V CTL = 5 V 2 0 2 0 − 44 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ − 35 50 0 15 VREF 0.8 VCC 0.8 − 29 75 10 23 V V V V µA µA µA mA 120 180 ns 5.1 1.0 0.8 80 ⎯ 1.4 1.0 120 V V V ns VOH2 VOL2 VD tD1 19, 27 OUT2 = − 100 mA 19, 27 OUT2 = 100 mA 16, 30 VB = 10 mA 29, 27, VS = 0 V 17, 19 OUT1 = OUT2 = OPEN, Dead time tD2 Output ON condition Output OFF condition Control Block [CTL, CTL1, CTL2] Output ON condition Output OFF condition Input current Standby current Power-supply current VON VOFF VON VOFF ICTL ICCS ICC OUT2 : 29, 27, VS = 0 V 17, 19 OUT1 = OUT2 = OPEN, OUT1 : 9, 10 9, 10 6 6 9, 10 CTL1 = CTL2 = 0 V 6 24 24 General *: Standard design value 9 MB39A106 ■ TYPICAL CHARACTERISTICS Power Supply Current vs. Power Supply Voltage 20 Reference Voltage vs. Power Supply Voltage 6 Ta = +25 °C CTL = 5 V VREF = 0 mA Power Supply current ICC (mA) Reference voltage VREF (V) 20 18 16 14 12 10 8 6 4 2 0 0 5 10 Ta = +25 °C CTL = 5 V 5 4 3 2 1 0 0 5 10 15 15 20 Power supply voltage VCC (V) Reference Voltage vs. Load Current 5 Ta = +25 °C VCC = 12 V CTL = 5 V Power supply voltage VCC (V) Reference Voltage vs. Ambient Temperature 2.0 VCC = 12 V CTL = 5 V VREF = 0 mA Reference voltage ∆VREF (%) Reference voltage VREF (V) 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 0 +20 +40 4 3 2 1 0 0 5 10 15 20 25 +60 +80 +100 Load current IREF (mA) CTL Terminal Current, Reference Voltage vs. CTL Terminal Voltage 500 Ambient temperature Ta (°C) Triangular Wave Oscillation Frequency vs. Timing Resistor 1000 CTL terminal current ICTL (µA) 400 VREF 300 3 Reference voltage VREF (V) Triangular wave oscillation frequency fOSC (kHz) 5 Ta = +25 °C VCC = 12 V VREF = 0 mA 4 Ta = +25 °C VCC = 12 V CTL = 5 V 100 200 ICTL 100 2 1 0 0 5 10 15 0 20 10 10 100 1000 CTL terminal voltage VCTL (V) Timing resistor RT (Ω) (Continued) 10 MB39A106 Triangular Wave Oscillation Frequency vs. Power Supply Voltage 330 325 320 315 310 305 300 295 290 285 280 275 270 0 5 10 Triangular Wave Oscillation Frequency vs. Ambient Temperature 2 Triangular wave oscillation frequency fosc (kHz) Triangular wave oscillation frequency ∆fOSC/fOSC (%) Ta = +25 °C RT = 47 kΩ CTL = 5 V 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −40 −20 0 +20 +40 +60 VCC = 12 V RT = 47 kΩ CTL = 5 V 15 20 +80 +100 Power supply voltage VCC (V) Error Amplifier Threshold Voltage vs. Ambient Temperature 1.244 1.242 1.240 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 1.222 1.220 1.218 −40 VCC = 12 V CTL = 5 V Ambient temperature Ta ( °C) Error amplifier threshold voltage VTH (V) −20 0 +20 +40 +60 +80 +100 Ambient temperature Ta ( °C) Error Amplifier, Gain, Phase vs. Frequency 40 30 20 AV ϕ 90 Ta = +25 °C 180 4.2 V VCC = 12 V 240 kΩ 10 kΩ 2.4 kΩ (15) 1− 3+ (13) + 10 0 −10 −20 −30 −40 100 1k 10 k 100 k 1M −90 0 Phase φ (deg) Gain AV (dB) 10 kΩ 1 µF + IN 2 (14) OUT 10 kΩ −180 10 M 10 kΩ 1.23 V Error Amp1 (Error Amp2) Frequency f (Hz) (Continued) 11 MB39A106 (Continued) Power Dissipation vs. Ambient Temperature 1600 Power dissipation PD (mW) 1400 1390 1200 1000 800 600 400 200 0 −40 −20 0 +20 +40 +60 +80 +100 Ambient temperature Ta ( °C) 12 MB39A106 ■ FUNCTIONS 1. DC/DC Converter Functions (1) Reference voltage block (Ref) The reference voltage circuit generates a temperature-compensated reference voltage (typically 3.5 V) using the voltage supplied from the power supply terminal (pin 24) . The voltage is used as the reference voltage for the IC’s internal circuit. The reference voltage can be used to supply a load current of up to 1 mA to an external device through the VREF terminal (pin 8) . (2) Triangular-wave oscillator block (OSC) The triangular waveform oscillator incorporates a triangular oscillation frequency setting capacitor connected respectively to the RT terminal (pin 5) to generate triangular oscillation waveforms CT1 (amplitude of 1.8 V to 3.0 V) and CT2 (amplitude of 1.8 V to 3.0 V in antiphase with CT1). The symmetrical-phase system using the two opposite-phase triangular waves reduces the input ripple current, resulting in a smaller input capacitor. The triangular oscillation waveforms are input to the IC’s internal PWM comparator. (3) Error amplifier block (Error Amp1, Error Amp2) The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. By connecting a feedback resistor and capacitor between the output terminal and inverted input terminal, it is possible to create any desired level of loop gain, thereby providing stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor to the CS1 terminal (pin 3) or CS2 terminal (pin 13), the non-inverted input terminal for Error Amp. The use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load on the DC/ DC converter. (4) PWM comparator block (PWM Comp.) The PWM comparator is a voltage-pulse width modulator that controls the output duty depending on the input/output voltage. Main side : Turns the output transistor on in the intervals in which the error amplifier output voltage is higher than the triangular wave voltage. Synchronous rectification side : Turns the output transistor on in the intervals in which the error amplifier output voltage is lower than the triangular wave voltage. (5) Output block The output circuits on the main side and on the synchronous rectification side are both in the totem pole configuration, capable of driving an external N-ch MOS FET. In addition, because the output drive ability (700 mA Max : Duty ≤ 5%) is high, the gate − source capacity is large and the FET of low ON resistor can be used. 13 MB39A106 2. Channel Control Function Channels, main, VB and PWRGOOD are turned on and off depending on the voltage levels at the CTL terminal (pin 6), CTL1 terminal (pin 9) and CTL2 terminal (pin 10). Channel On/Off Setting Conditions CTL CTL1 CTL2 Power CH1 CH2 VB PWRGOOD L H H H H *: Undefined ⎯* L H L H ⎯* L L H H OFF ON ON ON ON OFF OFF ON OFF ON OFF OFF OFF ON ON OFF ON ON ON ON OFF ON ON ON ON 3. Protective Functions (1) Undervoltage lockout protection circuit (UVLO) The transient state or a momentary drops in supply voltage, which occurs when the power supply is turned on, may cause the control IC to malfunction, resulting in breakdown or degradation of the system. To prevent such malfunctions, the undervoltage lockout protection circuit detects the internal reference voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the CSCP terminal (pin 11) at the “L” level and setting the PWRGOOD terminal (pin 12) to the “L” level. The system is restored when the supply voltage reaches the threshold voltage of the undervoltage lockout protection circuit. (2) Timer-latch overcurrent protection circuit block (OCP) The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source using the main-side FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the latch to turn off the FETs on the main side and synchronous rectification side of each channel while setting the PWRGOOD terminal (pin 12) to the “L” level. The detection current value can be set by resistor RLIM1 connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and resistor RLIM2 connected between the drain and the ILIM2 terminal (pin 23). To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “1. Setting TimerLatch Overcurrent Detection Current” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.) (3) Timer-latch short-circuit protection circuit (SCP) The short-circuit detection comparator (SCP Comp.) detects the output voltage level and, if the error amplifier output voltage of either channel reaches the short-circuit detection voltage (typically 3.1 V), the timer circuit is actuated to start charging the external capacitor Cscp connected to the CSCP terminal (pin 11). When the capacitor voltage reaches about 0.7 V, the circuit turns off the output transistor and sets the dead time to 100%. The PWRGOOD terminal (pin 12) is fixed at the “L” level. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.) 14 MB39A106 (4) Timer-latch overvoltage protection circuit block (OVP) When the overvoltage detection comparator (OVP Comp.) provided for each channel detects the DC/DC converter’s output voltage level exceeding its threshold voltage, the timer-latch overvoltage protection circuit actuates the timer circuit and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overvoltage remains applied beyond the predetermined period of time, the circuit sets the latch to turn off the FET on the main side of each channel while setting the PWRGOOD terminal (pin 12) to the “L” level. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (Refer to “3. Setting Overvoltage Detection by the Timer-Latch Overvoltage Protection Circuit” in ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT.) (5) Protection status output circuit block (PWRGOOD) The protection status output circuit outputs the “L” level signal to the PWRGOOD terminal (pin 12) when each protection circuit is actuated. 15 MB39A106 ■ SETTING THE OUTPUT VOLTAGE VO R1 (−INE2) 15 −INE1 1 − + + Error Amp VO (V) = 1.23 R2 (R1 + R2) R2 (CS2) 13 CS1 3 1.23 V < CH1, CH2 > ■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY The triangular oscillation frequency is determined by the timing resistor (RT) connected to the RT terminal (pin 5). Triangular oscillation frequency: fOSC fOSC (kHz) = : 14100 RT (kΩ) 16 MB39A106 ■ SETTING THE SOFT-START AND DISCHARGE TIMES To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 and CS2) to the CS1 terminal (pin 3) for channel 1 and the CS2 terminal (pin 13) for channel 2, respectively. Setting the each control terminals (CTL1 and CTL2) from “L” to “OPEN” switches SW1 and SW2 from B to A to charge the external soft-start capacitors (CS1 and CS2) connected to the CS1 and CS2 terminals at 3 µA. The error amplifier output (FB1 or FB2) is determined by comparison between the lower one of the potentials at two noninverted input terminals (1.23 V, CS terminal voltages) and the inverted input terminal voltage (-INE). The FB terminal voltage during the soft-start period is therefore determined by comparison between the -INE terminal and CS terminal voltages. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor connected to the CS terminal is charged. The soft-start time is obtained from the following equation: Soft-start time: ts (time to output 100%) ts (s) = 0.41 × CS (µF) : Setting the each control terminals (CTL1 and CTL2) from “OPEN” to “L” switches SW1 and SW2 from A to B. Then the IC discharges the soft-start capacitors (CS1 and CS2) charged at about 3.4 V using the internally set discharge resistor (Rs = 6 kΩ) and lowers the output voltage regardless of the DC/DC converter load current. : The discharge time is obtained from the following equation: Discharge time: toff (time to output 10%) toff (s) = 0.020 × CS (µF) : CS terminal voltage = 3.4 V : = 1.23 V : = 0.123 V : =0V : OPEN Error Amp block comparison voltage to −INE voltage Soft-start time (ts) Discharge time (toff) CTL signal L t 17 MB39A106 R1 −INE1 1 (CS2) 13 3 CS1 R2 L priority Error Amp − + + 1.23 V VREF 3 µA 100 kΩ CTL2 CTL1 Open : CH ON L : CH OFF VTH = 1.4 V 10 9 CTL1 = H 6 kΩ Buff A SW1 (SW2) B Soft-start Discharge ■ TREATMENT OF UNUSED CS TERMINALS When the soft-start function is not used, the CS1 terminal (pin 3) and CS2 terminal (pin 13) should be left open. “OPEN” 3 CS1 “OPEN” 13 CS2 < Operation Without Soft-start Setting > 18 MB39A106 ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT 1. Setting Timer-Latch Overcurrent Detection Current The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the main-side FET’s drain and source using the main-side FET ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 11). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the latch to turn off the FETs on the main side and synchronous rectification side of each channel while setting the PWRGOOD terminal (pin 12) to the "L" level. The detection current value can be set by the resistors (RLIM1 and RLIM2) connected between the main-side FET’s drain and the ILIM1 terminal (pin 25) and between the drain and the ILIM2 terminal (pin 23), respectively. The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 5). Internal current value: ILIM ILIM (µA) = : 5546 RT (kΩ) Detection current value: IOCP IOCP (A) = : ILIM(A) × RLIM(Ω) RON (Ω) − (VIN(V) − VO(V)) × VO(V) 2 × VIN(V) × fOSC(Hz) × L(H) RLIM: Overcurrent detection resistor RON: Main-side FET ON resistor VIN: Input voltage VO: DC/DC converter output voltage fOSC: Oscillation frequency L: Coil inductance To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level. VIN M1 (VS2) 18 VS1 28 − Current Protection Logic + 118 µA (ILIM2) 23 ILIM1 25 PWRGOOD 10 µA CTL CTL1 CTL2 VREF S R UVLO 12 CSCP 11 Latch Latch2 19 MB39A106 2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier’s output level to the reference voltage. While the DC/DC converter load conditions are stable on both channels, the short-circuit detection comparator keeps its output at the “H” level and the CSCP terminal (pin 11) remains at the “L” level. If a load condition changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the shortcircuit detection comparator changes its output to the “L” level. This causes the external short-circuit protection capacitor Cscp connected to the CSCP terminal to be charged at 10 µA. Short-circuit detection time (tSCP) : tSCP (s) = 0.070 × CSCP (µF) When capacitor Cscp is charged to the threshold voltage (VTH = 0.70 V), the protection circuit sets the latch and : turns off the external FET (setting the dead time to 100%). At this time, the latch input is closed. As the result, the CSCP terminal is held at the “L” level and the PWRGOOD terminal is set to “L” level. The protection circuit closes both channels even when a short-circuit is detected on only either. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the “L” level. (FB2) VO FB1 14 2 R1 (−INE2) 15 1 −INE1 − + Error Amp R2 1.23 V SCP Comp. + + − PWRGOOD 10 µA CTL CTL1 CTL2 VREF S R UVLO 3.1 V 12 CSCP 11 Latch Latch2 20 MB39A106 3. Setting Overvoltage Detection by the Timer-Latch Overvoltage Protection Circuit An overvoltage output from the DC/DC converter can be detected by connecting external resistors from the DC/ DC converter output to the noninverted input terminal (-INE1 terminal (pin 1) and -INE2 terminal (pin 15)) of the overvoltage comparators (OVP Comp. 1 and OVP Comp. 2). When the DC/DC converter output voltage exceeds the overvoltage detection level, the output of the overvoltage comparator (OVP Comp. 1 and OVP Comp. 2) becomes the “H” level and the overvoltage protection circuit actuates the timer circuit to start charging the external capacitor Cscp connected to the CSCP terminal (pin 11). If the overvoltage remains applied beyond setting time, the circuit sets the latch to turn off the FET on the main side of each channel while setting the PWRGOOD terminal (pin 12) to the “L” level. The protection circuit closes both channels even when an overvoltage is detected on only either. Overvoltage detection voltage : VOVP VOVP (V) = 1.38 × (R1 (Ω) + R2 (Ω) ) / R2 (Ω) = 1.12 × VO : : To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level. VO (−INE2) 15 1 − Error Amp R1 −INE1 R2 + 1.23 V OVP Comp. + − 1.38 V PWRGOOD 10 µA CTL CTL1 CTL2 VREF S R UVLO 12 CSCP 11 Latch Latch2 21 MB39A106 ■ TREATMENT OF UNUSED ILIM TERMINALS When the overcurrent protection circuit is not used, the ILIM1 terminal (pin 25) and ILIM2 terminal (pin 23) should be shorted to the SGND terminal. ILIM1 25 ILIM2 23 7 SGND ■ PROCESSING WITHOUT USING THE CSCP TERMINAL When the timer-latch short-circuit protection circuit is not used, the CSCP terminal (pin 11) should be shorted to SGND using the shortest possible connection. 7 SGND 11 CSCP ■ TREATMENT OF UNUSED PWRGOOD TERMINALS When the PWRGOOD terminal is not used, the PWRGOOD terminal (pin 12) should be shorted or open to the SGND terminal. 7 SGND "Open" 12 PWRGOOD 12 PWRGOOD 22 MB39A106 ■ OUTPUT STATES DURING PROTECTION CIRCUIT OPERATION The table below lists the output states with each protection circuit actuated. CH1 CH2 Output terminal Protection circuit OUT1-1 OUT2-1 OUT1-2 OUT2-2 Overcurrent protection circuit CH1 L L L L L L L L L H H L L L L L L L L L L L L H H L L L CH2 CH1 Overvoltage protection circuit CH2 CH1 Short-circuit protection CH2 Under voltage lockout protection circuit PWRGOOD L L L L L L L ■ RESETTING THE LATCH OF EACH PROTECTION CIRCUIT When the overvoltage, overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch to fix the output at the "L" level. The PWRGOOD terminal (pin 12) is fixed at the "L" level upon abnormality detection by each protection circuit. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the "L" level to lower the VREF terminal (pin 8) voltage to 1.7 V (Min) or less. It can also be reset by setting both of the CTL1 terminal (pin 9) and CTL2 terminal (pin 10) to the "L" level. 23 MB39A106 ■ NOTE ON IC’S INTERNAL POWER CONSUMPTION The oscillation frequency of an IC and the total gate charge of FETs largely affects the internal dissipation of the IC. Pay attention to the following point with respect to the internal power consumption of the IC when applications are used. IB (mean current) is obtained from the following equation, assuming Qg1 and Qg2 as the total gate charges applied to the gate capacitors (Ciss1, Ciss2, Crss1, Crss2) of external FETs Q1 and Q2. Current per channel IB (A) = I1 + I2 = Ibias1 × : t1 t + Qg1 + Ibias2 × t t2 t + Qg2 (Ibias1 = Ibias2 = 3 mA) : t As the current consumption by the IC, excluding IB, is about 15 mA, the power consumption is obtained from the following equation : Power consumption : Pc Pc (W) = 0.015 × VCC (V) + 2 × VCC (V) •IB (A) − VB (V) •IB (A) VIN VCC 24 6V IB 22 VB CVB CB1 Q1 Crss1 OUT1-1 Ciss1 VS1 Ciss2 Crss2 Q2 A L1 V O1 30 I1 Drive 1-1 29 28 I2 Drive 2-1 27 26 OUT2-1 PGND1 t VOUT1-1 VOUT2-1 I1 t1 I2 t2 Bias current Ibias1 = 3 mA : Bias current Ibias2 = 3 mA : t Refer to “Power Consumption vs. Input Voltage” on the next page as a reference and use the above method of obtaining the power consumption to design your application of the IC taking account of the “Power Dissipation vs. Ambient Temperature” characteristic in the ■ TYPICAL CHARACTERISTICS. 24 MB39A106 Power Consumption vs. Input Voltage (Qg Parameter) 1.5 1.4 1.3 Qg1 = Qg2 = 70 nC Power consumption PC (W) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ta = +25 °C fOSC = 300 kHz SW1 = OFF SW2 = OFF Qg1 = Qg2 = 30 nC Qg1 = Qg2 = 20 nC Qg1 = Qg2 = 10 nC Qg1 = Qg2 = 50 nC Input voltage VIN (V) Power Consumption vs. Input Voltage (fOSC Parameter) 1.2 1.1 1.0 Power consumption PC (W) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5 6 7 8 9 10 11 12 13 14 15 16 fOSC = 500 kHz fOSC = 300 kHz fOSC = 200 kHz fOSC = 100 kHz fOSC = 10 kHz Ta = +25 °C Qg1 = Qg2 = 20 nC SW1 = OFF SW2 = OFF 17 18 19 20 Input voltage VIN (V) 25 MB39A106 ■ I/O EQUIVALENT CIRCUIT VCC 24 1.23 V + − < Control block> CTL 6 67 kΩ < Channel control block> VREF (3.5 V) 100 kΩ ESD Protection Element 8 VREF 46.6 kΩ ESD Protection Element CTLX ESD Protection Element 104 kΩ 2 kΩ 24.6 kΩ SGND SGND SGND 7 VREF (3.5 V) < Soft-start block> < Short-circuit protection circuit block> VREF (3.5 V) 2 kΩ < Triangular wave oscillator block (RT) > VREF (3.5 V) 1.40 V + − CSX 400 Ω 11 CSCP 5 RT SGND VCC VSX VREF (3.5 V) 12 PWRGOOD SGND SGND < Overcurrent protection circuit block (CH1, CH2) > ILIMX < Protection status output circuit block> SGND SGND < Error amplifier block (CH1, CH2) > VCC VREF (3.5 V) -INEX CSX 1.23 V FBX VB 22 < Output block main side> CBX 35 kΩ OUT1-X SGND < Output block synchronous rectification side (CH1, CH2) > VB 35 kΩ 100 kΩ VSX SGND OUT2-X X : Each channel No. 100 kΩ GND PGNDX 26 MB39A106 ■ APPLICATION EXAMPLE VCC 24 6V A R13 430 Ω R10 10 kΩ R12 6.2 kΩ VB Reg. C10 FB1 0.022 2 µF R9 13 kΩ 1 −INE1 CS1 3 C11 0.1 µF L priority L priority C16 0.1 µF VB 22 CB1 30 OUT1-1 29 VS1 28 OUT2-1 27 PGND1 26 CH1 Dead Time Modulation 1 VREF 3 µA 100 kΩ Buff Error Amp1 − + + 1.23 V OVP + Comp.1 − 1.38 V PWM + Comp.1 + − Max Duty 81% Dtr ± 6% C9 4.7 µF C3 0.1 µF A Q1 L1 22 µH C25 C18 + 0.1 µF 82 µF C4 + VO1 (2 V/10 A) Drv 1-1 Drv 2-1 150 µF C5 0.1 µF CTL1 9 Open : CH1 ON CTL1 = H L : CH1 OFF 6 kΩ VTH = 1.4 V B R16 120 Ω R15 10 kΩ R17 3.3 kΩ VIN AC/DC Converter (12 V) CTL2 100 kΩ Buff C12 FB2 0.022 14 µF R14 13 kΩ 15 −INE2 CS2 13 C13 0.1 µF L priority PWM L priority Current Protection Logic H: at OCP − + 118 µA ILIM1 25 R1 1.3 kΩ CH2 16 Dead Time Modulation 2 CB2 OUT1-2 VS2 OUT2-2 VREF 3 µA Error Amp2 − + + 1.23 V OVP + Comp.2 − 1.38 V Comp.2 + + − C6 0.1 µF B Q2 L2 22 µH C26 C17 + 0.1 µF 82 µF C7 + VO2 (5 V/5 A) Drv 1-2 17 18 Max Duty 81% Dtr ± 6% Drv 2-2 19 20 PGND2 150 µF C8 0.1 µF 10 Open : CH2 ON CTL2 = H L : CH2 OFF 6 kΩ VTH = 1.4 V H priority Current Protection Logic H: at OCP H: UVLO release − + 118 µA 23 ILIM2 R5 1.3 kΩ SCP Comp. + + − H: at OVP 3.1 V H: at OVP H: at OVP H: at OCP H: at SCP Latch1 SQ CTL CTL1 CTL2 10 µA CSCP 11 C14 0.01 µF CTL CTL1 CTL2 SR Latch Latch2 R L: at protection operation PWRGOOD 12 Protection control signal VREF UVLO OSC 45 pF 3.0 V CT1 1.8 V 3.0 V CT2 1.8 V NC to Error amp reference 1.23 V bias VCC VREF 3.5 V Power VR1 ON/OFF CTL 7 4 NC 21 CTL 6 R4 100 kΩ 5 RT R8 47 kΩ 8 H : ON (Power/ON) L : OFF (Standby mode) VTH = 1.4 V VREF C15 0.1 µF SGND 27 MB39A106 ■ PARTS LIST COMPONENT ITEM SPECIFICATION Main sides: VDS = 30 V, Qg = 9.9 nC (Max) Synchronous sides: VDS = 30 V, Qg = 20.7 nC (Max) SBD: VF = 0.52 V (Max) at IF = 1 A 22 µH 0.1 µF 150 µF 0.1 µF 150 µF 4.7 µF 0.022 µF 0.1 µF 0.022 µF 0.01 µF 0.1 µF 0.1 µF 82 µF 1.3 Ω 100 kΩ 47 kΩ 13 kΩ 10 kΩ 6.2 kΩ 430 Ω 13 kΩ 10 kΩ 120 Ω 3.3 kΩ 3.5 A, 31.6 mΩ 50 V 6.3 V 50 V 6.3 V 10 V 50 V 50 V 50 V 50 V 50 V 50 V 16 V 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % VENDOR PARTS NO. Q1, Q2 Dual FETKYTM IR IRF7901D1 L1, L2 C3, C6 C4 C5, C8 C7 C9 C10 C11, C13 C12 C14 C15, C16 C17, C18 C25, C26 R1, R5 R4 R8 R9 R10 R12 R13 R14 R15 R16 R17 Coil Ceramics Condenser OS-CONTM Ceramics Condenser OS-CONTM Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser OS-CONTM Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor TDK TDK SANYO TDK SANYO TDK TDK TDK TDK TDK TDK TDK SANYO ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm SLF12565T220M3R5 C1608JB1H104K 6SVP150M C1608JB1H104K 6SVP150M C3216JB1A475M C1608JB1H223K C1608JB1H104K C1608JB1H223K C1608JB1H103K C1608JB1H104K C1608JB1H104K 16SVP82M RR0816P132D RR0816P104D RR0816P473D RR0816P133D RR0816P103D RR0816P622D RR0816P434D RR0816P133D RR0816P103D RR0816P124D RR0816P332D Note : IR : International Rectifier Corp. TDK : TDK Corporation SANYO : SANYO Electric Co., Ltd. ssm : SUSUMU Electronics Corp. Dual FETKY is a trademark of International Rectifier Corp. OS-CON is a trademark of SANYO Electric Co., Ltd. 28 MB39A106 ■ SELECTION OF COMPONENTS • N-ch MOS FET The N-ch MOS FET for switching use should be rated for at least 20% more than the maximum input voltage. To minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered. In this application, the IR IRF7901D1 is used. Continuity loss, on/off switching loss, and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values, and also must be in accordance with overcurrent detection levels. Continuity loss : PC PC = ID2 × RDS (ON) × Duty On-cycle switching loss : PS (ON) VD (Max) × ID × tr × fOSC PS (ON) = 6 Off-cycle switching loss : PS (OFF) VD (Max) × ID (Max) × tf × fOSC PS (OFF) = 6 Total loss : PT PT = PC + PS (ON) + PS (OFF) Example: Using the IR IRF7901D1 CH1 Main side Input voltage VIN (Max) = 15 V, output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) = 33 mΩ, tr = 13.8 ns, tf = 8 ns. : Drain current (Max) : ID (Max) VIN (Max) −VO ID (Max) = IO + 2L =3 + 15−3.3 2 × 22 × 10−6 ton × 1 300 × 103 × 0.22 = 3.20 (A) : Drain current (Min) : ID (Min) VIN (Max) −VO ID (Min) = IO − 2L =3 − 15−3.3 2 × 22 × 10−6 ton × 1 300 × 103 × 0.22 = 2.80 (A) : 29 MB39A106 PC1 = ID2 × RDS (ON) × Duty (ON) = 32 × 0.033 × 0.22 = : PS1 (ON) 0.065 W = = VD (Max) × ID × tr × fOSC 6 15 × 3 × 13.8 × 10−9 × 300 × 103 6 = 0.031 W : = = VD (Max) × ID (Max) × tf × fOSC 6 15 × 3.2 × 8 × 10−9 × 300 × 103 6 PS1 (OFF) = 0.019 W : PT1 = PC1 + PS1 (ON) + PS1 (OFF) = 0.065 + 0.031 + 0.019 : = 0.115 W : CH1 (Synchronous rectification side) Input voltage VIN (Max) = 15 V, output voltage VO = 3.3 V, drain current ID = 3 A, oscillation frequency fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) = 28 mΩ, tr = 16.4 ns, tf = 5.2 ns. : Drain current (Max) : ID (Max) VO ID (Max) = IO + toff 2L =3 + 3.3 2 × 22 × 10−6 × 1 300 × 103 × (1−0.22) = 3.20 (A) : Drain current (Min) : ID (Min) VO ID (Min) = IO − toff 2L =3− 3.3 2 × 22 × 10−6 × 1 300 × 103 × (1−0.22) = 2.80 (A) : 30 MB39A106 PC2 = ID2 × RDS (ON) × Duty (OFF) = 32 × 0.028 × (1−0.22) = 0.197 W : PS2 (ON) = = VD (Max) × ID × tr × fOSC 6 15 × 3 × 16.4 × 10−9 × 300 × 103 6 = 0.037 W : PS2 (OFF) = = VD (Max) × ID (Max) × tf × fOSC 6 15 × 3.2 × 5.2 × 10−9 × 300 × 103 6 = 0.012 W : PT2 = PC2 + PS2 (ON) + PS2 (OFF) = 0.197 + 0.037 + 0.012 : = 0.246 W : PT = PT1 + PT2 = 0.115 + 0.246 : = 0.361 W : The above power dissipation figures for the IRF7901D1 are satisfied with ample margin at 2W (Ta = +100 °C) . 31 MB39A106 CH2 (Main side) Input voltage VIN (Max) = 15 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) = 33 mΩ, tr = 13.8 ns, tf = 8 ns. : Drain current (Max) : ID (Max) VIN (Max) −VO ton ID (Max) = IO + 2L =3 + 15−5 1 × 2 × 22 × 10−6 300 × 103 × 0.33 = 3.25 (A) : Drain current (Min) : ID (Min) VIN (Max) −VO ID (Min) = IO + ton 2L =3− = : PC1 15−5 2 × 22 × 10−6 × 1 300 × 103 × 0.33 2.75 (A) = ID2 × RDS (ON) × Duty (ON) = 32 × 0.033 × 0.33 = 0.098 W : PS1 (ON) = = = : PS1 (OFF) = = = : VD (Max) × ID × tr × fOSC 6 15 × 3 × 13.8 × 10−9 × 300 × 103 6 0.031 W VD (Max) × ID (Max) × tf × fOSC 6 15 × 3.25 × 8 × 10−9 × 300 × 103 6 0.020 W PT1 = PC1 + PS1 (ON) + PS1 (OFF) = 0.098 + 0.031 + 0.020 : = 0.149 W : 32 MB39A106 CH2 (Synchronous rectification side) Input voltage VIN (Max) = 15 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 300 kHz, L = 22 µH, drain-source on resistance RDS (ON) = 28 mΩ, tr = 16.4 ns, tf = 5.2 ns. : Drain current (Max) : ID (Max) VO ID (Max) = IO + toff 2L =3 + 5 2 × 22 × 10−6 × 1 300 × 103 × (1−0.33) = 3.25 (A) : VO 2L ID (Min) = IO − =3− toff × 1 300 × 103 × (1−0.33) 5 2 × 22 × 10−6 = 2.75 (A) : PC2 = ID2 × RDS (ON) × Duty (OFF) = 32 × 0.028 × (1−0.33) = 0.169 W : PS2 (ON) = = VD (Max) × ID × tr × fOSC 6 15 × 3 × 16.4 × 10−9 × 300 × 103 6 = 0.037 W : PS2 (OFF) = = VD (Max) × ID (Max) × tf × fOSC 6 15 × 3.25 × 5.2 × 10−9 × 300 × 103 6 = 0.013 W : PT2 = PC2 + PS2 (ON) + PS2 (OFF) = 0.169 + 0.037 + 0.013 : = 0.219 W : PT = PT1 + PT2 (OFF) = 0.149 + 0.219 : = 0.368 W : The above power dissipation figures for the IRF7901D1 are satisfied with ample margin at 2W (Ta = +100 °C) . 33 MB39A106 • Inductors In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light loads. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristics become worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current condition is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L 2 (VIN−VO) ton L≥ IO Example: CH1 L≥ ≥ 2 (VIN (Max) −VO) ton IO 2 × (15−3.3) 3 × 1 × 0.22 300 × 103 ≥ 5.7 µH CH2 L≥ ≥ 2 (VIN (Max) −VO) ton IO 2 × (15−5) 3 × 1 × 0.33 300 × 103 ≥ 7.3 µH Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore necessary to determine the load level at which continuous operation becomes possible. In this application, the TDK SLF12565T-220M3R5 is used. At 22 µH, the load current value under continuous operating conditions is determined by the following formula. Load current value under continuous operating conditions : IO VO IO ≥ toff 2L Example : Using the SLF12565T-220M3R5 22 µH (allowable tolerance ±20%) , rated current = 3.5 A 34 MB39A106 CH1 IO ≥ ≥ VO 2L toff × 1 300 × 103 × (1−0.22) 3.3 2 × 22 × 10−6 ≥ 195 mA CH2 IO ≥ ≥ VO 2L toff × 1 × (1−0.33) 300 × 103 5 2 × 22 × 10−6 ≥ 254 mA To determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak value : IL VIN − VO IL ≥ IO + 2L ton Peak-to-peak value : ∆IL VIN − VO ∆IL = ton L Example: Using the SLF12565T-220M3R5 22 µH (allowable tolerance ±20%) , rated current = 3.5 A Peak value CH1 IL ≥ IO + ≥3+ ≥ 3.20 A CH2 IL ≥ IO + ≥3+ ≥ 3.25 A VIN (Max) −VO 2L 15−5 2 × 22 × 10−6 ton × 1 300 × 103 × 0.33 VIN (Max) −VO ton 2L 15−3.3 2 × 22 × 10−6 × 1 300 × 103 × 0.22 35 MB39A106 Peak-to-peak value: CH1 ∆IL = = VIN (Min) −VO ton L 15−3.3 22 × 10−6 × 1 300 × 103 × 0.22 = 0.39 A : CH2 ∆IL = = VIN (Max) −VO ton L 15−5 22 × 10−6 × 1 300 × 103 × 0.33 = 0.5 A : • Smoothing Capacitor The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smoothing capacitor it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics, and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient margin for allowable ripple current. This application uses the 6SVP150M (OS-CONTM : SANYO) . The ESR, capacitance value, and ripple current can be calculated from the following formulas. Equivalent Series Resistance : ESR ∆VO 1 ESR ≤ − ∆IL 2πfCL Capacitance value : CL ∆I L CL ≥ 2πf (∆VO − ∆IL × ESR) Ripple current : ICLrms (VIN − VO) ICLrms ≥ 2√3L ton Example: Using the 6SVP150M Rated voltage = 6.3 V, ESR = 35 mΩ, maximum allowable ripple current = 2.35 Arms Equivalent series resistance CH1 ESR ≤ ≤ ≤ 36 ∆V O ∆I L 0.033 0.39 − − 1 2πfCL 1 2π × 300 × 103 × 150 × 10−6 81.1 mΩ MB39A106 CH2 ESR ≤ ≤ ∆V O ∆I L 0.05 0.5 − − 1 2πfCL 1 2π × 300 × 103 × 150 × 10−6 ≤ 96.5 mΩ Capacitance value CH1 CL ≥ ≥ ≥ CH2 CL ≥ ≥ ∆IL 2πf (∆VO − ∆IL × ESR) 0.5 2π × 300 × 103 × (0.05 − 0.5 × 0.035) ∆I L 2πf (∆VO − ∆IL × ESR) 0.39 2π × 300 × 103 × (0.033 − 0.39 × 0.035) 10.7 µF ≥ 8.2 µF Ripple current CH1 ICLrms ≥ ≥ (VIN (Max) − VO) 2√3L ton (15 − 3.3) × 0.22 2√3L × 22 × 10−6 × 300 × 103 ≥ 112.6 mArms CH2 ICLrms ≥ ≥ (VIN (Max) − VO) ton 2√3L (15 − 5) × 0.33 2√3L × 22 × 10−6 × 300 × 103 ≥ 114.3 mArms 37 MB39A106 ■ REFERENCE DATA Conversion Efficiency vs. Load Current (CH1) 100 90 Conversion efficiency η (%) 80 70 VIN = 8.5 V VIN = 10 V VIN = 12 V 60 50 40 Ta = + 25 °C 3.3 V output CTL = 5 V CTL1 = Open CTL2 = “L” level 0.10 1.00 10.00 30 0.01 Load current IL (A) Conversion Efficiency vs. Load Current (CH2) 100 90 Conversion efficiency η (%) 80 70 VIN = 8.5 V VIN = 10 V VIN = 12 V 60 50 40 Ta = + 25 °C 5 V output CTL = 5 V CTL1 = “L” level CTL2 = Open 0.10 1.00 10.00 30 0.01 Load current IL (A) (Continued) 38 MB39A106 Switching Waveform (CH1) VS1 (V) 12 10 8 6 4 2 0 Ta = + 25 °C 3.3 V output VIN = 12 V CTL = 5 V CTL1 = Open CTL2 = “L”level VO1 = 3 A 0 1 2 3 4 5 6 7 8 9 10 t (µs) VS1 (V) Expansion VS1 (V) Expansion 2 2 1 1 0 0 0 100 200 300 400 500 (ns) 0 100 200 300 400 500 (ns) tD1 90 ns tD2 150 ns (Continued) 39 MB39A106 Switching Waveform (CH2) VS2 (V) 12 10 8 6 4 2 0 Ta = + 25 °C 5 V output VIN = 12 V CTL = 5 V CTL1 = “L”level CTL2 = Open VO2 = 3 A 0 1 2 3 4 5 6 7 8 9 VS2 (V) 2 Expansion 10 t (µs) VS2 (V) 2 Expansion 1 1 0 0 0 100 200 300 400 500 (ns) 0 100 200 300 400 500 (ns) tD1 tD1 90 ns 160 ns (Continued) 40 MB39A106 (Continued) Soft-start Operating Waveform (CH1) VO1 (V) 4 2 Ta = + 25 °C VIN = 12 V CTL1 = Open CTL2 = “L”level VO1 = 1.2 Ω VO1 0 ts VCTL (V) 5 VCTL 0 36 ms 0 10 20 30 40 50 60 70 80 90 100 (ms) Soft-start Operating Waveform (CH2) VO2 (V) 6 4 2 VO2 0 ts 36 ms VCTL (V) 5 VCTL 0 Ta = + 25 °C VIN = 12 V CTL1 = “L”level CTL2 = Open VO2 = 1.67 Ω 0 10 20 30 40 50 60 70 80 90 100 (ms) 41 MB39A106 ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools, and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage. - Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. ■ PRECAUTIONS ON HANDLING THIS PRODUCT This product has obtained US patents for patent numbers of 6,147,477. ■ ORDERING INFORMATION Part number MB39A106PFT-❏❏❏E1 Package 30-pin plastic TSSOP (FPT-30P-M04) Remarks Lead Free version ■ EV BOARD ORDERING INFORMATION EV board part No. MB39A106EVB EV board version No. Board Rev. 2.0 Remarks TSSOP-30P ■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Fujitsu with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added “E1” at the end of the part number. ■ MARKING FORMAT (LEAD FREE VERSION) M B 3 9 A 106 XXXX XXX E1 INDEX Lead Free version 42 MB39A106 ■ LABELING SAMPLE (LEAD FREE VERSION) Lead-free mark JEITA logo JEDEC logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 G Pb (3N)2 1561190005 107210 QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN 1/1 MB123456P - 789 - GE1 0605 - Z01A 1000 1561190005 Lead Free version 43 MB39A106 ■ MB39A106PFT-❏❏❏E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL Item Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions Condition IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 8 days Please processes within 8 days after baking (125 °C, 24H) 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) [Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) H rank : 260 °C Max 260 °C 255 °C 170 °C ~ 190 °C RT (b) (c) (d) (e) (a) (d') (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60 s to 180 s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10 s or less : Temperature 230 °C or more, 40 s or less or Temperature 225 °C or more, 60 s or less or Temperature 220 °C or more, 80 s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 °C Max Times : 5 s max/pin 44 MB39A106 ■ PACKAGE DIMENSION 30-pin plastic TSSOP Lead pitch Package width × package length Lead shape Sealing method Mounting height 0.50 mm 4.40 × 7.80 mm Gullwing Plastic mold 1.10 mm MAX (FPT-30P-M04) 30-pin plastic TSSOP (FPT-30P-M04) 7.80±0.10(.307±.004) "A" Details of "A" part 0~8° 1.10(.043) MAX 4.40 –0.10 6.40±0.10 +.008 .173 –.004 (.252±.004) 0.25(.010) +0.20 0.60±0.10 (.024±.004) INDEX 0.10±0.05 (.004±.002) 0.50(.020) 0.20±0.03 (.008±.001) 0.3865(.0152) 0.127±0.03 (.005±.001) 0.10(.004) 7.00(.276) 0.90±0.05 (.035±.002) 0.3865(.0152) C 2001 FUJITSU LIMITED F30007SC-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. 45 MB39A106 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0608