HPMX-5002

IF Modulator/Demodulator IC Technical Data HPMX-5002 Features • Use with HPMX-5001 Up/Down Converter Chip for DECT Telephone Applications • 2.7– 5.5 V Single Supply Voltage • >75 dB RSSI Range • Internal Data Slicer • On-chip LO Generation, Including VCO, Prescalers and Phase/ Frequency Detector • Flexible Chip Biasing, Including Standby Mode • Supports Reference Crystal Frequencies of 9, 12, and 16 Times the DECT Bit Rate (1.152 MHz) • IF Input Frequency Range up to 250 MHz • TQFP-48 Surface Mount Package Plastic TQFP-48 Package Description The Hewlett-Packard HPMX-5002 IF Modulator/Demodulator provides all of the active components necessary for the demodulation of a downconverted DECT signal. Designed specifically for DECT, the HPMX-5002 contains a down-conversion mixer (to a 2nd IF), limiting amplifier chain, discriminator/data slicer, lock detector, and RSSI circuits. The LO2 generation is also included on-chip, via a VCO, dividers, and phase/frequency detector. The divide ratios are programmable to support reference frequencies of either 9, 12, or 16 times the DECT bit rate of 1.152 MHz allowing the use of common, low cost crystals. The LO2 VCO can also be utilized in transmit mode by directly modulating the external VCO tank. An AGC loop in the buffered VCO output suppresses harmonics and reduces signal level variability. The HPMX-5002 is designed to meet the size and power demands of portable applications. Battery cell count and cost are reduced due to the 2.7 V minimum supply voltage. The TQFP-48 package, combined with the high level of integration, means smaller footprints and fewer components. Flexible chip biasing takes full advantage of the power savings inherent in time-duplexed systems such as DECT. 5965-9106E X– HPM3 943 5 643 500 2 019 Pin Configuration 48 1 37 36 HPMX–5002 9433 6435 12 13 019 25 24 Applications • DECT, Unlicensed PCS and ISM Band Handsets, Basestations and Wireless LANs 7-105 100 kΩ 4 100 kΩ 5 0.1 µ 3 6 2 7 1 8 100 kΩ = connector = terminal DC post 0.01 µ 0.01 µ 0.01 µ 6 kΩ 1000 p 15 µH 3.9 p 22 p 3 to 10 p 0.01 µ 49.9 Ω 0.01 µ 0.01 µ 0.01 µ 1 kΩ 0.01 µ 10 Ω 0.01 µ 100 p 0.01 µ 1F1P1 10 p 2.7 µH 100 p 0.01 µ 0Ω 3.9 µH VSUB DC1B 48 1 IFOP1 DMOD DMODOP BUF1 BUF2 TCNT DATA SLICER DC1A VCC2 VEE2 BGR XLO PLL NC NC RX 37 36 NC IF1 VEE1 VCC1 0Ω 0.01 µ 10 p 10 Ω 0.01 µ 270 nH 0.01 µ 0.01 µ 270 nH 1p 0Ω 1.2 k Ω 3.9 µH 68 p 4.7 kΩ 22 p 0.01 µ 1p 100 nH 22 p 68 p 4.7 kΩ 0.01 µ 0Ω 1000 p R S S I IP1 IPDC VEE5 VCC5 TCSET DATOP 10 p 20 kΩ 1000 p RSS1 LKFIL LKDET REF 49.9 Ω 8.2 p 0Ω 0Ω 8.2 p 220 nH 8.2 p 1000 p 20 kΩ 20 kΩ 1 kΩ LOCK DET φ Freq. Det. 90/216 OSCOPB OSCOP 9/12/16 CHARGE PUMP VCOADJ VCOB 12 VCOA VCC3 VCC4 VEE3 VEE4 D1V1 D1V2 D1V3 AGC PFD 25 13 24 1 kΩ 1000 p 1000 p NC NC 51.1 Ω 0.01 µ 0Ω 0.01 µ 0Ω 3.9 p 120 n 10 kΩ 22 p 0.01 µ 10 Ω 6 5 4 0.01 µ 0.01 µ 0Ω 0.01 µ 10 Ω 0.01 µ 1 kΩ 4400 p 0.01 µ 0.01 µ 4.7 kΩ 3.3 kΩ 1000 p 1 2 3 1 kΩ 0Ω 0.01 µ 10 kΩ 330 p Figure 1. HPMX-5002 Test Board Schematic Diagram. 7-106 HPMX-5002 Functional Block Diagram IFIP1 IF1 IFOP1 DMOD DMODOP BUF1 BUF2 TCSET IP1 DATA SLICER RSSI DATAOP RSSI DIV2 OSCOP 90/216 OSCOPB CHARGE PUMP φ FREQ. DET. 9/12/16 DIV1 LOCK DET. BIAS CONTROL REF BGR VCOADJ VCOB VCOA DIV3 PFD LKDET PLL RX XLO HPMX-5002 Absolute Maximum Ratings[1] Symbol Parameter VCC Supply Voltage Voltage at any Pin[4] Power Dissipation[2,3] Junction Temperature Storage Temperature Units V V mW °C °C Min. -0.2 -0.2 Max. 7.5 VCC + 0.2 200 +110 +125 Thermal Resistance [2]: θjc = 80°C/W Notes: 1. Operation of this device in excess of any of these parameters may cause permanent damage. 2. Tcase = 25°C 3. Derate at 10 mW/°C for Tcase > 90°C 4. Except CMOS logic inputs, see Summary Characterization Information Table. Pdiss TSTG -55 HPMX-5002 Guaranteed Electrical Specifications Unless otherwise noted, all parameters are guaranteed under the following conditions: 2.7 V < VCC < 5.5 V. Test results are based upon use of networks shown in test diagram (see Figure 1). fin = 110.592 MHz. Typical values are for VCCX = 3.0 V, TA = 25°C. Symbol Parameters and Test Conditions Units Min. Typ. Max. Iccx Total Vccx supply current (PLL locked) (PLL locked) RX mode PLL mode TX “flywheel” mode Standby mode high current mode low current mode input matched to 50 Ω mA mA mA µA µA µA dB 21 16 9 400 30 5 550 50 8 27 20 11.5 100 1000 100 GIF1 VDATOP VDATOP Charge pump current Charge pump current Mixer power gain from IP1 to IF1, external load impedance of 600 Ω Data slicer output level Data slicer output level Logic ‘0’ Logic ‘1’ V V 0.3 Vccx -0.3 7-107 HPMX-5002 Summary Characterization Information Typical values measured on test board shown in Figure 1 at Vccx = 3.0 V, TA = 25°C, fin = 110.592 MHz, fLO2 = 103.68 MHz, unless otherwise noted. Symbol VIH VIL IIH IIL P1 dB IIP3 NFIF1 ZinIP1 Parameters and Test Conditions CMOS input high voltage (can be pulled up as high as Vcc+7V) CMOS input low voltage CMOS input high current CMOS input low current Mode switching time Mixer input 1 dB compression point Mixer input IP3 Mixer SSB noise figure (see test diagram Fig. 1) Mixer input impedance matched to 50 Ω source matched to 50 Ω source input matched to 50 Ω source, 600 Ω load at output 50 MHz < fin < 250 MHz Units V V µA µA µS dBm dBm dB Ω dB mV/dB V Typ. ≥ Vcc -0.8 ≤ 1.0 - 50 50 kΩ Pin 4 Vcc 650 Ω BUF2 BUF2 Pin 5 V Figure 4. HPMX-5002 Internal and Equivalent Circuits, Pins 1-5. 7-114 Circuit in the IC Vcc Small Signal Equivalent Circuit (typical values) DATAOP Pin 8 Vcc Vcc RSSI Pin 9 30 kΩ RSSI Vcc RSSI Pin 11 Vcc VCOA VCOB V Pins 24, 25 Vcc 65 Ω OSCOP OSCOPB OSCOP OSCOPS Pins 27, 28 V Figure 5. HPMX-5002 Internal and Equivalent Circuits, Pins 8, 9, 11, 24, 25, 27, and 28. 7-115 Circuit in the IC Vcc Small Signal Equivalent Circuit (typical values) IP1 Pin 32 IP1 100 Ω Vcc IF1 Pin 35 Vcc V IFIP1 Pin 37 IFIP1 600 Ω Figure 6. HPMX-5002 Internal and Equivalent Circuits, Pins 32, 35, and 37. 7-116 Package Dimensions 48 Pin Thin Quad Flat Package All dimensions shown in mm. 9.0 ± 0.25 7.0 ± 0.1 9.0 ± 0.25 7.0 ± 0.1 0.22 typ. 0.5 1.4 ± 0.05 0.05 min., 0.1 max. 0.6+0.15, -0.10 Part Number Ordering Information Part Number HPMX-5002-STR HPMX-5002-TR1 HPMX-5002-TY1 No. of Devices 10 1000 250 Container Strip Tape and Reel Tray 7-117 Tape Dimensions and Product Orientation for Outline TQFP-48 REEL CARRIER TAPE USER FEED DIRECTION COVER TAPE 2.0 (See Note 7) 0.30 ± 0.05 4.0 (See Note 2) 1.5+0.1/-0.0 DIA 1.75 R 0.5 (2) 1.6 (2) 5.0 BO 019 7.5 (See Note 7) 16.0 ± 0.3 HPMX – 5002 9433 6435 K1 KO 1.5 Min. 6.4 (2) AO 12.0 Cover tape width = 13.3 ± 0.1 mm Cover tape thickness = 0.051 mm (0.002 inch) NOTES: 1. Dimensions are in millimeters 2. 10 sprocket hole pitch cumulative tolerance ±0.2 3. Chamber not to exceed 1 mm in 100 mm 4. Material: black conductive Advantek™ polystyrene 5. AO and BO measured on a plane 0.3 mm above the bottom of the pocket. 6. KO measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 7. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. AO = 9.3 mm BO = 9.3 mm KO = 2.2 mm K1 = 1.6 mm 7-118