Titl
IDT Tsi578
Hardware Manual
April 4, 2016
3
Contents
1.
2.
3.
A.
B.
Signals and Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
Pinlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2
Impedance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3
Tracking Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5
Decoupling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.6
Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.7
Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.8
Testing and Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.9
Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.1
Line Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.2
P_CLK Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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About this Document
This section discusses general document information about the Tsi578. The following topics are
described:
•
“Scope” on page 5
•
“Document Conventions” on page 5
•
“Revision History” on page 6
Scope
The Tsi578 Hardware Manual discusses electrical, physical, and board layout information for
the Tsi578. It is intended for hardware engineers who are designing system interconnect
applications with these devices.
Document Conventions
This document uses a variety of conventions to establish consistency and to help you quickly
locate information of interest. These conventions are briefly discussed in the following sections.
Non-differential Signal Notation
Non-differential signals are either active-low or active-high. An active-low signal has an active
state of logic 0 (or the lower voltage level), and is denoted by a lowercase “b”. An active-high
signal has an active state of logic 1 (or the higher voltage level), and is not denoted by a special
character. The following table illustrates the non-differential signal naming convention.
State
Single-line signal
Multi-line signal
Active low
NAME_b
NAMEn[3]
Active high
NAME
NAME[3]
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Differential Signal Notation
Differential signals consist of pairs of complement positive and negative signals that are
measured at the same time to determine a signal’s active or inactive state (they are denoted by
“_p” and “_n”, respectively). The following table illustrates the differential signal naming
convention.
State
Single-line signal
Multi-line signal
Inactive
NAME_p = 0
NAME_n = 1
NAME_p[3] = 0
NAME_n[3] =1
Active
NAME_p = 1
NAME_n = 0
NAME_p[3] is 1
NAME_n[3] is 0
Symbols
This symbol indicates a basic design concept or information considered helpful.
p
Ti
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that may result in misuse or
damage to the device.
Revision History
April 4, 2016
•
Updated the package diagram in Figure 2
•
Added GCLH, GCLV, GILH, and GILV part numbers to “Ordering Information” on
page 87
May 18, 2012
•
Updated the first paragraph in “Power Sequencing” on page 33
•
Updated the caution above Figure 2
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November 18, 2010
•
Added a note to Table 13
July 2009
This is the production version of the Serial RapidIO Switch. The document has been updated with IDT
formatting. There have been no technical changes.
May 2009
•
Updated “Power” on page 31
November 2008
•
The SP_IO_SPEED default value was updated in Table 3 on page 13
•
The Moisture Sensitivity was improved from four to three in “Package Characteristics” on
page 24
July 2008
•
Updated “Recommended Operating Conditions” on page 30
•
Updated “Power” on page 31
April 2008
•
Information on “Register Requirements Using 125 MHz S_CLK for a 3.125 Gbps Link
Rate” on page 72 was added to“Clocking” on page 71 and the supporting information was
added to “EEPROM Scripts.”
November 2007
•
Information on “P_CLK Programming” on page 75 was added to “Clocking” on page 71.
•
General clarification in “Signals and Package” on page 9, including:
— Any unused signal that is designated a No Connect (N/C) must be left unconnected
— The I2C_SCLK signal description was updated
— The BCE signal description was updated
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April 4, 2016
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1.
Signals and Package
This chapter describes the packaging (mechanical) features for the Tsi578. It includes the
following information:
1.1
•
“Pinlist” on page 9
•
“Signals” on page 10
•
“Package Characteristics” on page 24
•
“Thermal Characteristics” on page 26
Pinlist
The pinlist and ballmap information for the Tsi578 are available by visiting www.idt.com. For
more information, see the following documents:
•
Tsi578 Pinlist
•
Tsi578 Ballmap
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1.2
Signals
Figure 1: Signal Groupings
BCE
TCK
TDI
TDO
TMS
TRST_b
I2C_SCLK
I2C_SD
I2C_DISABLE
HARD_RST_b
SW_RST_b
INT_b
S_CLK_[p,n]
P_CLK
REF_AVDD
MCES
1
1
8
1
8
JTAG
TAP
1
1
1
Ports 0,1
1
1
SP0_T[A,B,C,D]_[p,n]
SP0_R[A,B,C,D]_[p,n]
1
SP0_REXT
1
SP0_AVDD
1
SP0_MODESEL
1
2
IC
SP1_PWRDN
1
1
Reset
1
1
Interrupt
SP2
SP4
SP6
Ports
2 - 13
SP8
SP10
SP12
2
8
Ref Clks
1
8
1
1
Multicast
Ports
14,15
SP14_REXT
1
SP14_AVDD
1
SP14_MODESEL
1
VSS
VDD
Logic
Pwr/Gnd
VSS_IO
VDD_IO
IO
Pwr/Gnd
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SP0, 2, 4 …. 14
VDD
SP14_R[A,B,C,D]_[p,n]
1
1
Port
Config
SP14_T[A,B,C,D]_[p,n]
2
SP14_PWRDN
SP15_PWRDN
SP_IO_SPEED[1:0]
SP_VDD
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1.2.1
Conventions
The following conventions are used in the signal description table:
•
Signals with the suffix “_p” are the positive half of a differential pair.
•
Signals with the suffix “_n” are the negative half of a differential pair.
•
Signals with the suffix “_b” are active low.
Signals are classified according to the types defined in Table 1.
Table 1: Signal Types
Pin Type
Definition
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
SRIO
Differential driver/receiver defined by RapidIO
Interconnect Specification (Revision 1.3)
PU
Pulled Up internal to the Tsi578
PD
Pulled Down internal to the Tsi578
LVTTL
CMOS I/O with LVTTL thresholds
Hyst
Hysteresis
Core Power
Core supply
Core Ground
Ground for core logic
I/O Power
I/O supply
N/C
No connect
These signals must be left unconnected.
1.2.2
Endian Ordering
This document follows the bit-numbering convention adopted by RapidIO Interconnect
Specification (Revision 1.3), where [0:7] is used to represent an 8 bit bus with bit 0 as the
most-significant bit.
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1.2.3
Port Numbering
The following table shows the mapping between port numbers and the physical ports. These port
numbers are used within the destination ID lookup tables for ingress RapidIO ports and in numerous
register configuration fields.
Table 2: Port Numbering
Port Number
RapidIO Port
Mode
0
Serial Port 0 (SP0)
1x or 4x
1
Serial Port 1 (SP1)
1x
2
Serial Port 2 (SP2)
1x or 4x
3
Serial Port 3 (SP3)
1x
4
Serial Port 4 (SP4)
1x or 4x
5
Serial Port 5 (SP5)
1x
6
Serial Port 6 (SP6)
1x or 4x
7
Serial Port 7 (SP7)
1x
8
Serial Port 8 (SP8)
1x or 4x
9
Serial Port 9 (SP9)
1x
10
Serial Port 10 (SP10)
1x or 4x
11
Serial Port 11 (SP11)
1x
12
Serial Port 12 (SP12)
1x or 4x
13
Serial Port 13 (SP13)
1x
14
Serial Port 14 (SP14)
1x or 4x
15
Serial Port 15 (SP15)
1x
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1.2.4
Signal Grouping
The following table lists the signals by group and their recommended termination.
Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Terminationa
PORT n = 1x/4x Mode Serial RapidIO
PORT (n+1) = 1x Mode Serial RapidIO
n = 0, 2, 4, 6, 8, 10, 12, 14
Serial Port Transmit
SP{n}_TA_p
O, SRIO
Port n Lane A Differential Non-inverting Transmit
Data output (4x mode)
No termination required.
Port n Lane A Differential Non-inverting Transmit
Data output (1x mode)
SP{n}_TA_n
O, SRIO
Port n Lane A Differential Inverting Transmit Data
output (4x mode)
No termination required.
Port n Lane A Differential Inverting Transmit Data
output (1x mode)
SP{n}_TB_p
O, SRIO
Port n Lane B Differential Non-inverting Transmit
Data output (4x mode)
Port n+1 Lane B Differential Non-inverting
Transmit Data output (1x mode)
No termination required.
SP{n}_TB_n
O, SRIO
Port n Lane B Differential Inverting Transmit Data
output (4x mode)
Port n+1 Lane B Differential Inverting Transmit
Data output (1x mode)
No termination required.
SP{n}_TC_p
O, SRIO
Port n Lane C Differential Non-inverting Transmit
Data output (4x mode)
No termination required.
SP{n}_TC_n
O, SRIO
Port n Lane C Differential Inverting Transmit Data
output (4x mode)
No termination required.
SP{n}_TD_p
O, SRIO
Port n Lane D Differential Non-inverting Transmit
Data output (4x mode)
No termination required.
SP{n}_TD_n
O, SRIO
Port n Lane D Differential Inverting Transmit Data
output (4x mode)
No termination required.
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Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Terminationa
I, SRIO
Port n Lane A Differential Non-inverting Receive
Data input (4x node)
DC blocking capacitor of
0.1uF in series
Serial Port Receive
SP{n}_RA_p
Port n Lane A Differential Non-inverting Receive
Data input (1x mode)
SP{n}_RA_n
I, SRIO
Port n Lane A Differential Inverting Receive Data
input (4x mode)
DC blocking capacitor of
0.1uF in series
Port n Lane A Differential Inverting Receive Data
input (1x mode)
SP{n}_RB_p
I, SRIO
Port n Lane B Differential Non-inverting Receive
Data input (4x mode)
Port n+1 Lane B Differential Non-inverting
Receive Data input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RB_n
I, SRIO
Port n Lane B Differential Inverting Receive Data
input (4x mode)
Port n+1 Lane B Differential Inverting Receive
Data input (1x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RC_p
I, SRIO
Port n Lane C Differential Non-inverting Receive
Data input (4x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RC_n
I, SRIO
Port n Lane C Differential Inverting Receive Data
input (4x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RD_p
I, SRIO
Port n Lane D Differential Non-inverting Receive
Data input (4x mode)
DC blocking capacitor of
0.1uF in series
SP{n}_RD_n
I, SRIO
Port n Lane D Differential Inverting Receive Data
input (4x mode)
DC blocking capacitor of
0.1uF in series
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Table 3: Signal Descriptions and Recommended Termination
Type
Description
Recommended
Terminationa
SP{n}_REXT
Analog
Used to connect a resistor to VSS to provide a
reference current for the driver and equalization
circuits.
Must be connected to VSS
with a 191-ohm (1%)
resistor.
SP{n}_MODESEL
I/O,
LVTTL,
Selects the serial port operating mode for ports n
and n+1
PD
0 = Port n operating in 4x mode (Port n+1 not
available)
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS_IO.
Pin Name
Serial Port Configuration
1 = Ports n and n+1 operating in 1x mode
Note: The output capability of this pin is used only
in test mode.
Internal pull-down may be
used for logic 0.
Must remain stable for 10 P_CLK cycles after
HW_RST_b is de-asserted in order to be sampled
correctly.
This signal is ignored after reset.
SP{n}_PWRDN
I/O,
LVTTL,
PU
Port n Transmit and Receive Power Down control
This signal controls the state of Port n and Port
n+1
The PWRDN controls the state of all four lanes
(A/B/C/D) of SERDES Macro.
0 = Port n Powered Up. Port n+1 controlled by
SP{n+1}_PWRDN.
1 = Port n Powered Down. Port n+1 Powered
Down.
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS_IO.
Internal pull-up may be
used for logic 1.
Override SP{n}_PWRDN using PWDN_x1 field in
“SRIO MAC x Clock Selection Register” in the
Tsi578 User Manual.
Output capability of this pin is only used in test
mode.
Must remain stable for 10 P_CLK cycles after
HW_RST_B is de-asserted in order to be sampled
correctly.
This signal is ignored after reset.
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Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
SP{n+1}_PWRDN
I/O,
LVTTL,
Port n+1 Transmit and Receive Power Down
control
This signal controls the state of Port n+1. Note
that Port n+1 is never used when 4x mode is
selected for a Serial Rapid IO MAC, and it must
be powered down.
PU
0 = Port n+1 Powered Up
1 = Port n+1 Powered Down
Recommended
Terminationa
Pin must be tied off
according to the required
configuration. Either a 10K
pull up to VDD_IO or a
10K pull-down to VSS_IO.
Internal pull-up may be
used for logic 1.
Override SP{n+1}_PWRDN using PWDN_x4 field
SRIO MAC x Clock Selection Register.
Output capability of this pin is only used in test
mode.
Must remain stable for 10 P_CLK cycles after
HW_RST_B is de-asserted in order to be sampled
correctly.
This signal is ignored after reset.
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Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
I/O,
LVTTL,
Serial Port Transmit and Receive operating
frequency select, bit 1. When combined with
SP_IO_SPEED[0], this pin selects the default
serial port frequency for all ports.
Recommended
Terminationa
Serial Port Speed Select
SP_IO_SPEED[1]
PU
00 = 1.25 Gbit/s
01 = 2.5 Gbit/s
10 = 3.125 Gbit/s (default)
Pin must be tied off
according to the required
configuration. Either a 10K
pull-up to VDD_IO or a
10K pull-down to VSS_IO.
Internal pull-down may be
used for logic 0.
11 = Illegal
Selects the speed at which the ports operates
when reset is removed. This could be at either
HARD_RST_b being de-asserted or by the
completion of a self-reset.
These signals must remain stable for 10 P_CLK
cycles after HW_RST_b is de-asserted in order to
be sampled correctly.
These signals are ignored after reset and
software is able to over-ride the port frequency
setting in the SRIO MAC x Digital Loopback and
Clock Selection register.
The SP_IO_SPEED[1:0] setting is equal to the
IO_SPEED field in SRIO MAC x Clock Selection
Register.
Output capability of this pin is only used in test
mode.
SP_IO_SPEED[0]
I/O,
LVTTL,
PD
See SP_IO_SPEED[1]
Pin must be tied off
according to the required
configuration. Either a 10K
pull-up to VDD_IO or a
10K pull-down to VSS_IO.
Internal pull-up may be
used for logic 1.
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Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
Recommended
Terminationa
Serial Port Lane Ordering Select
SP_RX_SWAP
I, LVTTL,
PD
Configures the order of 4x receive lanes on serial
ports [0,2,4,6,...,14].
0 = A, B, C, D
1 = D, C, B, A
This signal is ignored in 1X mode.
Must remain stable for 10 P_CLK cycles after
HARD_RST_b is de-asserted in order to be
sampled correctly.
No termination required.
Internal pull-down can be
used for logic 0. Pull up to
VDD_IO through 10K if
external pull-up is desired.
Pull down to VSS_IO
through a 10K resistor if an
external pull-down is
desired.
This signal is ignored after reset.
Note: Ports that require the use of lane swapping
for ease of routing will only function as 4x mode
ports. The re-configuration of a swapped port to
dual 1x mode operation results in the inability to
connect to a 1x mode link partner.
SP_TX_SWAP
I, LVTTL,
PD
Configures the order of 4x transmit lanes on serial
ports [0,2,4,6,...,14].
0 = A, B, C, D
1 = D, C, B, A
Must remain stable for 10 P_CLK cycles after
HARD_RST_b is de-asserted in order to be
sampled correctly.
This signal is ignored after reset.
No termination required.
Internal pull-down can be
used for logic 0. Pull up to
VDD_IO through 10K if
external pull-up is desired.
Pull down to VSS_IO
through 10K resistor if an
external pull-down is
desired.
Note: Ports that require the use of lane swapping for
ease of routing only function as 4x mode ports. The
re-configuration of a swapped port to dual 1x mode
operation results in the inability to connect to a 1x
mode link partner.
Clock and Reset
P_CLK
Tsi578 Hardware Manual
April 4, 2016
I,
This clock is used for the register bus clock.
LVTTL
The nominal frequency of this input clock is
100 MHz. For more information on programming
the P_CLK operating frequency, refer to “P_CLK
Programming”.
No termination required.
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Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
S_CLK_p
I,
Differential non-inverting reference clock. The
clock is used for following purposes: SERDES
reference clock, serial port system clock, ISF
clock and test clock.
CML
Recommended
Terminationa
AC coupling capacitor of
0.1uF required.
The maximum frequency of this input clock is
156.25 MHz.
The clock frequency is defined in “Reference
Clock, S_CLK_p/n”.
For more information on the S_CLK operating
frequency, refer to “Line Rate Support”.
S_CLK_n
I,
CML
Differential inverting reference clock. The clock is
used for following purposes: SerDes reference
clock, serial port system clock, ISF clock and test
clock.
AC coupling capacitor of
0.1uF required.
The maximum frequency of this input clock is
156.25 MHz.
The clock frequency is defined in “Reference
Clock, S_CLK_p/n”.
For more information on the S_CLK operating
frequency, refer to “Line Rate Support”.
HARD_RST_b
I
Schmidt-triggered hard reset. Asynchronous
active low reset for the entire device.
Connect to a power-up
reset source.
PU
The Tsi578 does not contain a voltage detector to
generate internal reset.
Refer to “Reset
Requirements”
O, OD,
Interrupt signal (open drain output)
External pull-up required.
Pull up to VDD_IO through
a 10K resistor.
LVTTL,
Hyst,
Interrupts
INT_b
LVTTL,
2mA
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Table 3: Signal Descriptions and Recommended Termination
Recommended
Terminationa
Pin Name
Type
Description
SW_RST_b
O, OD,
Software reset (open drain output): This signal is
asserted when a RapidIO port receives a valid
reset request on a RapidIO link. If self-reset is not
selected, this pin remains asserted until the reset
request is cleared from the status registers. If
self-reset is selected, this pin remains asserted
until the self reset is complete. If the Tsi578 is
reset from the HARD_RST_b pin, this pin is
de-asserted and remains de-asserted after
HARD_RST_b is released.
LVTTL,
2mA
External pull-up required.
Pull up to VDD_IO through
a 10K resistor.
For more information, refer to “Resets” in the
Tsi578 User’s Manual.
Multicast
MCES
I/O,
LVTTL,
PD
Multicast Event Symbol pin.
As an input, an edge (rising or falling) will trigger a
Multicast Event Control Symbol will be sent to all
ports;
As an output, this pin will toggle its value every
time an Multicast Event Control Symbol is
received by any port which is enabled for
Multicast even control symbols.
No termination required.
This pin must not be driven
by an external source until
all power supply rails are
stable.
Must remain stable for 10 P_CLK cycles before
and after a transition.
I2C
I2C_SCLK
I/O, OD,
LVTTL,
PU
8mA
I2C_SD
I/O, OD,
LVTTL,
PU
8mA
Tsi578 Hardware Manual
April 4, 2016
I2C input/output clock, up to 100 kHz.
2C
If an EEPROM is present on the I bus, this
clock signal must be connected to the clock input
of the serial EEPROM on the I2C bus. If an
EEPROM is not present, the recommended
terminations should be used.
I2C input and output data bus (bidirectional open
drain)
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
a minimum 470 ohms
resistor if higher edge rate
is required.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
a minimum 470 ohms
resistor if higher edge rate
required.
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Table 3: Signal Descriptions and Recommended Termination
Recommended
Terminationa
Pin Name
Type
Description
I2C_DISABLE
I, LVTTL,
PD
Disable I2C register loading after reset. When
asserted, the Tsi578 does not attempt to load
register values from I2C.
0 = Enable I2C register loading
No termination required.
Pull up to VDD_IO through
a 10K resistor if I2C
loading is not required.
1 = Disable I2C register loading
Must remain stable for 10 P_CLK cycles after
HARD_RST_b is de-asserted in order to be
sampled correctly.
Note: This signal does not control the slave
accessibility of the interface.
This signal is ignored after reset.
I2C_MA
I, CMOS,
PU
I2C Multibyte Address.
2C
When driven high, I module will expect
multi-byte peripheral addressing; otherwise, when
driven low, single-byte peripheral address is
assumed.
Must remain stable for 10 P_CLK cycles after
HW_RST_b is de-asserted in order to be sampled
correctly.
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS_IO to
change the logic state.
This signal is ignored after reset.
I2C_SA[1,0]
I, CMOS,
PU
I2C Slave Address pins.
The values on these two pins represent the
values for the lower 2 bits of the 7-bit address of
Tsi578 when acting as an I2C slave (see I2C Slave
Configuration register).
The values at these pins can be overridden by
software after reset.
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No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS_IO to
change the logic state.
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22
Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
I2C_SEL
I, CMOS,
PU
I2C Pin Select. Together with the I2C_SA[1,0]
pins, Tsi578 will determine the lower 2 bits of the
7-bit address of the EEPROM address it boots
from.
When asserted, the I2C_SA[1,0] values will also
be used as the lower 2 bits of the EEPROM
address.
When de-asserted, the I2C_SA[1,0] pins will be
ignored and the lower 2 bits of the EEPROM
address are default to 00.
Recommended
Terminationa
No termination required.
Internal pull-up may be
used for logic 1.
Pull up to VDD_IO through
10K resistor if an external
pull-up is desired. Pull
down to VSS_IO to
change the logic state.
The values of the lower 2 bits of the EEPROM
address can be over-ridden by software after
reset.
JTAG TAP Controller
TCK
I, LVTTL,
PD
IEEE 1149.1 Test Access Port Clock input
Pull up to VDD_IO through
10K resistor if not used.
TDI
I, LVTTL,
PU
IEEE 1149.1 Test Access Port Serial Data Input
Pull up to VDD_IO through
a 10K resistor if the signal
is not used or a if higher
edge rate is required.
TDO
O,
LVTTL,
IEEE 1149.1 Test Access Port Serial Data Output
No connect if JTAG is not
used.
2mA
Pull up to VDD_IO through
a 10K resistor if used.
TMS
I, LVTTL,
PU
IEEE 1149.1 Test Access Port Test Mode Select
Pull up to VDD_IO through
a 10K resistor if not used.
TRST_b
I, LVTTL,
PU
IEEE 1149.1 Test Access Port TAP Reset Input
Tie to VSS_IO through a
10K resistor if not used.
This input must be asserted during the assertion
of HARD-RST_b. Afterwards, it may be left in
either state.
Combine the HARD_RST_b and TRST_b signals
with an AND gate and use the output to drive the
TRST_b pin.
Tsi578 Hardware Manual
April 4, 2016
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23
Table 3: Signal Descriptions and Recommended Termination
Pin Name
Type
Description
BCE
I, LVTTL,
PU
Boundary Scan compatibility enabled pin. This
input is used to aid 1149.6 testing.
This signal also enables system level diagnostic
capability using features built into the SerDes. For
more information on this functionality, refer to the
Serial RapidIO Signal Analyzer documentation.
This signal must be tied to VDD_IO during normal
operation of the device, and during JTAG
accesses of the device registers
Recommended
Terminationa
This signal should have
the capability to be
pulled-up or pulled-low.
• The default setting is to
be pulled-up.
• Pulling the signal low
enables the signal
analyzer functionality on
the SerDes
• A 10K resistor to
VDD_IO should be used.
Power Supplies
SP_AVDD
-
Port n and n+1: 3.3V supply for bias generator
circuitry. This is required to be a low-noise supply.
Refer to ““Decoupling
Requirements””
REF_AVDD
-
Analog 1.2V for Reference Clock (S_CLK_p/n).
Clock distribution network power supply.
Refer to ““Decoupling
Requirements””
VDD_IO
-
Common 3.3V supply for LVTTL I/O
Refer to ““Decoupling
Requirements””
VSS
-
Common ground supply for digital logic
Refer to ““Decoupling
Requirements””
VDD
-
Common 1.2V supply for digital logic
Refer to ““Decoupling
Requirements””
SP_VDD
-
1.2V supply for CDR, Tx/Rx, and digital logic for
all RapidIO ports
Refer to ““Decoupling
Requirements””
Common Supply
a. Signals for unused serial ports do not require termination and can be left as N/Cs.
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24
1.3
Package Characteristics
The Tsi578’s package characteristics are summarized in the following table. The following
figures show the top, side, and bottom views of the Tsi578 package.
Table 4: Package Characteristics
Feature
Description
Package Type
Flip-Chip Ball Grid Array (FCBGA)
Ball count
675-ball
Package Body Size
27 mm x 27 mm
JEDEC Specification
95-1 Section 14
Pitch
1.00 mm
Ball pad size
500 um
Soldermask opening
400 um
Moisture Sensitivity Level
3
The capacitors shown in Figure 2 are not present on the Tsi578 package.
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Figure 2: Package Diagram
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26
1.4
Thermal Characteristics
Heat generated by the packaged IC has to be removed from the package to ensure that the IC is
maintained within its functional and maximum design temperature limits. If heat buildup
becomes excessive, the IC temperature may exceed the temperature limits. A consequence of
this is that the IC may fail to meet the performance specifications and the reliability objectives
may be affected.
Failure mechanisms and failure rate of a device have an exponential dependence of the IC
operating temperatures. Thus, the control of the package temperature, and by extension the
Junction Temperature, is essential to ensure product reliability. The Tsi578 is specified safe for
operation when the Junction Temperature is within the recommended limits.
Table 5 shows the simulated Thetajb and Theta jc thermal characteristics of the Tsi578 FCBGA
package.
Table 5: Thermal Characteristics
1.4.1
Interface
Result
Theta jb (junction to board)
11.7 C/watt
Theta jc (junction to case)
0.08 C/watt
Junction-to-Ambient Thermal Characteristics (Theta ja)
The following table shows the simulated Theta ja thermal characteristic of the Tsi578 FCBGA
package. The results in the table are based on a JEDEC Thermal Test Board configuration
(JESD51-9) and do not factor in system level characteristics. As such, these values are for
reference only.
The Theta ja thermal resistance characteristics of a package depend on multiple
system level variables.
Table 6: Simulated Junction to Ambient Characteristics
Theta ja at specified airflow (no Heat Sink)
Tsi578 Hardware Manual
April 4, 2016
Package
0 m/s
1 m/s
2 m/s
Tsi578 FCBGA
14.6 C/watt
13.6 C/watt
12.9 C/watt
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27
1.4.1.1
System-level Characteristics
In an application, the following system-level characteristics and environmental issues must be
taken into account:
•
Package mounting (vertical / horizontal)
•
System airflow conditions (laminar / turbulent)
•
Heat sink design and thermal characteristics (see “Heatsink Requirement and Analysis” on
page 27)
•
Heat sink attachment method (see “Heatsink Requirement and Analysis” on page 27)
•
PWB size, layer count and conductor thickness
•
Influence of the heat dissipating components assembled on the PWB (neighboring effects)
Example on Thermal Data Usage
Based on the ThetaJA data and specified conditions, the following formula can be used to derive
the junction temperature (Tj) of the Tsi578 with a 0m/s airflow:
•
Tj = èJA * P + Tamb.
Where: Tj is Junction Temperature, P is the Power consumption, Tamb is the Ambient
Temperature
Assuming a power consumption (P) of3.5 W and an ambient temperature (Tamb) of 70C, the
resulting junction temperature (Tj) would be 121.1C.
1.4.2
Heatsink Requirement and Analysis
The Tsi578 is packaged in a Flip-Chip Ball Grid Array (FCBGA). With this package
technology, the silicon die is exposed and serves as the interface between package and heatsink.
Where a heatsink is required to maintain junction temperatures at or below specified maximum
values, it is important that attachment techniques and thermal requirements be critically
analyzed to ensure reliability of this interface. Factors to be considered include: surface
preparations, selection of thermal interface materials, curing process, shock and vibration
requirements, and thermal expansion coefficients, among others. Each design should be
individually analyzed to ensure that a reliable thermal solution is achieved.
Both mechanical and adhesive techniques are available for heatsink attachment.
IDT makes no recommendations as to the reliability or effectiveness of either
approach. The designer must critically analyze heatsink requirements, selection
criteria, and attachment techniques.
For heatsink attachment methods that induce a compressive load to the FCBGA package, the
maximum force that can be applied to the package should be limited to 5 gm / BGA ball
(provided that the board is supported to prevent any flexing or bowing). The maximum force for
the Tsi578 package is 3.38 Kg.
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2.
Electrical Characteristics
This chapter provides the electrical characteristics for the Tsi578. It includes the following
information:
2.1
•
“Absolute Maximum Ratings” on page 29
•
“Recommended Operating Conditions” on page 30
•
“Power” on page 31
Absolute Maximum Ratings
Operating the device beyond the listed operating conditions is not recommended. Stressing the
Tsi578 beyond the Absolute Maximum Rating can cause permanent damage.
Table 7 lists the absolute maximum ratings.
Table 7: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Tstorage
Storage Temperature
-55
125
C
VDD_IO
3.3 V DC Supply Voltage
-0.5
4.6
V
3.3 V Analog Supply Voltage
-0.5
4.6
V
1.2 V DC Supply Voltage
-0.3
1.7
V
VI_SP{n}-R{A-D}_{p,n}
SERDES Port Receiver Input Voltage
-0.3
3
V
VO_SP{n}-T{A-D}_{p,n}
SERDES Port VM Transmitter Output Voltage
-0.3
3
V
SP_AVDD
VDD, SP_VDD,
REF_AVDD
SP_AVDD
Transient di/dt
-
0.0917
A/nS
SP_VDD
Transient di/dt
-
0.136
A/nS
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30
Table 7: Absolute Maximum Ratings
2.2
Symbol
Parameter
Min
Max
Unit
VO_LVTTL
LVTTL Output or I/O Voltage
-0.5
VDD_IO +0.5
V
VESD_HBM
Maximum ESD Voltage Discharge Tolerance
for Human Body Model (HBM). [Test
Conditions per JEDEC standard JESD22-A114-B]
-
2000
V
VESD_CDM
Maximum ESD Voltage Discharge Tolerance
for Charged Device Model (CDM). Test
Conditions per JEDEC standard JESD22-C101-A
-
500
V
Recommended Operating Conditions
Table 8 lists the recommended operating conditions.
Continued exposure of IDT's devices to the maximum limits of the specified
junction temperature could affect the device reliability. Subjecting the devices to
temperatures beyond the maximum/minimum limits could result in a permanent
failure of the device.
Table 8: Recommended Operating Conditions
Symbol
Min
Max
Unit
Junction temperature
-40
125
C
3.3 V DC Supply Voltage
2.97
3.63
V
3.3 V Analog Supply Voltage
2.97
3.63
V
VDD,SP_VDD,
REF_AVDD
1.2 V DC Supply Voltage
1.14
1.29
V
IVDD_IO
3.3 V IO Supply Currenta
-
15
mA
ISP_VDD
SerDes Digital Supply Currenta
-
1060
mA
ISP_AVDD
3.3 V SerDes Supply Currenta
-
842
mA
1.2 V Core Supply Currenta
-
2070
mA
1.2 V Ref Clock Supply Current
-
12.5
mA
Tj
VDD_IO
SP_AVDD
IVDD
IREF_AVDD
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Parameter
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31
Table 8: Recommended Operating Conditions
Symbol
Parameter
Min
Max
Unit
Vripple1
Power Supply ripple for Voltage Supplies:
SP_VDD, VDD and VDD_IO
-
100
mVpp
Vripple2
Power Supply ripple for Voltage Supplies:
SP{n}_AVDD, REF_AVDD
-
50
mVpp
External reference resistor current
-
10
uA
IREXT
a. The current values provided are maximum values and dependent on device configuration, such as port
usage, traffic, etc.
2.3
Power
The following sections describe the Tsi578’s power dissipation and power sequencing.
2.3.1
Power Dissipation
The Tsi578’s power dissipation values are dependent on device configuration, such as line rate,
port configuration, and traffic.
The following tables show the power in both 1x and 4x mode configurations in 125C ambient
temperature, typical process and voltage conditions.
1x Mode
Table 9: Tsi578 Power Dissipation in 1x Mode, 16 Links in Operation
Line Rate
1.25 GBaud
2.5 GBaud
3.125 GBaud
VDD_CORE
0.898
1.402
1.668
SP_VDD
0.795
0.737
0.898
SP_AVDD
1.372
1.538
1.749
VDD_IO
0.003
0.003
0.003
Power (W)
3.069
3.680
4.318
Secondary Port Power W)
0.044
0.075
0.099
Primary Port Power (W)
0.297
0.342
0.398
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32
Notes:
•
Power is provided for typical process and voltage, and 25C ambient temperature
•
VDD_CORE supplies the ISF and other internal digital logic
•
SP_VDD supplies the digital portion of the Serial RapidIO SerDes
•
SP_AVDD supplies the analog portion of the Serial RapidIO SerDes
•
VDD_IO supplies power for all non-Serial RapidIO I/O
•
Power is modeled for link utilization of approximately 25%
•
SerDes I/O drive parameters are set to default values in the SRIO MAC x SerDes
Configuration Channel register (TX_BOOST) and the SRIO MAC x SerDes Configuration
Global register (Tx_LVL)
•
The primary port associated with each SerDes must be enabled before any secondary ports
can be used
4x Mode
Table 10: Tsi578 Power Dissipation in 4x Mode, 4 Links in Operation
Line Rate
1.25 GBaud
2.5 GBaud
3.125 GBaud
VDD_CORE
0.833
1.292
1.502
SP_VDD
0.784
0.845
1.063
SP_AVDD
1.381
1.733
2.007
VDD_IO
0.003
0.003
0.003
Power (W)
3.000
3.873
4.576
Port Power (W)
0.332
0.441
0.529
Table 10 Notes:
•
Power is provided for typical process and voltage, and 25C ambient temperature
•
VDD_CORE supplies the ISF and other internal digital logic
•
SP_VDD supplies the digital portion of the Serial RapidIO SerDes
•
SP_AVDD supplies the analog portion of the Serial RapidIO SerDes
•
VDD_IO supplies power for all non-Serial RapidIO I/O
•
Power is modeled for link utilization of approximately 25%
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33
•
2.3.2
SerDes I/O drive parameters (TX_ATTEN, TX_BOOST) are set to default values in the
SRIO MAC x SerDes Configuration Channel register.
Power Sequencing
Power-up option pins that are controlled by a logic device, in addition to all clocks, must not be
driven until all power supply rails to the Tsi578 are stable. External devices also must not be
permitted to sink current from, or source current to, the device because of the risk of triggering
ESD protection or causing a latch-up condition.
The Tsi578 must have the supplies powered-up in the following order:
•
VDD (1.2 V) must be powered up first
•
SP_VDD (1.2 V) and REF_AVDD (1.2 V) should power up at approximately the same
time as VDD
•
Delays between the powering up of VDD, SP_VDD, and REF_AVDD are acceptable.
•
No more than 50ms after VDD is at a valid level, VDD_IO (3.3 V) should be powered up to
a valid level
•
VDD_IO (3.3V) must not power up before VDD (1.2 V)
•
SP_AVDD (3.3V) should power up at approximately the same time as VDD_IO
•
Delays between powering up VDD_IO and SP_AVDD are acceptable
•
SP_AVDD must not power up before SP_VDD
It is recommended that there is no more than 50ms between ramping of the 1.2 V
and 3.3 V supplies. The power supply ramp rates must be kept between 10 V/s and
1x10E6 V/s to minimize power current spikes during power up.
If it is necessary to sequence the power supplies in a different order than that recommended
above, the following precaution must be taken:
•
2.3.2.1
Any power-up option pins must be current limited with 10 K ohms to VDD_IO or VSS_IO
as required to set the desired logic level.
Power-down
Power down is the reverse sequence of power up:
•
VDD_IO (3.3V) and SP_AVDD
•
VDD (1.2V), SP_VDD and REF_AVDD power-down at the same time
•
Or all rails falling simultaneously
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2.4
Electrical Characteristics
This section describes the AC and DC signal characteristics for the Tsi578.
2.4.1
SerDes Receiver (SP{n}_RD_p/n)
Table 11 lists the electrical characteristics for the SerDes Receiver in the Tsi578.
Serial RapidIO signals may be presented to the receiver differential inputs while the switch is in
an un-powered state only if a return current path (VSS) is present between the Tsi578 and the
source of the signal. For example, this situation can occur if the Tsi578 is located on an AMC
card that has been inserted into an active uTCA chassis and the slot power has been left in the
off state.
Table 11: SerDes Receiver Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Notes
ZDI
RX Differential Input
impedance
90
100
110
Ohm
-
VDIFFI
RX Differential Input
Voltage
170
-
1600
mV
-
LCR
RX Common Mode
Return Loss
-
-
6
dB
Over a range 100MHz to 0.8* Baud
Frequency
LDR
RX Differential Return
Loss
-
-
10
dB
Over a range 100MHz to 0.8* Baud
Frequency
VLOS
RX Loss of Input
Differential Level
55
-
-
mV
Port Receiver Input level below which
Low Signal input is detected
-
-
24
ns
Between channels in a given x4 port @
1.25/2.5Gb/s
-
-
22
ns
Between channels in a given x4 port @
3.125Gb/s
-
-
160
ps
Between 20% and 80% levels
TRX_ch_skew
RTR,RTF
RX Channel to
Channel Skew
Tolerance
RX Input Rise/Fall
times
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2.4.2
SerDes Transmitter (SP{n}_TD_p/n)
Table 12 lists the electrical characteristics for the SerDes transmitter in the Tsi578.
Table 12: SerDes Transmitter Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Notes
ZSEO
TX Single-Ended
Output impedance
45
50
55
Ohm
-
ZDO
TX Differential Output
Impedance
90
100
110
Ohm
-
VSW
TX Output Voltage
Swing (Single-ended)
425
600
mVp
-p
VSW (in mV) = ZSEO/2 x Inom x
RIdr/Inom, where Ridr/Inom is the Idr to
Inom ratio
VDIFFO
TX Differential Output
Voltage Amplitude
-
2*VSW
mVp
-p
+/- 2%
VOL
TX Output Low-level
Voltage
-
1.2 VSW
V
-
VOH
TX Output High-level
Voltage
-
1.2
V
-
VTCM
TX common-mode
Voltage
-
1.2 VSW/2
V
-
LDR1
TX Differential Return
Loss
-
-
10
dB
Baud Frequency)/10
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