HFA1305IB

HFA1305 Data Sheet April 1999 File Number 4727 Triple, 560MHz, Low Power, Video Operational Amplifier The HFA1305 is a triple, high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 process. These amplifiers deliver up to 560MHz bandwidth and 1700V/µs slew rate, on only 58mW of quiescent power. They are specifically designed to meet the performance, power, and cost requirements of high volume video applications. The excellent gain flatness and differential gain/phase performance make these amplifiers well suited for component or composite video applications. Video performance is maintained even when driving a double terminated cable (RL = 150Ω), and degrades only slightly when driving two double terminated cables (RL = 75Ω). RGB applications will benefit from the high slew rates, and high full power bandwidth. The HFA1305 is a pin compatible, low power, high performance upgrade for the popular Intersil HA5013, and for the AD8073 and CLC5623, in ±5V applications. Features • Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ • Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . . 560MHz • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 1700V/µs • Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . . . ±0.03dB • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Differential Phase . . . . . . . . . . . . . . . . . . . . 0.03 Degrees • All Hostile Crosstalk (5MHz). . . . . . . . . . . . . . . . . . -60dB • Pin Compatible Upgrade to HA5013, AD8073 and CLC5623 in ±5V Supply Applications Applications • Flash A/D Drivers • Professional Video Processing • Video Digitizing Boards/Systems • Computer Video Plug-In Boards • RGB Preamps Ordering Information PART NUMBER HFA1305IB HA5025EVAL TEMP. RANGE (oC) -40 to 85 PACKAGE 14 Ld SOIC PKG. NO. M14.15 • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications • High Speed Oscilloscopes and Analyzers High Speed Op Amp DIP Evaluation Board Pinout HFA1305 (SOIC) TOP VIEW NC 1 NC 2 NC 3 V+ 4 +IN 1 5 -IN 1 6 OUT 1 7 + + 14 OUT 3 - 13 -IN 3 12 +IN 3 11 V10 +IN 2 9 -IN 2 8 OUT 2 + - - 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HFA1305 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Output Current (Note 2) . . . . . . . . . . . . . . . . .Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability. Electrical Specifications PARAMETER INPUT CHARACTERISTICS Input Offset Voltage VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (NOTE 4) TEST LEVEL TEMP. (oC) HFA1305IB (SOIC) MIN TYP MAX UNITS TEST CONDITIONS A A 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 25 85 -40 25 Full Full 25 85 -40 45 43 43 48 46 46 0.8 0.5 0.5 - 2 3 1 48 46 46 52 48 48 6 10 5 0.5 0.8 0.8 1.2 0.8 0.8 2 5 60 3 4 4 5 8 10 15 25 60 1 3 3 7.5 15 200 6 8 8 mV mV µV/oC dB dB dB dB dB dB µA µA nA/oC µA/V µA/V µA/V MΩ MΩ MΩ µA µA nA/oC µA/V µA/V µA/V Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Input Offset Voltage Power Supply Rejection Ratio ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Non-Inverting Input Bias Current B A A A A A A A A Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Non-Inverting Input Resistance ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V Inverting Input Bias Current B A A A A A A A A Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity ∆VCM = ±1.8V ∆VCM = ±1.8V ∆VCM = ±1.2V B A A A 2 HFA1305 Electrical Specifications PARAMETER Inverting Input Bias Current Power Supply Sensitivity VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 4) TEST LEVEL A A A C B A A f = 100kHz f = 100kHz f = 100kHz B B B TEMP. (oC) 25 85 -40 25 25 25, 85 -40 25 25 25 HFA1305IB (SOIC) MIN ±1.8 ±1.2 TYP 2 4 4 60 1.4 ±2.4 ±1.7 3.5 2.5 20 MAX 5 8 8 UNITS µA/V µA/V µA/V Ω pF V V nV/√Hz pA/√Hz pA/√Hz TEST CONDITIONS ∆VPS = ±1.8V ∆VPS = ±1.8V ∆VPS = ±1.2V Inverting Input Resistance Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS Tests) Input Noise Voltage Density Non-Inverting Input Noise Current Density Inverting Input Noise Current Density TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain AC CHARACTERISTICS (Note 3) -3dB Bandwidth (VOUT = 0.2VP-P, Notes 3, 5) AV = +1 AV = -1 AV = +2 Full Power Bandwidth (VOUT = 5VP-P, Notes 3, 5) AV = +1 AV = -1 AV = +2 Gain Flatness (VOUT = 0.2VP-P, Notes 3, 5) AV = +1, To 25MHz AV = +1, To 50MHz AV = +1, To 100MHz AV = -1, To 25MHz AV = -1, To 50MHz AV = +2, To 25MHz AV = +2, To 50MHz AV = +2, To 100MHz Minimum Stable Gain Crosstalk (AV = +2, All Channels Hostile, Note 5) 5MHz 10MHz C 25 - 500 - kΩ B B B B B B B B B B B B B B A B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 Full 25 25 - 375 420 560 160 260 165 ±0.03 ±0.03 ±0.07 ±0.03 ±0.04 ±0.03 ±0.03 ±0.07 1 -60 -56 - MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB dB dB V/V dB dB OUTPUT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified Output Voltage Swing (Note 5) Output Current (Note 5) Output Short Circuit Current Closed Loop Output Impedance AV = -1, RL = 100Ω A A AV = -1, RL = 50Ω A A B B 25 Full 25, 85 -40 25 25 ±3 ±2.8 50 28 ±3.4 ±3 60 42 90 0.2 V V mA mA mA Ω 3 HFA1305 Electrical Specifications PARAMETER Second Harmonic Distortion (VOUT = 2VP-P, Note 5) Third Harmonic Distortion (VOUT = 2VP-P, Note 5) VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued) (NOTE 4) TEST LEVEL B B B B TEMP. (oC) 25 25 25 25 HFA1305IB (SOIC) MIN TYP -51 -46 -63 -56 MAX UNITS dBc dBc dBc dBc TEST CONDITIONS 10MHz 20MHz 10MHz 20MHz TRANSIENT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P, Note 3) Overshoot (VOUT = 0.5VP-P, VIN tRISE = 1ns, Notes 3, 6) AV = +1 AV = +2 AV = +1, +OS AV = +1, -OS AV = -1, +OS AV = -1, -OS AV = +2, +OS AV = +2, -OS Slew Rate (VOUT = 5VP-P at AV = +2, -1, VOUT = 4VP-P, at AV = +1, Notes 3, 5) AV = +1, +SR AV = +1, -SR AV = -1, +SR AV = -1, -SR AV = +2, +SR AV = +2, -SR Settling Time (VOUT = +2V to 0V Step, Note 5) To 0.1% To 0.05% To 0.025% Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz) Differential Phase (f = 3.58MHz) POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 5) C A A NOTES: 3. The optimum feedback resistor depends on closed loop gain and package type. The following resistors were used for the SOIC characterization: AV = -1, RF = 360Ω; AV = +2, RF = 510Ω; AV = +1, RF = 464Ω, +RS = 649Ω. See the Application Information section for more information. 4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 5. See Typical Performance Curves for more information. 6. Undershoot dominates for output signal swings below GND (e.g., 2VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 2V condition. See the “Application Information” section for details. 25 25 Full ±4.5 5.8 5.9 ±5.5 6.1 6.3 V mA/Op Amp mA/Op Amp VIN = ±2V AV = +2 (Note 3), Unless Otherwise Specified RL = 150Ω RL = 75Ω RL = 150Ω RL = 75Ω B B B B 25 25 25 25 0.02 0.03 0.03 0.06 % % Degrees Degrees B B B B B B B B B B B B B B B B B B 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 1.0 0.8 5 11 7 8 5 10 1230 1350 2500 1900 1700 1700 23 30 37 8.5 ns ns % % % % % % V/µs V/µs V/µs V/µs V/µs V/µs ns ns ns ns 4 HFA1305 Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1305 design is optimized for RF = 510Ω (SOIC) at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback causes the same problems due to the feedback impedance decrease at higher frequencies). However, at higher gains the amplifier is more stable so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For good channel-to-channel gain matching, it is recommended that all resistors (termination as well as gain setting) be ±1% tolerance or better. TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (ACL) -1 +1 +2 +5 +10 RF (Ω) SOIC 360 464 (+RS = 649) 510 200 180 BANDWIDTH (MHz) SOIC 420 375 560 330 140 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and eventual instability. To reduce this capacitance the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 560MHz. By decreasing RS as CL increases (as illustrated in the curve), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. Non-Inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥ 50Ω. This is especially important in inverting gain configurations where the non-inverting input would normally be connected directly to GND. Pulse Undershoot The HFA1305 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figure 6 and Figure 9). This undershoot isn’t present for small bipolar signals, or large positive signals (see Figures 4, 7, 10 and Figures 5, 8). 5 HFA1305 50 SERIES OUTPUT RESISTANCE (Ω) TOP LAYOUT 40 30 20 AV = +2 10 0 0 50 100 150 200 250 300 350 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE BOTTOM LAYOUT Evaluation Board The performance of the HFA1305IB (SOIC) may be evaluated using the HA5025 Evaluation Board and a SOIC to DIP adaptor like the Aries 14-350000-10 part. The schematic for amplifier 1 and the board layout are shown in Figure 2 and Figure 3. Resistors RF, RG and RS may require a change to values applicable to the HFA1305. To order evaluation boards (part number HA5025EVAL), please contact your local sales office. FIGURE 3. EVALUATION BOARD LAYOUT 1 10µF +5V 3 50Ω IN RG OUT 50Ω RS RF 4 5 6 7 + 12 11 10 9 8 GND GND 0.1µF 10µF -5V 0.1µF 2 14 13 - FIGURE 2. EVALUATION BOARD SCHEMATIC 6 HFA1305 Typical Performance Curves 160 AV = +2 120 SOIC OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = +2 SOIC FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL PULSE RESPONSE 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = +2 SOIC OUTPUT VOLTAGE (mV) 160 120 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) AV = -1 SOIC FIGURE 6. LARGE SIGNAL PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = -1 SOIC OUTPUT VOLTAGE (V) 1.6 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = -1 SOIC FIGURE 8. LARGE SIGNAL PULSE RESPONSE FIGURE 9. LARGE SIGNAL PULSE RESPONSE 7 HFA1305 Typical Performance Curves 160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (5ns/DIV.) AV = +1 SOIC VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 1.6 1.2 OUTPUT VOLTAGE (V) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 TIME (5ns/DIV.) AV = +1 SOIC FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL PULSE RESPONSE NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 6 3 VOUT = 200mVP-P SOIC GAIN NORMALIZED PHASE (DEGREES) AV = +2 AV = -1 PHASE AV = +1 0 AV = +1 AV = -1 AV = +2 90 180 270 360 2 1 0 -1 -2 -3 AV = +2 VOUT = 200mVP-P SOIC RF = 1kΩ RF = 1.5kΩ RF = 500Ω RF = 683Ω RF = 750Ω 0 -3 -6 RF = 1.5kΩ 0 90 180 RF = 500Ω 1 10 100 270 360 1000 0.3 1 10 100 FREQUENCY (MHz) 800 FREQUENCY (MHz) FIGURE 12. FREQUENCY RESPONSE FIGURE 13. FREQUENCY RESPONSE vs FEEDBACK RESISTOR 0.3 0.2 NORMALIZED GAIN (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 1 VOUT = 200mVP-P SOIC AV = -1 NORMALIZED GAIN (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 10 FREQUENCY (MHz) 100 -0.8 1 10 FREQUENCY (MHz) 100 RF = 1.5kΩ RF = 750Ω RF = 1kΩ RF = 683Ω AV = +2, SOIC VOUT = 200mVP-P RF = 500Ω AV = +1 AV = +2 AV = +2 FIGURE 14. GAIN FLATNESS FIGURE 15. GAIN FLATNESS vs FEEDBACK RESISTOR 8 PHASE (DEGREES) HFA1305 Typical Performance Curves -42 -43 -44 -45 DISTORTION (dBc) -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) 10MHz DISTORTION (dBc) 20MHz VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -50 -25 0 25 50 75 100 125 10MHz 20MHz TEMPERATURE (oC) FIGURE 16. 2nd HARMONIC DISTORTION vs TEMPERATURE FIGURE 17. 3rd HARMONIC DISTORTION vs TEMPERATURE 3.6 SUPPLY CURRENT (mA / AMPLIFIER) 3.5 3.4 OUTPUT VOLTAGE (V) 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 0 25 50 75 100 125 +VOUT (RL= 50Ω) AV = -1 +VOUT (RL= 100Ω) |-VOUT| (RL= 50Ω) |-VOUT| (RL= 100Ω) 6.6 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 4.5 5 5.5 6 6.5 7 TEMPERATURE (oC) SUPPLY VOLTAGE ( V) FIGURE 18. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 19. SUPPLY CURRENT vs SUPPLY VOLTAGE 0.2 0.15 SETTLING ERROR (%) AV = +2 VOUT = 2V -10 SOIC -20 -30 CROSSTALK (dB) -40 -50 -60 -70 -80 -90 -100 RL = RL = 100Ω 0.1 0.05 0.025 0 -0.025 -0.05 -0.1 -0.15 -0.2 0 5 10 15 20 25 30 TIME (ns) 35 40 45 50 ∞ -110 0.3 1 10 FREQUENCY (MHz) 100 200 FIGURE 20. SETTLING RESPONSE FIGURE 21. ALL HOSTILE CROSSTALK Die Characteristics 9 HFA1305 DIE DIMENSIONS: 79 mils x 118 mils x 19 mils 2000µm x 3000µm x 483µm METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) PASSIVATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT: 240 Metallization Mask Layout HFA1305 NC NC OUT3 -IN3 NC +IN3 V+ V- +IN1 +IN2 -IN1 OUT1 V- OUT2 -IN2 10 HFA1305 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 A1 B C D E α A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 11 HFA1305 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 12