IS62WV1288ALL-70HI

IS62WV1288ALL IS62WV1288BLL 128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 45ns, 55ns, 70ns • CMOS low power operation: 30 mW (typical) operating 15 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply: 1.65V--2.2V VDD (62WV1288ALL) 2.5V--3.6V VDD (62WV1288BLL) • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available • Lead-free available ISSI JUNE 2005 ® DESCRIPTION The ISSI IS62WV1288ALL / IS62WV1288BLL are highspeed, 1M bit static RAMs organized as 128K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV1288ALL and IS62WV1288BLL are packaged in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP (TYPEI), SOP, and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CS2 CS1 OE WE CONTROL CIRCUIT Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 1 IS62WV1288ALL, PIN CONFIGURATION IS62WV1288BLL ISSI 32-pin TSOP (TYPE I) (T), 32-pin sTSOP (TYPE I) (H) ® 36-pin mini BGA (B) (6mm x 8mm) 1 2 3 4 5 6 A B C D E F G H A0 I/O4 I/O5 GND VDD I/O6 I/O7 A9 A1 A2 CS2 WE NC A3 A4 A5 A6 A7 A8 I/O0 I/O1 VDD GND NC OE A10 CS1 A11 NC A16 A12 A15 A13 I/O2 I/O3 A14 A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 CS1 CS2 OE WE I/O0-I/O7 NC VDD GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground 32-pin SOP (Q) NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, IS62WV1288BLL ISSI Value –0.2 to VDD+0.3 –0.2 to +3.8 –65 to +150 1.0 Unit V V °C W ® ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (VDD) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C IS62WV1288ALL 1.65V - 2.2V 1.65V - 2.2V IS62WV1288BLL 2.5V - 3.6V 2.5V - 3.6V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH(2) VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOH = -1 mA IOL = 0.1 mA IOL = 2.1 mA VDD 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –1 –1 Max. — — 0.2 0.4 VDD + 0.2 VDD + 0.3 0.4 0.6 1 1 Unit V V V V V V V V µA µA Notes: 1. Undershoot: –1.0V for pulse width less than 10 ns. Not 100% tested. 2. Overshoot: VDD + 1.0V for pulse width less than 10 ns. Not 100% tested. TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CS1 H X L L L CS2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 3 IS62WV1288ALL, CAPACITANCE(1) Symbol CIN COUT Parameter IS62WV1288BLL ISSI Max. 8 10 Unit pF pF ® Conditions VIN = 0V VOUT = 0V Input Capacitance Input/Output Capacitance Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 62WV1288ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF See Figures 1 and 2 62WV1288BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 1.65V - 2.2V R1(Ω) R2(Ω) VREF VTM 3070 3150 0.9V 1.8V 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 VTM VTM R1 OUTPUT 30 pF Including jig and scope R2 OUTPUT 5 pF Including jig and scope R2 Figure 1 Figure 2 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, IS62WV1288BLL ISSI Max. 70 ns 8 8 5 5 5 0.8 0.8 Unit mA ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV1288ALL (1.65V - 2.2V) Symbol Parameter ICC VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ VDD = Max., CS1 ≥ VDD – 0.2V, CS2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. ICC1 ISB1 mA mA ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. typ.(2) 10 10 5 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=1.8V, TA=25oC. Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV1288BLL (2.5V - 3.6V) Symbol Parameter ICC VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ VDD = Max., CS1 ≥ VDD – 0.2V, CS2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. Max. 45ns 17 17 12 5 5 0.8 0.8 Max. 55 ns 15 15 10 5 5 0.8 0.8 Unit mA ICC1 ISB1 mA mA ISB2 CMOS Standby Current (CMOS Inputs) Com. Ind. typ.(2) 10 10 5 10 10 5 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.0V, TA=25oC. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 5 IS62WV1288ALL, IS62WV1288BLL ISSI 55 ns Min. Max. 55 — 10 — — 0 5 0 10 — 55 — 55 25 20 — 20 — 70 ns Min. Max. 70 — 10 — — 0 5 0 10 — 70 — 70 35 25 — 25 — Unit ns ns ns ns ns ns ns ns ns — 45 — 45 20 15 — 15 — ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time OE to High-Z Output OE to Low-Z Output (2) 45 ns Min. Max. 45 — 10 — — 0 5 0 5 tRC tAA tOHA tACS1/tACS2 tDOE tHZOE(2) tLZOE(2) tHZCS1/tHZCS2 tLZCS1/tLZCS2 (2) CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, AC WAVEFORMS IS62WV1288BLL ISSI ® READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CS1 tACS1/tACS2 tLZOE CS2 tLZCS1/ tLZCS2 HIGH-Z tHZCS DATA VALID DOUT Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 7 IS62WV1288ALL, IS62WV1288BLL ISSI 55 ns Min. Max. 55 45 45 0 0 40 25 0 — 5 — — — — — — — — 20 — 70 ns Min. Max. 70 60 60 0 0 50 30 0 — 5 — — — — — — — — 20 — Unit ns ns ns ns ns ns ns ns ns ns — — — — — — — — 20 — ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CS1/CS2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output 45 ns Min. Max. 45 35 35 0 0 35 20 0 — 5 tWC tSCS1/tSCS2 tAW tHA tSA tPWE tSD tHD tHZWE(3) tLZWE(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW) tWC ADDRESS tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, AC WAVEFORMS IS62WV1288BLL ISSI tWC ® WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 9 IS62WV1288ALL, IS62WV1288BLL ISSI Min. 1.2 — 0 tRC Max. 3.6 5 — — Unit V µA ns ns ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol VDR IDR tSDR tRDR Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CS1 ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform DATA RETENTION WAVEFORM (CS1 Controlled) tSDR VDD Data Retention Mode tRDR VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD tSDR tRDR CS2 VDR CS2 ≤ 0.2V GND 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 IS62WV1288ALL, IS62WV1288BLL ISSI ® ORDERING INFORMATION IS62WV1288ALL (1.65V - 2.2V) Industrial Range: -40°C to +85°C Speed (ns) 70 Order Part No. IS62WV1288ALL-70BI IS62WV1288ALL-70HI Package mini BGA (6mm x 8mm) sTSOP, TYPE I IS62WV1288BLL (2.5V-3.6V) Industrial Range: -40°C to +85°C Speed (ns) 45 Order Part No. IS62WV1288BLL-45TI IS62WV1288BLL-45BI IS62WV1288BLL-45HI IS62WV1288BLL-45QI IS62WV1288BLL-55TI IS62WV1288BLL-55TLI IS62WV1288BLL-55BI IS62WV1288BLL-55HI IS62WV1288BLL-55HLI IS62WV1288BLL-55QI IS62WV1288BLL-55QLI Package TSOP, TYPE I mini BGA (6mm x 8mm) sTSOP, TYPE I SOP TSOP, TYPE I TSOP, TYPE I, Lead-free mini BGA (6mm x 8mm) sTSOP, TYPE I sTSOP, TYPE I, Lead-free SOP SOP, Lead-free 55 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/20/05 11 PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (36-pin) Top View 1 2 3 4 56 6 ISSI Bottom View φ b (36x) ® 5 4 3 2 1 A B C D D E F G H D1 e A B C D E F G H e E E1 Notes: 1. Controlling dimensions are in millimeters. A2 SEATING PLANE A1 A mBGA - 6mm x 8mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.24 0.60 mBGA - 8mm x 10mm INCHES Min. Typ. Max. 36 MILLIMETER Sym. N0. Leads INCHES Min. Typ. Max. 36 Min. Typ. Max. 36 — — — 5.25BSC 5.90 6.00 3.75BSC 0.75BSC 0.30 0.35 0.40 6.10 1.20 0.30 — 8.10 Min. Typ. Max. 36 — 0.24 0.60 — — — 5.25BSC 7.90 8.00 8.10 3.75BSC 0.75BSC 0.30 0.35 0.40 1.20 0.30 — — 0.009 0.024 — — — 0.047 0.012 — A A1 A2 D D1 E E1 e b — 0.009 0.024 — — — 0.047 0.012 — 7.90 8.00 0.311 0.315 0.319 0.207BSC 0.232 0.236 0.240 0.148BSC 0.030BSC 0.012 0.014 0.016 9.90 10.00 10.10 0.390 0.394 0.398 .207BSC 0.311 0.315 0.319 0.148BSC 0.030BSC 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 01/15/03 PACKAGING INFORMATION 450-mil Plastic SOP Package Code: Q (32-pin) ISSI ® N E1 E 1 D SEATING PLANE S A e B L A1 α C MILLIMETERS Symbol No. Leads A A1 B C D E E1 e L α S Min. Max. 32 — 3.00 0.10 — 0.36 0.51 0.15 0.30 20.14 20.75 13.87 14.38 11.18 11.43 1.27 BSC 0.58 0.99 0° 10° — 0.86 INCHES Min. Max. — 0.118 0.004 — 0.014 0.020 0.006 0.012 0.793 0.817 0.546 0.566 0.440 0.450 0.050 BSC 0.023 0.039 0° 10° — 0.034 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03 PACKAGING INFORMATION Plastic STSOP - 32 pins Package Code: H (Type I) A2 A ISSI A1 ® 1 N E b e D1 D S SEATING PLANE L α C Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A — 1.25 — 0.049 A1 0.05 — 0.002 — A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. α 0° 5° 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197H32 Rev. B 04/21/03 PACKAGING INFORMATION Plastic TSOP-Type I Package Code: T (32-pin) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C MILLIMETERS Symbol No. Leads A A1 B C D E H e L α S Min. Max. 32 — 1.20 0.05 0.25 0.17 0.23 0.12 0.17 7.90 8.10 18.30 18.50 19.80 20.20 0.50 BSC 0.40 0.60 0° 8° 0.25 REF INCHES Min. Max. — 0.047 0.002 0.010 0.007 0.009 0.005 0.007 0.311 0.319 0.720 0.728 0.780 0.795 0.020 BSC 0.016 0.024 0° 8° 0.010 REF Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03