IS62WV5128ALL-70T2

IS62WV5128ALL IS62WV5128BLL 512K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V – 2.2V VDD (IS62WV5128ALL) 2.5V – 3.6V VDD (IS62WV5128BLL) • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available ISSI APRIL 2003 ® DESCRIPTION The ISSI IS62WV5128ALL / IS62WV5128BLL are highspeed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62WV5128ALL and IS62WV5128BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin sTSOP (TYPE I), and 32-pin TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CS1 OE WE CONTROL CIRCUIT Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 1 IS62WV5128ALL, PIN DESCRIPTIONS A0-A18 CS1 OE WE I/O0-I/O7 NC VDD GND IS62WV5128BLL ISSI ® Address Inputs Chip Enable 1 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground PIN CONFIGURATION 32-pin TSOP (TYPE I), (Package Code T) 32-pin sTSOP (TYPE I) (Package Code H) 32-pin TSOP (TYPE II) (Package Code T2) A11 A9 A8 A13 WE A18 A15 VDD A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 A18 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI IS62WV5128BLL 2.5V - 3.6V 2.5V - 3.6V 1.65V - 2.2V 1.65V - 2.2V ® OPERATING RANGE (VDD) Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C IS62WV5128ALL ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Related to GND Storage Temperature Power Dissipation Value –0.2 to VDD+0.3 –0.2 to VDD+0.3 –65 to +150 1.0 Unit V V °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOH = -1 mA IOL = 0.1 mA IOL = 2.1 mA VDD 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V Min. 1.4 2.2 — — 1.4 2.2 –0.2 –0.2 –1 –1 Max. — — 0.2 0.4 VDD + 0.2 VDD + 0.3 0.4 0.6 1 1 Unit V V V V V V V V µA µA Notes: 1. VIL (min.) = –1.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 3 IS62WV5128ALL, IS62WV5128BLL ISSI Max. 8 10 Unit pF pF ® CAPACITANCE(1) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load IS62WV5128ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF See Figures 1 and 2 IS62WV5128BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2 IS62WV5128ALL 1.65 - 2.2V R1(Ω) R2(Ω) VREF VTM 3070 3150 0.9V 1.8V IS62WV5128BLL 2.5V - 3.6V 3070 3150 1.5V 2.8V AC TEST LOADS R1 VTM R1 VTM OUTPUT 30 pF Including jig and scope R2 OUTPUT 5 pF Including jig and scope R2 Figure 1 Figure 2 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI Max. 70 ns 25 30 10 10 0.35 0.35 Unit mA mA ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV5128ALL (1.65V - 2.2V) Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. ISB1 VDD = Max., CS1 = 0.2V Com. WE = VDD-0.2V Ind. f=1MHZ VDD = Max., Com. VIN = VIH or VIL Ind. CS1 = VIH, f = 1 MHZ VDD = Max., CS1 ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. mA ISB2 CMOS Standby Current (CMOS Inputs) 15 15 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) 62WV5128BLL (2.5V - 3.6V) Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. Max. 55 ns 40 45 15 15 0.35 0.35 Max. 70 ns 35 40 15 15 0.35 0.35 Unit mA mA ISB1 VDD = Max., CS1 = 0.2V Com. WE = VDD-0.2V Ind. f=1MHZ VDD = Max., Com. VIN = VIH or VIL Ind. CS1 = VIH, f = 1 MHZ VDD = Max., CS1 ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. mA ISB2 CMOS Standby Current (CMOS Inputs) 15 15 15 15 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 5 IS62WV5128ALL, IS62WV5128BLL ISSI 70 ns Min. Max. 70 — 10 — — — 5 0 10 — 70 — 70 35 25 — 25 — Unit ns ns ns ns ns ns ns ns ns — 55 — 55 25 20 — 20 — ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1 Access Time OE Access Time (2) 55 ns Min. Max. 55 — 10 — — — 5 0 10 tRC tAA tOHA tACS1 tDOE tHZOE tLZOE(2) tHZCS1 tLZCS1 OE to High-Z Output OE to Low-Z Output CS1 to High-Z Output CS1 to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT PREVIOUS DATA VALID 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, AC WAVEFORMS IS62WV5128BLL ISSI ® READ CYCLE NO. 2(1,3) (CS1, OE Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CS1 tACS1 tLZOE tLZCS1 tHZCS DATA VALID DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1= VIL. WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 7 IS62WV5128ALL, IS62WV5128BLL ISSI 55 ns Min. Max. 55 45 45 0 0 40 25 0 — 5 — — — — — — — — 20 — 70 ns Min. Max. 70 60 60 0 0 50 30 0 — 5 — — — — — — — — 20 — Unit ns ns ns ns ns ns ns ns ns ns ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter Write Cycle Time CS1 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output tWC tSCS1 tAW tHA tSA tPWE tSD tHD tHZWE(3) tLZWE(3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to VDD-0.2V/VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tSCS1 tHA CS1 tAW WE tSA tHZWE tPWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI tWC ® WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) ADDRESS OE tSCS1 tHA CS1 tAW WE tSA tPWE tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tAW WE tSA tPWE tHZWE HIGH-Z tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 9 IS62WV5128ALL, IS62WV5128BLL ISSI Min. 1.2 — 0 tRC Max. 3.6 15 — — Unit V µA ns ns ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol VDR IDR tSDR tRDR Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.2V, CS1 ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform DATA RETENTION WAVEFORM (CS1 Controlled) tSDR VDD Data Retention Mode tRDR VDR CS1 ≥ VDD CS1 GND - 0.2V 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 IS62WV5128ALL, IS62WV5128BLL ISSI ® ORDERING INFORMATION IS62WV5128ALL (1.65V - 2.2V) Commercial Range: 0°C to +70°C Speed (ns) 70 70 70 Order Part No. IS62WV5128ALL-70T IS62WV5128ALL-70T2 IS62WV5128ALL-70H Package TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I Industrial Range: –40°C to +85°C Speed (ns) 70 70 70 Order Part No. IS62WV5128ALL-70TI IS62WV5128ALL-70T2I IS62WV5128ALL-70HI Package TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I ORDERING INFORMATION IS62WV5128BLL (2.5V - 3.6V) Commercial Range: 0°C to +70°C Speed (ns) 55 55 70 70 70 Order Part No. IS62WV5128BLL-55T2 IS62WV5128BLL-55H IS62WV5128BLL-70T IS62WV5128BLL-70T2 IS62WV5128BLL-70H Package TSOP, TYPE II sTSOP, TYPE I TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I Industrial Range: –40°C to +85°C Speed (ns) 55 55 55 70 70 Order Part No. IS62WV5128BLL-55TI IS62WV5128BLL-55T2I IS62WV5128BLL-55HI IS62WV5128BLL-70TI IS62WV5128BLL-70HI Package TSOP, TYPE I TSOP, TYPE II sTSOP, TYPE I TSOP, TYPE I sTSOP, TYPE I Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 04/30/03 11 PACKAGING INFORMATION Plastic STSOP - 32 pins Package Code: H (Type I) A2 A ISSI A1 ® 1 N E b e D1 D S SEATING PLANE L α C Plastic STSOP (H - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 32 A — 1.25 — 0.049 A1 0.05 — 0.002 — A2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 C 0.14 0.16 0.0055 0.0063 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 e 0.50 BSC 0.020 BSC L 0.30 0.70 0.012 0.028 S 0.28 Typ. 0.011 Typ. α 0° 5° 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197H32 Rev. B 04/21/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) ISSI Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ® N N/2+1 E1 E 1 D N/2 SEATING PLANE ZD A e b L A1 α C Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD α Millimeters Min Max Inches Min Max Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF. 0.032 REF. 0° 5° 0° 5° Millimeters Min Max 50 — 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF. 0° 5° Inches Min Max (N) 32 — 1.20 — 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF. 0.037 REF. 0° 5° 0° 5° — 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 02/20/03 PACKAGING INFORMATION Plastic TSOP - 32 pins Package Code: T (Type I) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C Symbol Ref. Std. No. Leads A A1 B C D E H e L α Plastic TSOP (T—Type I) Millimeters Inches Min Max Min Max 32 — 1.20 0.05 0.25 0.17 0.23 0.12 0.17 7.90 8.10 18.30 18.50 19.80 20.20 0.50 BSC 0.40 0.60 0° 8° — 0.047 0.002 0.010 0.007 0.009 0.006 0.014 0.308 0.316 0.714 0.722 0.772 0.788 0.020 BSC 0.016 0.024 0° 8° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Integrated Silicon Solution, Inc. PK13197T32 Rev. B 01/31/97 1