Buck Regulator, 3.0 A
FAN53527
Descriptions
The FAN53527 is a step−down switching voltage regulator with an
input voltage supply range of 2.5 V to 5.5 V. Device settings can be
programmed through an I2C interface, or the IC can be operated in
stand−alone mode with pin controls for enable, output voltage, and
Auto PFM or Forced PWM operation.
Using a proprietary architecture with synchronous rectification, the
FAN53527 is capable of delivering 3.0 A continuous at over 80%
efficiency, and maintain that efficiency with load currents as low as
10 mA. At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate in Power−Save Mode where excellent
transient response is maintained. In Shutdown Mode, the supply
current drops below 1 mA, further reducing power consumption. At
higher loads, the device automatically transitions to fixed−frequency
PWM control, operating typically at 2.4 MHz.
The FAN53527 is available in a 15−bump, 1.310 mm x 2.015 mm,
0.4 mm ball pitch, Wafer−Level Chip−Scale Package (WLCSP).
Features
•
•
•
•
•
•
•
•
•
•
•
•
I2C Compatible Interface or Stand−Alone Operation
Fixed−Frequency PWM Operation: 2.4 MHz
Auto PFM Mode for High Efficiency at Light−Load
Best−in−Class Load Transient Response
Wide Input Voltage Range: 2.5 V to 5.5 V
Continuous Output Current Capability: 3.0 A
Low Quiescent Current: 48 mA
Low Shutdown Current: 6.5V, PWM Switching
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
2000
Charged Device Model per JESD22−C101
1000
V
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 7V or VIN + 0.3 V.
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VIN
Supply Voltage Range
IOUT
Output Current
Min
Typ
Max
Unit
2.5
5.5
V
0
3.0
A
TA
Operating Ambient Temperature
−40
+85
°C
TJ
Operating Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 7. THERMAL PROPERTIES
Symbol
Parameter
θJA
Junction−to−Ambient Thermal Resistance
NOTE:
Min
Typ
42
Max
Unit
°C/W
Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p
boards with vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction
temperature TJ(max) at a given ambient temperate TA.
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FAN53527
Table 8. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VIN = 3.6 V, TA = −40°C to +85°C, unless
otherwise noted. Typical values are at TA = 25°C, VIN = 3.6 V, and VOUT = 1.081 V.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
IQ
Quiescent Current
EN Pin = VIN, Auto PFM, No Load
48
mA
EN Pin = VIN, Forced PWM, No Load
13
mA
H/W Shutdown Supply Current
EN Pin = GND, SDA/SCL = VIN or
GND, 2.5 V ≤ VIN ≤ 5.5 V
0.1
3.0
mA
Sleep
EN Pin = VIN, [BUCK_ENx] = “0”, SDA/
SCL = VIN or GND, 2.5 V ≤ VIN ≤ 5.5 V
0.1
3.0
mA
VUVLO
Under−Voltage Lockout Threshold
VIN Rising
2.32
2.45
V
VUVHYST
Under−Voltage Lockout Hysteresis
ISD
350
mV
EN, VSEL, MODE, SDA, SCL
VIH
high−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
VIL
low−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
IIN
Input Bias Current
Input Tied to GND or VIN
1.1
V
0.01
0.4
V
1
mA
%
VOUT REGULATION
VREG
Output Voltage Accuracy (Note 2)
Auto PFM, VOUT = 1.0000 to 1.39375 V,
IOUT = 0 to 3 A, 2.5 V ≤ VIN ≤ 5.5 V
−2.5
2.5
Forced PWM, V OUT = 1.0000 to
1.39375 V, IOUT = 0 to 3A, 2.5 V ≤ VIN
≤ 5.5 V
−1.5
1.5
DVOUT / DILOAD
Load Regulation (Note 2)
IOUT = 1 A to 3 A
±0.02
%/A
DVOUT / DVIN
Line Regulation (Note 2)
2.5 V ≤ VIN ≤ 5.5 V, IOUT = 1 A
±0.02
%/V
Transient Response (Note 2)
ILOAD Step 1 mA ⇔ 500 mA,
tr = tf = 100 ns, Forced PWM
±15
mV
ILOAD Step 1 mA ⇔ 500 mA,
tr = tf = 100 ns, Auto PFM
±19
ILOAD Step 1 mA ⇔ 3 A,
tr = tf = 100 ns, Forced PWM
±60
ILOAD Step 1 mA ⇔ 3 A,
tr = tf = 100 ns, Auto PFM
±70
VTRSP
POWER SWITCH / PROTECTION
ILIMPK
P−MOS Peak Current Limit
4.00
4.75
5.50
A
TLIMIT
Thermal Shutdown
150
°C
THYST
Thermal Shutdown Hysteresis
17
°C
VSDWN
Input OVP Shutdown
6.15
V
Rising Threshold
Falling Threshold
5.50
5.73
DAC
Resolution
7
Differential Nonlinearity (Note 2)
Bits
0.5
LSB
SOFT−START
tSS
Regulator Enable to Regulated VOUT RLOAD > 5W, From EN Rising Edge to
95% VOUT and COUT = 2x22 mF
75
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by Design. Characterized on the ATE or Bench.
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FAN53527
Table 9. I2C TIMING SPECIFICATIONS Minimum and maximum values are at VIN = 3.6 V, TA = −40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C, VIN = 3.6 V, and VOUT = 1.081 V. Guaranteed by Design.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
fSCL
tBUF
tHD;STA
tLOW
SCL Clock Frequency
Bus−Free Time between STOP and
START Conditions
START or REPEATED START
Hold Time
SCL LOW Period
Standard Mode
100
Fast Mode
400
Fast Mode Plus
1000
High−Speed Mode, CB ≤ 100 pF
3400
High−Speed Mode, CB ≤ 400 pF
1700
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
Standard Mode
4
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode
160
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
High−Speed Mode, CB ≤ 100 pF
160
High−Speed Mode, CB ≤ 400 pF
320
Standard Mode
tHIGH
tSU;STA
tSU;DAT
tHD;DAT
tRCL
SCL HIGH Period
Repeated START Setup Time
Data Setup Time
Data Hold Time
SCL Rise Time
ms
ms
ns
ms
ns
4
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode, CB ≤ 100 pF
60
High−Speed Mode, CB ≤ 400 pF
120
Standard Mode
4.7
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode
160
Standard Mode
250
Fast Mode
100
Fast Mode Plus
50
High−Speed Mode
10
ms
ns
ms
ns
ns
Standard Mode
0
3.45
Fast Mode
0
900
Fast Mode Plus
0
450
High−Speed Mode, CB ≤ 100 pF
0
70
High−Speed Mode, CB ≤ 400 pF
0
150
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
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6
kHz
ms
ns
ns
FAN53527
Table 9. I2C TIMING SPECIFICATIONS Minimum and maximum values are at VIN = 3.6 V, TA = −40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C, VIN = 3.6 V, and VOUT = 1.081 V. Guaranteed by Design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
POWER SUPPLIES
tFCL
tRCL1
tRDA
tFDA
tSU;STO
CB
SCL Fall Time
Rise Time of SCL After a REPEATED
START Condition and After ACK Bit
SDA Rise Time
SDA Fall Time
Stop Condition Setup Time
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
40
High−Speed Mode, CB ≤ 400 pF
20
80
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
4
Fast Mode
600
Fast Mode Plus
120
High−Speed Mode
160
Capacitive Load for SDA and SCL
7
ns
ns
ns
ms
ns
400
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ns
pF
FAN53527
Timing Diagrams
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÖÖ
ÖÖ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÓÓÓ
ÓÓÓ
tF
SDA
SCL
tSU;STA
tR
TSU;DAT
tHIGH
tLOW
tHD;STA
tHD;DAT
tSU;STA
SCLH
tHD;STO
REPEATED
START
STOP
Figure 3. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÛÛÛ
ÛÛÛ
tFDA
SDAH
tBUF
tHD;STA
START
tRDA
tFCL
REPEATED
START
REPEATED
START
tRCL
tSU;STO
tHIGH
tLOW
tHD;STA
START
ŠŠŠŠ
ÙÙ
ÜÜÜ
ŠŠŠŠÙÙ
ÜÜÜ
ÕÕ
ÕÕ
ÕÕ
ÕÕ
ÕÕ
tSU;DAT
tRCL1
ÌÌÎÎ
ÌÌ
ÎÎ
ÌÌÎÎ
ÌÌ
ÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÒÒ
ÏÏ
ÒÒÏÏ
tHD;DAT
note A
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 4. I2C Interface Timing for High−Speed Mode
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STOP
FAN53527
TYPICAL CHARACTERISTICS
95
95
90
90
85
85
80
3.0Vin
3.6Vin
75
3.8Vin
70
4.6Vin
1
10
100
Load Current (mA)
80
−40°C
+25°C
+85°C
75
70
4.35Vin
65
60
Efficiency (%)
Efficiency (%)
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
TA = 25°C, VIN = 3.6 V, VOUT = 1.081 V, Auto PFM Mode
65
60
1000
1
Figure 5. Efficiency versus Load Current and Input
Voltage
800
Load Current (mA)
Output Voltage (V)
1.08
4.35Vin
1.07
3.8Vin
3.6Vin
1.06
0
500
1000
1500
2000
Load Current (mA)
2500
700
600
500
400
PWM Entry
300
3.0Vin
PFM Entry
200
2.8
3000
Figure 7. Output regulation versus Load Current and
Input Voltage
3000
3.3
3.8
4.3
4.8
Input Voltage (V)
5.3
Figure 8. PWM/PFM Entry Level versus Input Voltage
45
Output Ripple (mV pk−pk)
2500
Frequency (kHz)
1000
900
1.09
2000
1500
3.6Vin FPWM
4.35Vin FPWM
1000
3.6Vin Auto
500
0
100
Load Current (mA)
Figure 6. Efficiency versus Load Current and
Temperature
1.1
1.05
10
4.35Vin Auto
0
500
1000
1500
2000
Load Current (mA)
2500
40
4.35Vin Auto
35
3.6Vin Auto
30
4.35Vin FPWM
25
3.6Vin FPWM
20
15
10
5
0
3000
Figure 9. Frequency versus Load Current versus
Auto PFM and Forced PWM
0
500
1000
1500
2000
Load Current (mA)
2500
Figure 10. Output Ripple versus Load Current
versus Auto PFM and Forced PWM
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9
3000
FAN53527
TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
TA = 25°C, VIN = 3.6 V, VOUT = 1.081 V, Auto PFM Mode
90
35
+85°C
+25°C
−40°C
30
25
20
15
Quiescent Current ( A)
Quiescent Current (mA)
40
10
5
2.8
3.3
3.8
4.3
4.8
Input Voltage (V)
80
60
50
40
30
2.8
5.3
+85°C
+25°C
−40°C
70
Figure 11. Quiescent Current versus Input Voltage
and Temperature in Forced PWM
3.3
3.8
4.3
4.8
Input Voltage (V)
5.3
Figure 12. Quiescent Current versus Input Voltage
and Temperature in Auto PFM
3.6V DC Offset
VEN
1V DC Offset
Figure 13. Line Transient, 3.6 Ve4.2 V, 1A,
10 ms Edge
Figure 14. Start−Up into 5.4 kW Load
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FAN53527
TYPICAL CHARACTERISTICS
Unless otherwise specified; circuit per Typical Application using Recommended External Components,
TA = 25°C, VIN = 3.6 V, VOUT = 1.081 V, Auto PFM Mode
1V DC Offset
1V DC Offset
Figure 15. Load Transient, 1 mAe500 mA,
100 ns Edge, Forced PWM
Figure 16. Load Transient, 1 mAe500 mA,
100 ns Edge, Auto PFM
1V DC Offset
1V DC Offset
Figure 17. Load Transient, 1 mAe3 A, 100 ns Edge,
Forced PWM
Figure 18. Load Transient, 1 mAe3 A, 100 ns Edge,
Auto PFM
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FAN53527
Operating Description
VSEL pin or simply by setting the MODE pin high. See
Table 2.
The FAN53527 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53527
is capable of delivering 3.0 A at over 80% efficiency. The
regulator operates at a nominal frequency of 2.4 MHz at full
load, which reduces the value of the external components to
330 nH or 470 nH for the output inductor and 44 μF for the
output capacitor. High efficiency is maintained at light load
with single−pulse PFM.
An I2C−compatible interface allows transfers up to
3.4 Mbps. This communication interface can be used to:
• Dynamically re−program the output voltage in 6.25 mV
increments;
• Reprogram the mode to enable or disable PFM;
• Control voltage transition slew rate; or
• Enable / disable the regulator
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C can be written to or read from as long as input
voltage is above the UVLO. The registers keep the content
when the EN pin is LOW. The registers are reset to default
values during a Power On Reset (POR). When the
OUTPUT_DISCHARGE bit in the Control register is
enabled (logic HIGH) and the EN pin is LOW or the
BUCK_ENx bit is LOW, an 11 W load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. During soft−start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited,
allowing the IC to start into a pre−charged capacitive load.
If large values of output capacitance are used, the
regulator may fail to start. The maximum COUT capacitance
for starting with a heavy constant−current load is
approximately:
Control Scheme
The FAN53527 uses a proprietary non−linear,
fixed−frequency PWM modulator to deliver a fast load
transient response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results
in a switching frequency that varies with input voltage and
load current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
For very light loads, the FAN53527 operates in
Discontinuous Current Mode (DCM) single−pulse PFM,
which produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition between
DCM and CCM Modes.
PFM can be disabled by programming the MODE bits in
the CONTROL register in combination with the state of the
C OUTMAX [ (I LMPK * I LOAD) @
320m
(eq. 1)
V OUT
where COUTMAX is expressed in μF and ILOAD is the
load current during soft−start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
tri−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both set to “1” by default. These options
start after a POR, regardless of the state of the VSEL pin.
Table 10. HARDWARE AND SOFTWARE ENABLE
Control Pins
BUCK_ENx Bits
EN
VSEL
MODE
BUCK_EN0
BUCK_EN1
Mode Bits
Operation
VOUT
0
X
X
X
X
XX
Shutdown
N/A
1
X
X
0
0
XX
Shutdown
N/A
1
0
0
1
X
X0
Auto PFM
NSEL0
1
0
0
1
X
X1
Forced PWM
NSEL0
1
1
0
X
1
0X
Auto PFM
NSEL1
1
1
0
X
1
1X
Forced PWM
NSEL1
1
0
X
0
X
XX
Shutdown
N/A
1
0
1
1
X
XX
Forced PWM
NSEL0
1
1
X
X
0
XX
Shutdown
N/A
1
1
1
X
1
XX
Forced PWM
NSEL1
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FAN53527
VSEL Pin and I2C Programming Output Voltage
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages,
as shown in Table 1.
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output is given as:
(eq. 2)
V OUT + 1.000 V ) ƪ(NSELx * 64) @ 6.25 mVƫ
Transition Slew Rate Limiting
For example, if NSEL =1010000 (80 decimal), then VOUT
= 1.000 + 0.100 = 1.100 V.
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the Control register, as shown in the table
below.
Table 11. TRANSITION SLEW RATE
Decimal
Bin
Slew Rate
0
000
64.00
mV/ms
1
001
32.00
mV/ms
2
010
16.00
mV/ms
3
011
8.00
mV/ms
4
100
4.00
mV/ms
5
101
2.00
mV/ms
6
110
1.00
mV/ms
7
111
0.50
mV/ms
Thermal Shutdown
Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high−to−low transition begins, the IC stops switching until
VOUT has reached the new set point.
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C hysteresis.
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of
the IC. If the IC is enabled and is regulating, its value is
(1000 0001).
Input Over−Voltage Protection (OVP)
I2C Interface
When VIN exceeds VSDWN (~ 6.2 V), the IC stops
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
The serial interface is compatible with Standard, Fast,
Fast Plus, and HS Mode I2C BusR specifications. The SCL
line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
Current Limiting
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from causing damage. 16 consecutive current limit
cycles in current limit, cause the regulator to shut down and
stay off for about 1700 ms before attempting a restart.
I2C Slave Address
The slave address uses the standard 7 most significant bits
for defining the address and the LSB as the read/write bit. In
doing so, the first word consists of bit [7:5] and the second
word utilizes bits [4:1]. Thus the slave address is 60. Other
slave addresses can be assigned. Contact an
On Semiconductor representative.
Table 12. I2C SLAVE ADDRESS
Bits
Address
7
6
5
4
3
2
1
0
60
1
1
0
0
0
0
0
X
Other slave addresses can be assigned. Contact an ON Semiconductor representative.
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13
FAN53527
Bus Timing
During a read from the FAN53527, the master issues a
REPEATED START after sending the register address and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 22.
As shown in Figure 19 data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow sufficient time for the data to set up before
the next SCL rising edge.
Slave Releases
Data change allowed
tSU;STA
tHD;STA
ACK(0) or
NACK(1)
SDA
SLADDR
MS Bit
SCL
SDA
Figure 22. REPEATED START Timing
tH
tSU
SCL
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical; except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition (Figure 20). The master code is sent in
Fast or Fast−Plus Mode (less than 1 MHz clock); slaves do
not ACK this transmission.
The master generates a REPEATED START condition
(Figure 22) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 21)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 22).
Figure 19. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 20.
tHD;STA
SDA
Slave Address
MS Bit
SCL
Figure 20. START Bit
A transaction ends with a STOP condition, defined as
SDA transitioning from 0 to 1 with SCL high, as shown in
Figure 21.
Slave Releases
Master Drives
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as:
tHD;STO
•
•
ACK(0) or
NACK(1)
SDA
SCL
Master Drives Bus
and
Slave Drives Bus
All addresses and data are MSB first.
Figure 21. STOP Bit
Table 13. I2C BIT DEFINITIONS FOR FIGURE 23 AND FIGURE 24
Symbol
Definition
S
START, see Figure 20
P
STOP, see Figure 21
R
REPEATED START, see Figure 22
A
ACK. The slave drives SDA to 0 acknowledge the preceding packet.
A
NACK. The slave sends a 1 to NACK the preceding packet.
7 bits
S
Slave Address
0
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 23. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
Figure 24. Write Transaction Followed by a Read Transaction
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14
P
FAN53527
REGISTER DESCRIPTION
Table 14. REGISTER MAP
Hex
Address
Name
00
VSEL0
Controls VOUT settings when VSEL pin = LOW
11010100
01
VSEL1
Controls VOUT settings when VSEL pin = HIGH
11001101
02
CONTROL
Determines whether VOUT output discharge is enabled and also the slew rate
of positive transitions
10000000
03
ID1
Read−only register identifies vendor and chip type
10000101
04
ID2
Read−only register identifies die revision
00000000
05
MONITOR
Indicates device status
00000000
Function
Default
Table 15. BIT DEFINITIONS
Bit
Name
Type
Default
VSEL0
Description
Register Address: 00
7
BUCK_EN0
R/W
6:0
NSEL0
R/W
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
1
1010100
VSEL1
Sets the VOUT value for VSEL0 setting. VOUT = 1.000 +
6.25 mV * (d−64); where d is the decimal value of NSEL0 from
64 to 255.
Register Address: 01
7
BUCK_EN1
R/W
6:0
NSEL1
R/W
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
1
1001101
CONTROL
Sets the VOUT value for VSEL1 setting. VOUT = 1.000 +
6.25 mV * (d−64); where d is the decimal value of NSEL1 from
64 to 255.
Register Address: 02
7
OUTPUT_ DISCHARGE
6:4
SLEW
3
Reserved
2
RESET
R/W
R/W
R/W
0
The internal pull−down is not enabled when the converter is
disabled
1
The internal pull−down will be activated when the converter is
disabled
Sets the slew rate for positive voltage transitions. Refer to the
Transition Slew Rate Limiting section for details.
000
0
Always reads back 0.
0
Setting to 1 resets all registers to default values. Always reads
back 0.
In combination with the VSEL and MODE pin, the MODE bits
configure the buck to operate in either Auto PFM or Forced
PWM Mode. The bits are don’t−care if the Mode pin is high.
Refer to the Hardware and Software Enable table for details.
1:0
MODE
R/W
00
7:5
VENDOR
R
100
4
Reserved
R
0
3:0
DIE_ID
R
0101
ID1
Register Address: 03
Signifies On Semiconductor as the IC vendor.
Always reads back 0.
ID2
DIE ID − FAN53527
Register Address: 04
7:4
Reserved
R
0000
3:0
DIE_REV
R
0000
MONITOR
7
Always reads back 0000
FAN53527 Die Revision
Register Address: 05
PGOOD
R
0
1: Buck is enabled and soft−start is completed.
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15
FAN53527
Table 15. BIT DEFINITIONS
Bit
Name
Type
Default
MONITOR
Description
Register Address: 05
6
UVLO
R
0
1: Signifies VIN is less than the UVLO threshold.
5
OVP
R
0
1: Signifies VIN is greater than the OVP threshold.
R
0
4
POS
1: Signifies a positive voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
This bit is set to “1” during IC soft−start.
R
0
3
NEG
1: Signifies a negative voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
This bit is set to “1” during IC soft−start.
2
RESET−STAT
R
0
1: Indicates that a register reset was performed. This bit is
cleared after register 5 is read.
1
OT
R
0
1: Signifies the thermal shutdown is active.
0
BUCK_STATUS
R
0
1: Buck enabled; 0 buck disabled.
APPLICATION INFORMATION
Selecting the Inductor
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (ΔI) of the regulator is:
DI [
V OUT
V IN
@
ǒ
V IN*V OUT
L @ f SW
Ǔ
Inductor Current Rating
The current-limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
(eq. 3)
The maximum average load current, IMAX(LOAD), is
related to the peak current limit, ILIM(PK), by the ripple
current such that:
I MAX(LOAD) + I LIM(PK)*
DI
2
Output Capacitor and VOUT Ripple
(eq. 4)
Increasing COUT has negligible effect on loop stability
and can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, DVOUT,
is calculated by:
The FAN53527 is optimized for operation with
L = 470 nH, but is stable with inductances up to 1.0 μH
(nominal). The inductor should be rated to maintain at least
80% of its value at ILIM(PK). Failure to do so decreases the
amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since ΔI increases, the
RMS current increases, as do core and skin−effect losses:
I RMS +
ǸI
OUT(DC)
2
)
DI 2
12
DV OUT + DI L
ƪ
f SW @ C OUT @ ESR 2
2 @ D @ (1 * D)
)
1
8 @ f SW @ C OUT
ƫ
(eq. 6)
where COUT is the effective output capacitance.
The capacitance of COUT decreases at higher output
voltages, which results in higher DVOUT. Equation 6 is only
valid for CCM operation, which occurs in PWM Mode.
The FAN53527 can be used with either 2 x 22 mF (0603)
or 2 x 47 mF (0603) output capacitor configuration. If a
tighter ripple and transient specification is need from the
FAN53527, then the 2 x 47 mF is recommended.
The lowest DVOUT is obtained when the IC is in PWM
Mode and, therefore, operating at 2.4 MHz. In PFM Mode,
fSW is reduced, causing DVOUT to increase.
(eq. 5)
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs and the inductor
ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs and the inductor
ESR.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
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16
FAN53527
square−wave component of output ripple that results from
the division ratio COUT ESL and the output inductor (LOUT).
The square−wave component due to the ESL can be
estimated as:
DV OUT(SQ) [ V IN @
ESL COUT
L1
2. Calculate total power dissipation using:
ǒ
1
P T + V OUT @ I LOAD @ h * 1
Ǔ
(eq. 8)
3. Estimate inductor copper losses using:
2
(eq. 7)
P L + I LOAD @ DCR L
(eq. 9)
4. Determine IC losses by removing inductor losses
(step 3) from total dissipation:
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value.
To minimize ESL, use capacitors with the lowest ratio of
length to width. Placing additional small−value capacitors
near the load also reduces the high−frequency ripple
components.
P IC + P T * P L
(eq. 10)
5. Determine device operating temperature:
DT + P IC @ Q JA
T IC + T A ) DT
(eq. 11)
and
Note that the RDS(ON) of the power MOSFETs increases
linearly with temperature at about 1.4%/°C. This causes the
efficiency (η) to degrade with increasing die temperature.
Input Capacitor
The ceramic input capacitors should be placed as close as
possible between the VIN and PGND pins to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed between CIN and the power
source lead to reduce under−damped ringing that can occur
between the inductance of the power source leads and CIN.
Layout Recommendations
1. The input capacitor (CIN) should be connected as
close as possible to the VIN and GND pins.
Connect to VIN and GND using only top metal.
Do not route through vias.
2. Place the inductor (L) as close as possible to the
IC. Use short wide traces for the main current
paths.
3. The output capacitor (COUT) should be as close as
possible to the IC. Connection to GND should be
on top metal. Feedback signal connection to
VOUT should be routed away from noisy
components and traces (e.g. SW line). For remote
sensing application, place one or all output
capacitors near the load and if there are also output
capacitors placed near the inductor, the maximum
trace resistance between the inductor and the load
should not exceed 30 mW.
Thermal Considerations
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
resistance (θJA) is largely a function of the PCB layout (size,
copper weight, and trace width) and the temperature rise
from junction to ambient (ΔT).
For the FAN53527, θJA is 42°C/W when mounted on its
four−layer with vias evaluation board in still air with 2 oz.
outer layer copper weight and 1 oz. inner layer.
For long−term reliable operation, the junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (
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