FDMC86260

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET 150 V, 25 A, 34 mΩ Features General Description „ Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. „ Max rDS(on) = 34 mΩ at VGS = 10 V, ID = 5.4 A „ Max rDS(on) = 44 mΩ at VGS = 6 V, ID = 4.8 A „ High Performance Technology for Extremely Low rDS(on) „ 100% UIL Tested Application „ Termination is Lead-free „ DC-DC Conversion „ RoHS Compliant Pin 1 Pin 1 S D D D Top S S S D S D S D G D G D Bottom Power 33 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted. Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID TC = 25 °C TJ, TSTG ±20 V 25 -Continuous TC = 100°C (Note 5) 16 TA = 25 °C (Note 1a) 5.4 -Pulsed PD Units V -Continuous Single Pulse Avalanche Energy EAS (Note 5) Ratings 150 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C (Note 4) 135 (Note 3) 121 54 (Note 1a) Operating and Storage Junction Temperature Range 2.3 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient (Note 1) 2.3 (Note 1a) 53 °C/W Package Marking and Ordering Information Device Marking FDMC86260 Device FDMC86260 ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 Package Power33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET September 2016 Symbol Parameter Test Conditions Min. Typ. Max. Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 120 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 150 V 110 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 5.4 A 27 34 rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 4.8 A 31 44 VGS = 10 V, ID = 5.4 A, TJ = 125 °C 55 69 VDD = 10 V, ID = 5.4 A 19 gFS Forward Transconductance 2 2.7 -9 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 75 V, VGS = 0 V, f = 1 MHz 0.1 1000 1330 pF 105 140 pF 4.8 10 pF 0.6 1.8 Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time VDD = 75 V, ID = 5.4 A, VGS = 10 V, RGEN = 6 Ω 9.5 19 ns 2 10 ns 17 30 ns 3.3 10 ns nC Qg(TOT) Total Gate Charge VGS = 0 V to 10 V 15 21 Qg(TOT) Total Gate Charge VGS = 0 V to 6 V 9.7 14 Qgs Total Gate Charge Qgd Gate to Drain “Miller” Charge VDD = 75 V, ID = 5.4 A nC 4.0 nC 3.1 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 5.4 A (Note 2) 0.77 1.3 V VGS = 0 V, IS = 1.9 A (Note 2) 0.72 1.2 V 64 102 ns 85 137 nC IF = 5.4 A, di/dt = 100 A/μs Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 125 °C/W when mounted on a minimum pad of 2 oz copper a. 53 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 121 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 9 A, VDD = 150 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 22 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 2 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted. 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 48 VGS = 5.5 V VGS = 10 V ID, DRAIN CURRENT (A) VGS = 6 V 36 VGS = 5 V 24 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 12 VGS = 4.5 V VGS = 4.5 V VGS = 5.5 V 2 VGS = 6 V 1 1 2 3 4 0 0 5 12 24 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics 48 120 ID = 5.4 A VGS = 10 V rDS(on), DRAIN TO 2.4 2.0 1.6 1.2 0.8 0.4 -75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 36 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 2.8 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 5.4 A 90 TJ = 125 oC 60 30 TJ = 25 oC 0 -50 3 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 4 5 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs. Junction Temperature Figure 4. On-Resistance vs. Gate to Source Voltage 100 IS, REVERSE DRAIN CURRENT (A) 48 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 VGS = 5 V 3 36 VDS = 5 V 24 TJ = 150 oC TJ = 25 oC 12 TJ = -55 oC 0 2 3 4 5 6 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 7 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 VGS = 0 V Figure 6. Source to Drain Diode Forward Voltage vs. Source Current 3 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted. 2000 ID = 5.4 A 1000 VDD = 75 V 8 Ciss CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 100 V VDD = 50 V 6 4 100 Coss 10 f = 1 MHz VGS = 0 V 2 0 0 4 8 12 1 0.1 16 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs. Drain to Source Voltage 30 ID, DRAIN CURRENT (A) 20 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 25 20 VGS = 10 V 15 VGS = 6 V 10 o RθJC = 2.3 C/W 5 1 0.001 0.1 1 10 0 25 20 50 P(PK), PEAK TRANSIENT POWER (W) 10 1 100 µs 0.1 1 ms 10 ms 100 ms THIS AREA IS LIMITED BY rDS(on) SINGLE PULSE TJ = MAX RATED TA = 25 oC 0.001 0.01 0.1 1s 10 s CURVE IS BENT TO ACTUAL DATA 1 10 DC 100 800 VDS, DRAIN to SOURCE VOLTAGE (V) 150 2000 1000 SINGLE PULSE RθJA = 125 oC/W TA = 25 oC 100 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 125 Figure 10. Maximum Continuous Drain Current vs. Case Temperature 200 100 RθJA = 125 oC/W 100 o Figure 9. Unclamped Inductive Switching Capability 0.01 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) Crss Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted. 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 0.0005 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 5 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted. 3.40 3.20 PKG CL 8 2.37 MIN A (0.45) 8 B 5 PKG CL 3.40 3.20 PKG CL SYM CL 5 2.15 MIN (0.40) (0.65) 0.70 MIN PIN 1 IND ICATOR 1 4 1 4 0.65 1.95 SEE D ETAIL A 0.42 MIN (8X) LAN D PAT TE RN R EC OM MEN D ATION 1.95 0.10 C A B 0.37 (8X) 0.27 0.65 1 4 0.50 0.30 PKG CL 2.05 1.85 8 (0.34) (0.52 TYP) NOTES: U NLESS OT HERWISE SPECIFIED A) PACKAGE STAND ARD REFERENC E: JED EC MO-240, ISSU E A, VAR. BA, DATED O CTOBER 2002. B) ALL D IMENSION S AR E IN MILLIMET ER S. C ) D IMEN SIONS D O NOT IN CLU DE BU RRS OR MOLD FLASH . MOLD FLASH OR BUR RS D OES NOT EXC EED 0.10MM. D ) D IMEN SIONIN G AND TOLERANC ING PER ASME Y14.5M-1994. E) D RAWIN G FILE NAME: PQFN 08HREV1 5 (0.33) TYP (2.27) 0.10 C 0.80 0.70 0.08 C 0.25 0.15 0.05 0.00 C SEATING PLANE DE TA IL A SC ALE: 2X Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 6 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET Dimensional Outline and Pad Layout AccuPower™ AttitudeEngine™ Awinda® AX-CAP®* BitSiC™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED® Dual Cool™ EcoSPARK® EfficentMax™ ESBC™ ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FastvCore™ FETBench™ FPS™ F-PFS™ FRFET® Global Power ResourceSM GreenBridge™ Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ Marking Small Speakers Sound Louder and Better™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ MotionGrid® MTi® MTx® MVN® mWSaver® OptoHiT™ OPTOLOGIC® OPTOPLANAR® ®* ® tm Power Supply WebDesigner™ PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ Solutions for Your Success™ SPM® STEALTH™ SuperFET® SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS® SyncFET™ Sync-Lock™ TinyBoost® TinyBuck® TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TranSiC™ TriFault Detect™ TRUECURRENT®* μSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ VoltagePlus™ XS™ Xsens™ 仙童 ® *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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I77 ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 7 www.fairchildsemi.com FDMC86260 N-Channel Shielded Gate PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 3.40 3.20 PKG CL 8 2.37 MIN A (0.45) 8 B 5 PKG CL 3.40 3.20 PKG CL SYM CL 5 2.15 MIN (0.40) (0.65) 0.70 MIN PIN 1 INDICATOR 1 4 1 4 0.65 1.95 SEE DETAIL A 0.42 MIN (8X) LAND PATTERN RECOMMENDATION 1.95 0.10 C A B 0.37 (8X) 0.27 0.65 1 4 0.50 0.30 PKG CL 2.05 1.85 5 8 (0.34) (0.52 TYP) (0.33) TYP (2.27) 0.10 C 0.80 0.70 0.08 C 0.25 0.15 0.05 0.00 C SEATING PLANE SCALE: 2X NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. BA, DATED OCTOBER 2002. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. 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