NCV4263-2C
LDO Regulator - Enable,
Reset, Watchdog
200 mA
The NCV4263−2C is a 200 mA LDO regulator with integrated reset
watchdog functions dedicated for microprocessor applications. Its
robustness allows NCV4263−2C to be used in severe automotive
environments. The Enable function can be used for decrease of
quiescent current down to max 10 mA. The NCV4263−2C contains
protection functions as current limit, thermal shutdown and reverse
output current protection. The regulator provides also Watchdog,
Reset function with adjustable Threshold and adjustable Power−on
Reset Delay Time.
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MARKING
DIAGRAMS
8
8
1
Features
•
•
•
•
•
•
•
•
•
•
Output Voltage Option: 5 V
Output Voltage Accuracy: ±2%
Output Current up to 200 mA
Very Low Dropout Voltage
Enable Function (10 mA Max Quiescent Current when Disabled)
Microprocessor Compatible Control Functions:
− Reset with Adjustable Threshold and Adjustable Power−on Delay
− Watchdog Function
Wide Input Voltage Operation Range: up to 40 V
Protection Features:
− Current Limitation
− Thermal Shutdown
− Reverse Output Current
AEC−Q100 Grade 1 Qualified and PPAP Capable
These are Pb−Free Devices
V632C5
ALYWX
SOIC−8 EP
PD SUFFIX
CASE 751AC
1
14
14
1
SOIC−14
D SUFFIX
CASE 751A
NCV4263−2C50G
AWLYWWG
1
A
L, WL
Y
W, WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Typical Applications
•
•
•
•
Body Control Module
Instruments and Clusters
Occupant Protection and Comfort
Powertrain
Vin
Vout
Vin
Cin
100 nF NCV4263−2C
Cout
22 mF
RADJ
OFF
ON
EN
GND
RO
WDI
D
VDD
RRO*
5.6 kW
Microprocessor
RESET
I/O
CD
100 nF
*−optional if Reset function is needed
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2015
September, 2019 − Rev. 1
1
Publication Order Number:
NCV4263−2C/D
NCV4263−2C
Vin
Vout
VOLTAGE
VREF
REFERENCE
RO
SP
ENABLE
EN
WDI
SATURATION
VREF
SP
PROTECTION
RESET
GENERATOR
and
WATCHDOG
TSD
THERMAL
D
TSD
SHUTDOWN
RADJ
GND
Figure 2. Simplified Block Diagram
Vin
1
8
RO
14
EN
Vin
NC
Vout
EN
WDI
RO
RADJ
GND
1
D
SOIC−8 EP
GND
GND
GND
GND
GND
GND
D
Vout
RADJ
WDI
SOIC−14
Figure 3. Pin Connections
(Top View)
PIN FUNCTION DESCRIPTION
Pin No.
SO−8 EP
Pin No.
SO−14
Pin Name
1
13
Vin
Positive Power Supply. Connect ceramic capacitor to ground.
2
14
EN
Enable Input. Low level disables the chip. Connect to Vin if this function is not needed.
3
1
RO
Reset Output; Open Collector connected to the Vout via an internal 30 kW pull−up resistor;
leave open if the function is not needed
4
3, 4, 5,
10, 11, 12
GND
5
6
D
6
7
RADJ
7
8
WDI
Watchdog Input. Rising edge triggered Input for watchdog pulses. Connect to GND if this
function is not needed.
8
9
Vout
Regulated Output Voltage. Connect a Cout ≥ 22 mF capacitor to ground.
EPAD
−
Exposed
Pad
−
2
NC
Description
Power Supply Ground. Connect pins to heat sink area with GND potential.
DelayTiming. Connect to GND via ceramic capacitor for adjusting reset delay timing and
watchdog trigger time or leave open if this function is not needed.
Reset Adjust Threshold. Connect to GND (VRT = 93% of Vout) or to output voltage divider to
adjust the reset threshold.
Connect to ground potential or leave unconnected.
Not connected. No internally bonded.
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2
NCV4263−2C
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
Input Voltage (Note 1)
Rating
Vin
−42
45
V
Enable Input
VEN
−42
45
V
Output Voltage
Vout
−1
7
V
Reset Output Voltage
VRO
−0.3
7
V
Watchdog Input Voltage
VWDI
−0.3
7
V
Reset Adjust Threshold
VRADJ
−0.3
7
V
Delay Timing Output Voltage
VD
−0.3
7
V
Maximum Junction Temperature
TJ
−40
150
°C
TSTG
−55
150
°C
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ESD CAPABILITY (Note 2)
Rating
Symbol
Min
Max
Unit
ESD Capability, Human Body Model
ESDHBM
−
2
kV
ESD Capability, Charged Device Model
ESDCDM
−
1
kV
Min
Max
Unit
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
LEAD SOLDERING TEMPERATURE AND MSL (Note 3)
Rating
Symbol
Moisture Sensitivity Level
SOIC−14
SOIC−8 EP
MSL
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions
TSLD
−
1
2
−
265 peak
°C
3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Thermal Characteristics, SOIC−8 Exposed Pad (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Pad (Note 5)
RθJA
YψJPad
65.1
8.7
Thermal Characteristics, SOIC−14 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Pin4 (Note 5)
RθJA
YψJP4
94.8
18.3
Unit
°C/W
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 6)
Rating
Symbol
Min
Max
Unit
Input Voltage
Vin
5.5
40
V
Junction Temperature
TJ
−40
150
°C
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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3
NCV4263−2C
ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN = 5 V, Cin = 100 nF, Cout = 22 mF, ESR = 1.5 W, WDI = 5 V pulses,
fWDI = 1 kHz. Min and Max values are valid for temperature range *40°C v TJ v 150°C unless otherwise noted and are guaranteed by
test design or statistical correlation. Typical values are referenced to TJ = 25°C. (Notes 7 and 8)
Test Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Vout
4.90
5.0
5.10
V
REGULATOR OUTPUT
Output Voltage Accuracy
Vin = 6 V to 40 V, Iout = 5 to 150 mA
Line Regulation
Iout = 150 mA, Vin = 6 V to 28 V
Regline
−25
3
25
mV
Load Regulation
Iout = 5 mA to 150 mA
Regload
−25
−
25
mV
Dropout Voltage (Note 9)
Iout = 150 mA
VDO
−
300
500
mV
IDIS
−
0.066
10
mA
−
−
−
0.275
3
11.3
1.3
18
23
ILIM
200
418
500
mA
PSRR
−
80
−
dB
−
0.8
2.0
1.74
3.5
−
DISABLE AND QUIESCENT CURRENTS
Disable Current
Quiescent Current, Iq = Iin − Iout
VEN = 0 V,TJ < 125°C
Iq
Iout = 0 mA
Iout = 150 mA
Iout = 150 mA, Vin = 4.5 V
mA
CURRENT LIMIT PROTECTION
Current Limit
Vout = 0.96 x Vout_nom
PSRR
Power Supply Ripple Rejection
(Note 10)
f = 100 Hz, 0.5 Vp−p
ENABLE
Vth(EN)
V
Enable Input Threshold Voltage
Logic High
Logic Low
Vout w 0.9 x Vout_nom
Vout v 0.1 V
Enable Input Current
VEN = 5 V
IEN
5
10
25
mA
Watchdog Input Low Time
CD = 100 nF, Vout > VRT, no WDI signal
tWL
1
2
3.5
ms
Watchdog Trigger Time
CD = 100 nF, Vout > VRT, no WDI signal
tWTT
16
20.8
27
ms
WATCHDOG INPUT
DELAY TIMING
Charge Current
VD = 1 V, no WDI signal
ID_charge
40
66.8
95
mA
Discharge Current
VD = 1 V, no WDI signal
ID_disch
4.40
6.54
9.40
mA
Saturation Voltage
Vout < VRT, no WDI signal
VD_sat
−
6
100
mV
VthH(D)
VthL(D)
1.45
0.2
1.70
0.34
2.05
0.55
VRT
90
93
96
% Vout
Vth(RADJ)
1.26
1.36
1.44
V
VRT_range
70
−
93
% Vout
Switching Threshold
Upper
Lower
V
RESET OUTPUT
Output Voltage Reset Threshold
(Note 11)
Vout decreasing, VRADJ = 0 V
Reset Adjust Threshold
(70% of Vout_nom) v Vout < (VRT)
Reset Adjustment Range (Note 12)
Reset Output Low Voltage
IRO = 1 mA
VROL
−
0.01
0.4
V
Reset Delay Time
CD = 100 nF
tRD
1.3
2.6
4.1
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.5 V.
10. Values based on design and/or characterization.
11. See APPLICATION INFORMATION section for Reset Threshold Adjustment
12. VRT_range limits are guaranteed by VRT and Vth(RADJ) parameters.
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NCV4263−2C
ELECTRICAL CHARACTERISTICS Vin = 13.5 V, VEN = 5 V, Cin = 100 nF, Cout = 22 mF, ESR = 1.5 W, WDI = 5 V pulses,
fWDI = 1 kHz. Min and Max values are valid for temperature range *40°C v TJ v 150°C unless otherwise noted and are guaranteed by
test design or statistical correlation. Typical values are referenced to TJ = 25°C. (Notes 7 and 8)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
CD = 100 nF
tRR
0.5
1.2
4
ms
Iout = 1 mA
TSD
150
177
195
°C
RESET OUTPUT
Reset Reaction Time
THERMAL SHUTDOWN
Thermal Shutdown Temperature
(Note 10)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.5 V.
10. Values based on design and/or characterization.
11. See APPLICATION INFORMATION section for Reset Threshold Adjustment
12. VRT_range limits are guaranteed by VRT and Vth(RADJ) parameters.
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NCV4263−2C
TYPICAL CHARACTERISTICS
16
Vin = 13.5 V
Iout = 0 mA
0.30
Iq, QUIESCENT CURRENT (mA)
Iq, QUIESCENT CURRENT (mA)
0.32
0.28
0.26
0.24
0.22
0.20
−40 −20
0
20
40
60
80
4
2
0
5
10
15
20
25
30
40
Figure 5. Quiescent Current vs. Input Voltage
Vin = 13.5 V
Iout = 5 mA
5.08
Vin = 13.5 V
TJ = 25°C
8
35
Figure 4. Quiescent Current vs. Temperature
Vout, OUTPUT VOLTAGE (V)
Iq, QUIESCENT CURRENT (mA)
6
Vin, INPUT VOLTAGE (V)
7
6
5
4
3
2
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
0
50
100
150
200
4.90
−40 −20
250
0
20
40
60
80
100 120 140 160
Iout, OUTPUT CURRENT (mA)
TJ, TEMPERATURE (°C)
Figure 6. Quiescent Current vs. Output
Current
Figure 7. Output Voltage Accuracy
6
600
VDO, DROPOUT VOLTAGE (mV)
Vout, OUTPUT VOLTAGE (V)
8
5.10
9
TJ = 25°C
Rout = 25 W
5
4
3
2
1
0
10
TJ, TEMPERATURE (°C)
10
1
0
12
0
100 120 140 160
TJ = 25°C
Rout = 25 W
14
0
1
2
3
4
5
TJ = 125°C
400
TJ = 25°C
300
TJ = −40°C
200
100
0
6
TJ = 150°C
500
0
50
100
150
200
250
Vin, INPUT VOLTAGE (V)
Iout, OUTPUT CURRENT (mA)
Figure 8. Output Voltage vs. Input Voltage
Figure 9. Dropout Voltage vs. Output Current
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NCV4263−2C
TYPICAL CHARACTERISTICS
500
400
300
200
100
0
−40 −20
0
20
40
60
80
100 120 140 160
450
TJ = 125°C
TJ = −40°C
TJ = 150°C
400
350
300
0
5
10
15
20
25
30
35
Figure 11. Output Current Limit vs. Input
Voltage
450
400
350
300
Vin = 13.5 V
Vout = 0.96 x Vout_nom
250
200
150
−40 −20
0
20
40
60
80
100 120 140 160
Unstable Region
10
1
Stable Region
Vin = 13.5 V
Cout = 22 mF
TJ = 25°C
0.1
0.01
0
50
100
150
200
Iout, OUTPUT CURRENT (mA)
Figure 12. Output Current Limit vs.
Temperature
Figure 13. Output Capacitor ESR Stability
Region vs. Output Current
100
90
80
70
Iout = 1 mA
60
50
40
Iout = 100 mA
100
1000
10,000
250
50
Vin = 13.5 V DC + 0.5 Vpp AC
Cout = 22 mF, TA = 25°C
110
40
100
TJ, TEMPERATURE (°C)
120
PSRR (dB)
TJ = 25°C
500
Figure 10. Dropout Voltage vs. Temperature
500
10
Vout = 0.96 x Vout_nom
550
Vin, INPUT VOLTAGE (V)
550
30
600
TJ, TEMPERATURE (°C)
ESR, OUTPUT CAPACITOR ESR (W)
ILIM, OUTPUT CURRENT LIMIT (mA)
ILIM, OUTPUT CURRENT LIMIT (mA)
Iout = 150 mA
IEN, ENABLE INPUT CURRENT (mA)
VDO, DROPOUT VOLTAGE (mV)
600
100,000
45
40
35
VEN = 13.5 V
30
Vin = 13.5 V
Iout = 0 mA
25
20
15
10
VEN = 5 V
5
VEN = 3.3 V
0
−40 −20
0
20
40
60
80
100 120 140 160
FREQUENCY (Hz)
TJ, TEMPERATURE (°C)
Figure 14. PSRR vs. Frequency
Figure 15. Enable Input Current vs.
Temperature
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NCV4263−2C
Vth(RADJ), RESET ADJUST THRESHOLD (V)
1.44
1.42
1.40
1.38
1.36
1.34
1.32
Vin = 13.5 V
Vout = 0.7 x Vout_nom
1.30
1.28
1.26
−40 −20
0
20
40
60
80
100 120 140 160
1.44
1.42
1.40
1.38
1.36
1.34
1.32
Vin = 13.5 V
TJ = 25°C
1.30
1.28
1.26
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vout, OUTPUT VOLTAGE (V)
Figure 17. Reset Adjust Threshold vs. Output
Voltage
1.8
Upper Threshold
1.6
1.4
1.2
1.0
Vin = 13.5 V
0.8
0.6
Lower Threshold
0.4
0.2
0
−40 −20
0
20
40
60
80
100 120 140 160
ID(charge), (disch), RESET DELAY
CHARGE / DISCHARGE CURRENT (mA)
TJ, TEMPERATURE (°C)
Figure 16. Reset Adjust Threshold vs.
Temperature
80
Charge Current
70
60
50
Vin = 13.5 V
VD = 1 V
40
30
20
Discharge Current
10
0
−40 −20
0
20
40
60
80
100 120 140 160
TJ, TEMPERATURE (°C)
TJ, TEMPERATURE (°C)
Figure 18. Delay Timing Switching Thresholds
vs. Temperature
Figure 19. Reset Delay Charge / Discharge
Current vs. Temperature
tWTT, WATCHDOG TRIGGER TIME (ms)
Vth(D), RESET DELAY THRESHOLDS (V)
Vth(RADJ), RESET ADJUST THRESHOLD (V)
TYPICAL CHARACTERISTICS
27
Vin = 13.5 V
Vout > VRT
CD = 100 nF
no WDI signal
26
25
24
23
22
21
20
19
18
17
16
−40 −20
0
20
40
60
80
100 120 140 160
TJ, TEMPERATURE (°C)
Figure 20. Watchdog Trigger Time vs.
Temperature
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NCV4263−2C
Vin
t
Vout
V RT
1V
t < t RR
VD
t
VthH(D)
VthL(D)
t
V RO
1V
V ROL
t RD
t RD
t RR
Input
Voltage Dip
Thermal
Shutdown
Under
Voltage
t
Output
Voltage Spike
Overload
Figure 21. Reset Operation Timing Diagram
VWDI
t
VD
VthH( D)
VthL( D)
t
V RO
VROL
tWTT
t WL
tWP
Figure 22. Watchdog Operation Timing Diagram
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9
t
NCV4263−2C
DEFINITIONS
General
Current Limit and Short Circuit Current Limit
All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.
Current Limit is value of output current by which output
voltage drops below 96% of its nominal value. It means that
the device is capable to supply minimum 200 mA without
sending Reset signal to microprocessor.
Short Circuit Current Limit is output current value
measured with output of the regulator shorted to ground.
Output Voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Line Transient Response
Typical output voltage overshoot and undershoot
response when the input voltage is excited with a given
slope.
Load Regulation
The change in output voltage for a change in output
current measured for specific input voltage over operating
ambient temperature range.
Load Transient Response
Typical output voltage overshoot and undershoot
response when the output current is excited with a given
slope between low−load and high−load conditions.
Dropout Voltage
The input to output differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. It is measured when the output
drops 100 mV below its nominal value. The junction
temperature, load current, and minimum input supply
requirements affect the dropout level.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 177°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Quiescent and Disable Currents
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
reduces its internal bias and shuts off the output, this term is
called the disable current (IDIS).
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
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NCV4263−2C
APPLICATIONS INFORMATION
range of Output Voltage 70% ≤ Vout < VRT by external
resistor output voltage divider, see schematic on Figure 23
and specification of Reset Output.
The NCV4263−2C regulator is self−protected with
internal thermal shutdown and internal current limit. Typical
characteristics are shown in Figures 4 to 22.
Input Decoupling (Cin)
A ceramic or tantalum 0.1 mF capacitor is recommended
and should be connected close to the NCV4263−2C
package. Higher capacitance and lower ESR will improve
the overall line and load transient response. If extremely fast
input voltage transients are expected then appropriate input
filter is recommended to use in order to decrease rising
and/or falling edges below 50 V/ms for proper operation.
The filter can be composed of several capacitors in parallel.
Cin
100 nF
OFF ON
where:
CD
tRD_des
tRD
RESET
RO
I/O
D
CD
Desired Reset Threshold is given by Equation 2.
V RT_des +
ǒ
Ǔ
R RADJ1 ) R RADJ2
R RADJ2
V th(RADJ) (eq. 2)
where:
VRT_des
is desired Reset Threshold
RRADJ1, RRADJ2 are resistance of resistor divider
Vth(RADJ)
is Reset Adjust Threshold specified in
datasheet
Use RRADJ2 ≤ 50 kW to avoid significant Reset Threshold
error due to RADJ bias current.
The Delay Timing pin is current source. Current from
Delay Timing pin charges connected capacitor. The value of
this capacitor determines the Reset Delay Time by
Equation 1 and Watchdog Trigger Time by Equation 4.
100 nF
EN
Microprocessor
Figure 23. Application Schematic with Adjustable
Reset Threshold
Delay Timing
Ǔ
RRADJ2
RRO
5.6 kW
100 nF
The Enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet.
t RD
22 mF
NCV4263−2C
GND
Enable Operation
t RD_des
RRADJ1
WDI
The NCV4263−2C is a stable component and requires a
minimum Equivalent Series Resistance (ESR) for the output
capacitor. Stability region of ESR versus Output Current is
shown in Figure 13. The minimum output decoupling value
is 22 mF and can be augmented to fulfill stringent load
transient requirements. Larger values improve noise
rejection and load transient response.
ǒ
VDD
Cout
RADJ
Output Decoupling (Cout)
CD +
Vout
Vin
Watchdog Operation
Watchdog Input monitors a signal from microprocessor.
This input is positive edge sensitive. The timing diagram of
watchdog function is shown in Figure 22. When watchdog
signal is not received during Watchdog Trigger Time, Reset
Output goes low for a Watchdog Input Low Time and is
periodically generated with period given by Equation 3.
Capacitance of Delay capacitor for setting the desired
Watchdog Trigger Time is given by Equation 4.
(eq. 1)
is capacitance of Delay capacitor
is desired Reset Delay Time
is Reset Delay Time specified in
datasheet
t WP + t WL ) t WTT
Reset Operation
CD +
A reset signal is provided on the Reset Output pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 21. This is in the form of a logic signal on
Reset Output. Output voltage conditions below the Reset
Threshold causes Reset Output to go low. The Reset Output
integrity is maintained down to Vout = 1.0 V. The Reset
Output circuitry is open collector output with internal 30 kW
pull−up resistor. Leave open this output if the Reset function
is not needed else an external pull−up resistor (5.6 kW)
connect to the output (Vout).
Reset Threshold is default set to 93% of nominal Output
Voltage (VRADJ = 0 V). Reset Threshold can be varied in
where:
CD
tWTT_des
tWTT
tWL
tWP
ǒ
t WTT_des
t WTT
Ǔ
100 nF
(eq. 3)
(eq. 4)
is capacitance of Delay capacitor
is desired Watchdog Trigger Time
is Watchdog Trigger Time specified in
datasheet
is Watchdog Input Low Time
is Watchdog Input Period
Thermal Considerations
As power in the NCV4263−2C increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
www.onsemi.com
11
NCV4263−2C
160
P D(MAX) +
ƪTJ(MAX) * TAƫ
RqJA, THERMAL RESISTANCE (°C/W)
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV4263−2C has good thermal conductivity through
the PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV4263−2C can handle is given by:
150
140
130
110
100
(eq. 5)
R qJA
Since TJ is not recommended to exceed 150°C, then the
NCV4263−2C soldered on 645 mm2, 1 oz copper area, FR4
can dissipate up to 1.3 W in SOIC−14 package and 1.9 W in
SOIC−8 EP package, when the ambient temperature (TA) is
25°C. See Figures 24 and 25 for RqJA versus PCB area. The
power dissipated by the NCV4263−2C can be calculated
from the following equations:
V in(MAX) [
I outǓ
I out ) I q
SOIC−14 − 2 OZ Cu
80
70
60
50
0
100
200
300
400
500
600
700
(mm2)
Figure 24. Thermal Resistance vs. PCB Copper Area
for SOIC−14
160
(eq. 6)
150
or
P D(MAX) ) ǒV out
90
COPPER HEAT SPREADER AREA
RqJA, THERMAL RESISTANCE (°C/W)
P D [ V inǒI q@I outǓ ) I outǒV in * V outǓ
SOIC−14 − 1 OZ Cu
120
140
130
(eq. 7)
120
110
SOIC−8 EP − 1 OZ Cu
100
Hints
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV4263−2C
and make traces as short as possible.
90
80
70
60
50
SOIC−8 EP − 2 OZ Cu
0
100
200
300
400
500
600
700
COPPER HEAT SPREADER AREA (mm2)
Figure 25. Thermal Resistance vs. PCB Copper Area
for SOIC−8 EP
ORDERING INFORMATION
Output Voltage
Marking
Package
Shipping†
NCV4263−2CD250R2G
5.0 V
NCV4263−2C50G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
NCV4263−2CPD50R2G
5.0 V
V632C5
SOIC−8 EP
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
14X
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE D
8
1
SCALE 1:1
DATE 02 APR 2019
GENERIC
MARKING DIAGRAM*
8
XXXXX
AYWWG
G
1
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
98AON14029D
SOIC−8 EP
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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