UPD17P218

DATA SHEET MOS INTEGRATED CIRCUIT µPD17P218 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROLLER DESCRIPTION The µPD17P218 is a model of the µPD17218 with a one-time PROM instead of an internal mask ROM. Since the user can write programs to the µPD17P218, it is ideal for experimental production or small-scale production of the µPD17215, 17216, 17217 or 17218 systems. When reading this document, also read the documents related to the µPD17215, 17216, 17217 and 17218. Detailed functions are described in the following user’s manual. Read this manual when designing your system. 5 µPD172×× Series User’s Manual: IEU-1317 FEATURES • Pin compatible with µPD17215, 17216, 17217 and 17218 (except PROM programming function) • Carrier generator circuit for infrared remote controller (REM output) • 17K architecture: General-purpose register method • Program memory (one-time PROM): 16K bytes (8192 × 16) • Data memory (RAM): 223 × 4 bits • Pull-up resistor can be connected to RESET pin Note. • Low-voltage detection circuit (WDOUT output) Note • Operating voltage range: 2.0 to 5.5 V (fx = 4 MHz: normal mode, 8 µs) 2.2 to 5.5 V (fx = 4 MHz: high-speed mode, 4 µs) 3.5 to 5.5 V (fx = 8 MHz: high-speed mode, 2 µs) Note: Can be selected by mask option with the mask model. APPLICATIONS Preset remote controllers, toys, and portable systems ORDERING INFORMATION Package 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) Quality Grade Standard Standard Part Number µPD17P218GT µPD17P218CT Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. The mark 5 shows major revised points. Document No. IC - 3252 (O. D. No. IC - 8797) Date Published September 1994 P Printed in Japan © 1994 µPD17P218 PIN CONFIGURATION (TOP VIEW) (1) Normal operation mode P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 REM V DD X OUT X IN GND RESET WDOUT 1 2 3 4 5 28 27 26 25 24 P0D 1 P0D 0 P0C 3 P0C 2 P0C 1 P0C 0 P0B 3 P0B 2 P0B 1 P0B 0 P0A 3 P0A 2 P0A 1 P0A 0 µ PD17P218GT µ PD17P218CT 6 7 8 9 10 11 12 13 14 23 22 21 20 19 18 17 16 15 GND INT P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 REM RESET VDD WDOUT XIN, XOUT : Ground : External interrupt request signal input : Port 0A (CMOS input) : Port 0B (CMOS input) : Port 0C (N-ch open-drain output) : Port 0D (N-ch open-drain output) : Port 0E (CMOS push-pull output) : Remote controller transmission output (CMOS push-pull output) : Reset input : Positive power supply : Hang-up detection/low-voltage detection output (N-ch open-drain output) : Oscillation connection 2 µPD17P218 (2) PROM programming mode D2 D3 V PP 1 2 3 4 5 28 27 26 25 24 D1 D0 D7 D6 D5 D4 MD 3 MD 2 MD 1 MD 0 (L) 6 7 (Open) V DD (Open) CLK GND (L) (Open) 8 9 10 11 12 13 14 µ PD17P218GT µ PD17P218CT 23 22 21 20 19 18 17 (L) 16 15 Note: Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470 W). Open : Do not connect anything to these pins. CLK D0-D7 GND VDD VPP : PROM clock input : PROM data I/O : Ground : Positive power supply : PROM writing power supply MD0-MD3 : PROM mode selection 3 µPD17P218 BLOCK DIAGRAM P0A 0 P0A 1 P0A 2 P0A 3 P0A RF RAM 223 × 4 bits Remote Control Divider REM P0B 0 /MD 0 P0B 1 /MD 1 P0B 2 /MD 2 P0B 3 /MD 3 8-bit Timer/ Counter P0B SYSTEM REG. Interrupt Controller ALU INT/V PP P0C 0 /D 4 P0C 1 /D 5 P0C 2 /D 6 P0C 3 /D 7 P0C P0D 0 /D 0 P0D 1 /D 1 P0D 2 /D 2 P0D 3 /D 3 One Time PROM 8192 × 16 bits P0D Instruction Decoder RESET WDOUT Program Counter P0E 0 P0E 1 P0E 2 P0E 3 P0E Stack 5 × 13 bits Power Supply Circuit CPU Clock V DD GND Basic Interval/ Watchdog Timer XIN /CLK OSC XOUT 4 µPD17P218 CONTENTS 1. DIFFERENCES BETWEEN µPD17P218 AND µPD17215/17216/17217/17218 .................................. 6 2. PIN FUNCTIONS ................................................................................................................................. 2.1 2.2 2.3 2.4 2.5 IN NORMAL MODE ................................................................................................................................ IN PROM PROGRAMMING MODE ........................................................................................................ PIN I/O CIRCUITS ................................................................................................................................... PROCESSING OF UNUSED PINS .......................................................................................................... NOTES ON USING INT AND RESET PINS ........................................................................................... 7 7 8 8 11 11 5 5 3. WRITING/VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................................. 12 3.1 3.2 3.3 OPERATION MODE FOR WRITING/VERIFICATION OF PROGRAM MEMORY .................................. PROGRAM MEMORY WRITE PROCEDURE ......................................................................................... PROGRAM MEMORY READ PROCEDURE ........................................................................................... 12 13 14 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ........................................................................... 15 5. PACKAGE DRAWINGS .................................................................................................................... 23 6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 25 5 APPENDIX A. FUNCTION OF µPD17215 SUB-SERIES PRODUCTS ................................................. 26 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 27 5 µPD17P218 5 1. DIFFERENCES BETWEEN µPD17P218 AND µPD17215/17216/17217/17218 The µPD17P218 is a model of the µPD17218 provided with a one-time PROM as the program memory, to which the user can write data, instead of an internal mask ROM. Table 1-1 shows the differences among the µPD17P218, µPD17215, 17216, 17217, and 17218. These five products have different memory capacities and mask options but the same CPU function and internal hardware. Therefore, the µPD17P218 can be used to evaluate the program of a system using the µPD17215, 17216, 17217, or 17218. Note that part of the electrical specifications of the µPD17P218 such as supply current and lowvoltage detection voltage are different from those of the µPD17215, 17216, 17217, and 17218. For the detail of the CPU functions and internal hardware, refer to the Data Sheet of the µPD17215, 17216, 17217, and 17218. Table 1-1 Differences between µPD17P218 and 17215/17216/17217/17218 Product Name Item µPD17P218 One-time PROM µPD17215 µPD17216 µPD17217 µPD17218 Mask ROM 8 K bytes (4096 × 16) 12 K bytes (6144 × 16) 16 K bytes (8192 × 16) (0000H-0FFFH) (0000H-17FFH) (0000H-1FFFH) 223 x 4 bits Any (mask option) Any (mask option) Not provided 2 µs (8 MHz ceramic oscillator: in high-speed mode) 4 µs (4 MHz ceramic oscillator: in high-speed mode) 16 µs (1 MHz ceramic oscillator: in high-speed mode) Retain output level immediately before standby mode 2.2 to 5.5 V (at 4 MHz, in high-speed mode) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) Program Memory 16 K bytes (8192 × 16) 4 K bytes (2048 × 16) (0000H-1FFFH) (0000H-07FFH) 223 × 4 bits Provided Provided Provided Data Memory Pull-Up Resistor of RESET Pin Low-Voltage Detector Circuit Note 111 x 4 bits VPP Pin, Operation Mode Select Pin Instruction Execution Time Operation When P0C, P0D Are Standby Operating Voltage Range Package Note: Although the circuit configuration of the low-voltage detector circuit is identical, its electrical specifications differ depending on the product. 6 µPD17P218 2. 2.1 PIN FUNCTIONS IN NORMAL MODE Symbol P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. This port retains output level immediately before standby mode is set when standby mode is set, and outputs low level on reset. 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. This port retains output level immediately before standby mode is set when standby mode is set, and outputs low level on reset. 4-bit I/O port which can be set in input or output mode in bit units. In output mode, this port serves as high-current CMOS output port. In input mode, it serves as CMOS input port to which pull-up resistor can be connected by program in bit units. On reset, this port is set as input port. Infrared remote controller transmission output pin. Outputs low level on reset. System reset input pin. By inputting low level to this pin, CPU can be reset. While low level is input to this pin, oscillation circuit stops oscillating. RESET pin of µPD17P218 is provided with pull-up resistor. Positive power supply pin Ground External interrupt request input Output for detection of hang-up or voltage drop. Outputs low level when watchdog timer overflows, when stack overflows/underflows, or when low voltage is detected. Connect this pin to RESET pin. Connect ceramic oscillator for system clock oscillation across these pins. 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. This port can release standby mode when at least one of pins goes low. Function 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. This port can release standby mode when at least one of pins goes low. Output Format On Reset Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 — Input — Input N-ch open-drain Low-level output N-ch open-drain Low-level output 4 5 6 7 P0E0 P0E1 P0E2 P0E3 CMOS push-pull Input 8 REM CMOS push-pull Low-level output 13 RESET — Input 9 12 3 VDD GND INT — — — — — Input High-impedance or low-level output (Oscillation stops) 14 WDOUT N-ch open-drain 11 10 XIN XOUT — 7 µPD17P218 2.2 IN PROM PROGRAMMING MODE Pin No. Symbol Function Power supply for PROM programming. Apply 12.5 V to this pin as the program voltage when writing/verifying program memory. Positive power supply. Apply 6 V to this pin when writing/ verifying program memory. Inputs clock for PROM programming. Ground Input pins used to select operation mode when PROM is programmed. Output Format On Reset 3 VPP — — 9 VDD — — 11 12 19 | 22 23 | 26 27 28 1 2 CLK GND MD0 | MD3 D4 | D7 D0 D1 D2 D3 — — — — — Input Input/output 8-bit data for PROM programming. CMOS push-pull Input Remarks: Pins other than above are not used in the PROM programming mode. For the processing of the unused pins, refer to PIN CONFIGURATION (2) PROM programming mode. 2.3 PIN I/O CIRCUITS This section shows the I/O circuits of the µPD17P218 pins in simplified schematic diagrams. (1) P0A0-P0A3, P0B0/MD0-P0B3/MD3 V DD Input buffer 8 µPD17P218 (2) P0C0/D4-P0C3/D7, P0D0/D0-P0D3/D3 Data Output latch N-ch Input buffer (3) P0E0-P0E3 V DD Data Pull-up resistor P-ch V DD Output latch Data P-ch Output disable N-ch Multiplexer Input buffer 9 µPD17P218 (4) RESET V DD Pull-up resistor Note Input buffer Note: Can be selected with mask option when mask products such as µPD17215, 17216, 17217, and 17218 are used. Remarks: Schmitt trigeer input with hysteresis characteristics (5) INT (Schmitt trigger input) Input buffer Remarks: Schmitt trigeer input with hysteresis characteristics 10 µPD17P218 2.4 PROCESSING OF UNUSED PINS Process the unused pins as follows: 5 Table 2-1 Processing of Unused Pins Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 REM INT WDOUT Recommended Connection Connect to VDD Connect to VDD Connect to GND Connect to GND Input : Connect to VDD or GND Output : Open Open Connect to GND Connect to GND 2.5 NOTES ON USING INT AND RESET PINS In addition to the functions shown in 2 PIN FUNCTIONS, the INT and RESET pins also have a function to set a 5 test mode (for IC testing) in which the internal operations of the µPD17P218 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during normal operation, the µPD17P218 may be set in the test mode and malfunction if a noise exceeding VDD is applied. For example, if the wiring length of the INT or RESET pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. • Connect diode with low VF between VDD and INT/RESET pin • Connect capacitor between VDD and INT/RESET pin V DD V DD Diode with low V F INT, RESET V DD V DD INT, RESET Moreover, if the test mode is set by the INT pin, low level is output from the WDOUT pin. In this case, connect the WDOUT pin to the RESET pin. 11 µPD17P218 3. WRITING/VERIFYING ONE-TIME PROM (PROGRAM MEMORY) The program memory of the µPD17P218 is a one-time PROM of 8192 x 16 bits. To write data to or verify this onetime PROM, the pins shown in the following table are used. No address input pin is used, as the address is updated by the clock input from the CLK pin. Table 3-1 Pins Used to Write/Verify Program Memory Pin Name VPP Function Applies voltage when program memory is written/verified. Apply +12.5 V to this pin. Positive power supply. Apply +6 V to write/verify program memory. Input clock to update address when program memory is written/verified. Program memory address is updated when four pulses are input to this pin. Select operation mode when program memory is written/verified. Input/output 8-bit data when program memory is written/verified. VDD CLK MD0-MD3 D0-D7 3.1 OPERATION MODE FOR WRITING/VERIFICATION OF PROGRAM MEMORY If +6 V is applied to the VDD and +12.5 V to the VPP pin after µPD17P218 has been placed in the reset status for a fixed time (VDD = 5V, RESET = 0V), µPD17P218 enters program memory write/verify mode. The MD0 to MD3 pins are used to set the operating modes listed in the following table. Leave the pins not used for program memory writing/verification open or connect to GND through pull-down resistors (470 Ω) (Refer to PIN CONFIGRATION (2) PROM programming mode). Table 3-2 Operating Mode Specification Operating Mode Specification Operating Mode VPP VDD MD0 H L +12.5 V +6 V L H L × H H H H Verify mode Program inhibit mode MD1 L H MD2 H H MD3 L H Program memory address 0 clear mode Write mode Remarks: ×: don‘t care (L or H) 12 µPD17P218 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows. High-speed program memory write is possible. (1) (2) (3) (4) (5) (6) (7) (8) (9) Ground the unused pins through pull-down resistors. The CLK pin must be low. Supply 5 V to the VDD pin. The VPP pin must be low. After waiting for 10 microseconds, supply 5 V to the VPP pin. Operate the MD0 to MD3 pins to set program memory address 0 clear mode. Supply 6 V to the VDD pin and 12.5 V to the VPP pin. Set program inhibit mode. Write data in 1-millisecond write mode. Set program inhibit mode. Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written ( ×) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below. X-time repetition Reset Write Verify Additional data write Address increment VPP VPP VDD GND VDD+1 VDD VDD GND CLK Data output D 0 -D 7 Data input Data input MD 0 MD 1 MD 2 MD 3 Remarks: Broken line indicates high impedance. 13 µPD17P218 3.3 (1) (2) (3) (4) (5) (6) (7) (8) (9) PROGRAM MEMORY READ PROCEDURE Ground the unused pins through pull-down resistors. The CLK pin must be low. Supply 5 V to the VDD pin. The VPP pin must be low. After waiting for 10 microseconds, supply 5 V to the VPP pin. Operate the MD0 to MD3 pins to set program memory address 0 clear mode. Supply 6 V to the VDD pin and 12.5 V to the VPP pin. Set program inhibit mode. Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the Set program inhibit mode. Set program memory address 0 clear mode. CLK pin four times. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below. VPP VPP VDD GND VDD+1 VDD VDD GND 1 cycle CLK D 0 - D7 Hi-Z Data output Data output Hi-Z MD 0 MD 1 L MD 2 MD 3 14 µPD17P218 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) Item Supply Voltage Input Voltage Output Voltage Symbol VDD VI VO Peak value REM pin Effective value High-Level Output Current Note Peak value IOH 1 pin (P0E pin) Effective value Peak value Total of P0E pins Effective value Peak value 1 pin Effective value Low-Level Output Current Note Peak value IOL Total of P0E pins Effective value Total of P0C, P0D, WDOUT pins Operating Temperature Storage Temperature Power dissipation Topt Tstg Pd Ta = 8 5 °C Peak value Effective value 20.0 22.5 15.0 –40 to +85 –60 to +150 180 mA mA mA °C °C mW 5.0 30.0 mA mA –15.0 7.5 mA mA –5.0 –22.5 mA mA –24.0 –7.5 mA mA Conditions Ratings –0.3 to +7.0 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –36.0 Unit V V V mA 5 5 Note: Effective value = Peak value × √Duty. 5 Caution: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality 5 of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. RECOMMENDED OPERATING RANGE (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item Symbol VDD1 Supply Voltage VDD2 fx = 4 MHz VDD3 VDD4 Oscillation Frequency fX fx = 8 MHz fx = 1 MHz Conditions Note High-speed mode (16 µs) Normal mode (8 µs) High-speed mode (4 µs) High-speed mode (2 µs) MIN. 2.0 2.2 3.5 1.0 TYP. 3.0 3.0 5.0 4.0 MAX. 5.5 V 5.5 5.5 8.0 MHz Unit 5 Note: Figures in parentheses indicate instruction execution time. 15 µPD17P218 SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 5.5 V) Oscillator Recommended Constants Item Oscillation frequency (fx) Note 1 Oscillation stabilization timeNote 2 After VDD has reached MIN value of oscillation voltage range Conditions MIN. TYP. MAX. Unit X IN Ceramic Oscillator X OUT 1.0 4.0 8.0 MHz 4 ms X IN X OUT Oscillation frequency (fx) Note 1 1.0 4.0 8.0 MHz 5 Crystal Oscillator Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 10 30 ms ms Note 1: The oscillation frequency indicates only the characteristics of the oscillation circuit. 2: The oscillation stabilization time is the time required for oscillation to stabilize after VDD has been applied or the STOP mode has been released. Caution: Wire the shaded portion in the above figures as follows to prevent adverse influence of wiring capacitance when the system clock oscillation circuit is used: • Keep the wiring length as short as possible. through which a high alternating current flows. • Always keep the ground of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract a signal from the oscillation circuit. • Do not cross the wiring with the other signal lines. Do not place the wiring in the vicinity of lines 16 µPD17P218 DC CHARACTERISTICS (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item Symbol VIH1 VIH2 High-Level Input Voltage VIH3 VIH4 VIH5 VIL1 VIL2 Low-Level Input Voltage VIL3 VIL4 High-Level Output Voltage VOH VOL1 Low-Level Output Voltage VOL2 High-Level Input Current Low-Level Input Current High-Level Input Leakage Current IIH IIL ILIH P0E XIN P0E, REM P0C, P0D, REM, WDOUT P0E XIN XIN INT, RESET, P0A, P0B, P0E INT P0E IOH = –0.5 mA IOL = 0.5 mA 0 0 VDD–0.3 0 0.35VDD 0.2VDD VDD 0.3 V V V V RESET, INT pin P0A, P0B P0E P0E XIN RESET, INT pins P0A, P0B 2.0 V ≤ VDD < 3.0 V 3.0 V ≤ VDD ≤ 5.5 V Conditions MIN. 0.8VDD 0.7VDD VDD–0.3 VDD–0.5 0.8VDD 0 0 TYP. MAX. VDD VDD VDD VDD VDD 0.2VDD 0.3VDD Unit V V V V V V V IOL = 1.5 mA VIH = VDD VIL = 0 V VIH = VDD 0 0.3 20 –20 3.0 V µA µA µA µA µA ILIL1 Low-Level Input Leakage Current ILIL2 VIL = 0 V VIL = 0 V w/o pull-up resistor VOH = 1.0 V, VDD = 3 V VOH = VDD –6.0 –13.0 –3.0 –3.0 High-Level Output Current High-Level Output Leakage Current IOH ILOH REM P0C, P0D, P0E, WDOUT WDOUT P0E –24.0 3.0 mA µA µA µA kΩ kΩ kΩ kΩ V ILOL1 Low-Level Output Leakage Current ILOL2 VOL = 0 V VOL = 0 V w/o pull-up resistor VDD = 3 V ± 10 % 25 25 100 100 0.5 50 50 200 200 1.4 –3.0 –3.0 100 100 400 400 2.0 RU1 Internal Pull-Up Resistor RU2 RESET, P0E VDD = 5 V ± 10 % VDD = 3 V ± 10 % P0A, P0B VDD = 5 V ± 10 % Low-Voltage Detector Voltage VDT WDOUT = Low level, VDT = VDD 5 17 µPD17P218 5 DC CHARACTERISTICS (VDD = 2.0 to 5.5 V, Ta = –40 to +85 °C) Item Symbol IDD1 fX = 8 MHz Conditions Operating mode (High-speed mode) HALT mode Operating mode (High-speed mode) VDD = 5 V ± 10 % VDD = 5 V ± 10 % VDD = 5 V ± 10 % VDD = 3 V ± 10 % VDD = 5 V ± 10 % Operating mode (Normal mode) VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V VDD = 5 V ± 10 % IDD4 fX = 4 MHz HALT mode VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V Operating mode (High-speed mode) VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V VDD = 3 V ± 10 % IDD6 fX = 1 MHz HALT mode VDD = 2.0 to 2.2 V VDD = 5 V ± 10 % IDD7 STOP mode (Ta = –40 to +85 ˚C) VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V VDD = 5 V ± 10 % IDD8 STOP mode (Ta = –20 to +70 ˚C) VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V VDD = 5 V ± 10 % IDD9 STOP mode (Ta = 25 °C) VDD = 3 V ± 10 % VDD = 2.0 to 2.2 V Data Retention Voltage VDDR RESET = Low level or in STOP mode 1.3 0.2 1 1 1 1 1 1 1 1 1 0.6 30 20 16 20 10 8 5 5 5 5.5 mA MIN. TYP. 3.8 MAX. 7.6 Unit mA IDD2 fX = 8 MHz 2.6 2.3 1.2 2.0 1.0 0.55 1.8 1.0 0.5 0.7 0.3 0.6 5.2 4.6 2.5 4.0 2.0 1.1 3.6 2.0 1.0 2.1 0.9 1.8 mA mA mA mA mA mA mA mA mA mA mA mA IDD3 fX = 4 MHz Supply Current IDD5 fX = 1 MHz µA µA µA µA µA µA µA µA µA V 18 µPD17P218 AC CHARACTERISTICS (Ta = –40 to +85 °C) Item CPU Clock Cycle Time Note (Instruction Execution Time) Symbol tCY1 tCY2 tCY3 tIOH1 INT High-Level Width tIOH2 tIOL1 INT Low-Level Width tIOL2 tRSL1 RESET Low-Level Width tRSL2 VDD = 2.0 to 5.5 V 50.0 VDD = 2.0 to 5.5 V VDD = 4.5 to 5.5 V 50.0 10.0 VDD = 2.0 to 5.5 V VDD = 4.5 to 5.5 V 50.0 10.0 Conditions VDD = 3.5 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.0 to 5.5 V VDD = 4.5 to 5.5 V MIN. 1.99 3.98 7.96 10.0 TYP. MAX. 32.2 32.2 32.2 Unit µs µs µs µs µs µs µs µs µs Note: CPU clock cycle time (instruction execution time) is determined depending on the connected oscillation frequency and SYSCK (RF: address 02H) in the register file. The following figure shows CPU clock cycle time tCY characteristics versus supply voltage VDD. tCY vs VDD 40 32 5 CPU clock cycle time tCY [µs] 10 9 8 7 6 5 4 3 2 2.2 V 0 1 2 3 4 5 6 Supply voltage VDD [V] 19 µPD17P218 DC PROGRAMMING CHARACTERISTICS (Ta = 25°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V) Item High-Level Input Voltage Symbol VIH1 VIH2 Low-Level Input Voltage Input Leakage Current High-Level Output Voltage Low-Level Output Voltage VDD Supply Current VPP Supply Current VIL1 VIL2 ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = –1 mA IOL = 1.6 mA VDD –1.0 0.4 30 30 Conditions MIN. 0.7 VDD VDD –0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V µA V V mA mA Caution 1: VPP must not exceed +13.5 V, including the overshoot. 2: Apply VDD before VPP and disconnect it after VPP. 20 µPD17P218 AC PROGRAMMING CHARACTERISTICS (Ta = 25°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V) Item Address Setup Time Note 2 Symbol Note 1 (vs.MD0↓) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH,tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR – – – – – – – tACC tOH – – Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit µs µs µs µs µs 130 ns MD1 Setup Time (vs. MD0↓) Data Setup Time (vs. MD0↓) Address Hold Time Note 2 (vs.MD0↑) Data Hold Time (vs. MD0↑) MD0 ↑→ Data Output Float Delay Time VPP Setup Time (vs. MD3↑) VDD Setup Time (vs. MD3↑) Initial Program Pulse Width Additional Program Pulse Width MD0 Setup Time (vs. MD1↑) MD0 ↓→ Data Output Delay Time MD1 Hold Time (vs. MD0↑) MD1 Recovery Time (vs. MD0↓) Program Counter Reset Time CLK Input High-/Low- Level Width CLK Input Frequency Initial Mode Set Time MD3 Setup Time (vs. MD1↑) MD3 Hold Time (vs. MD1↓) MD3 Setup Time (vs. MD0↓) Address Note 2 → Data Output Delay Time Address Note 2 → Data Output Hold Time MD3 Hold Time (vs. MD0↑) MD3 ↓→ Data Output Float Delay Time Reset Setup Time µs µs 1.0 1.05 21.0 ms ms µs 1 MD0 = MD1 = VIL tM1H + tM1R 50 µs 2 2 10 0.125 µs µs µs µs µs 4.19 2 2 2 When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory When data is read from program memory MHz µs µs µs µs µs 130 ns 2 2 0 2 2 10 µs µs µs Note 1: These symbols are the corresponding µPD27C256A symbols. 2: The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin. 21 µPD17P218 PROGRAM MEMORY WRITE TIMING tRES VPP VDD GND VDD+1 VDD GND CLK D 0 -D 7 tI MD 0 tPW MD 1 tPCR MD 2 tM3S MD 3 tM3H tM1S tM1H tM1R tM0S tOPW Data input tDS tOH Data output tVPS VPP tVDS tXH VDD Data input tDF tDS tDH tAH tXL tAS Data input tDV Remarks: Broken line indicates high impedance. PROGRAM MEMORY READ TIMING tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK tXL D 0 -D 7 tI MD 0 Hi-Z tDV tHAD Data output tDAD Data output tM3HR Hi-Z tDFR tVDS VDD tXH MD 1 L tPCR MD 2 tM3SR MD 3 22 µPD17P218 5. PACKAGE DRAWINGS 28 PIN PLASTIC SOP (375 mil) 28 15 detail of lead end 1 A 14 G 3° +7° –3° H I J K L F E C D MM B N P28GM-50-375B-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 18.07 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 –0.05 0.1 ± 0.1 2.9 MAX. 2.50 10.3 ± 0.3 7.2 1.6 0.15 +0.10 –0.05 0.8 ± 0.2 0.12 0.15 INCHES 0.712 MAX. 0.031 MAX. 0.050 (T.P.) 0.016+0.004 –0.003 0.004 ± 0.004 0.115 MAX. 0.098 0.406+0.012 –0.013 0.283 0.063 0.006+0.004 –0.002 0.031 –0.008 0.005 0.006 +0.009 23 µPD17P218 28 PIN PLASTIC SHRINK DIP (400 mil) 28 15 1 A 14 K I L J G H F D N M C B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 28.46 MAX. 2.67 MAX. 1.778 (T.P.) 0.50 ± 0.10 0.85 MIN. 3.2 ± 0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 –0.05 0.17 0 ˜15 ° INCHES 1.121 MAX. 0.106 MAX. 0.070 (T.P.) 0.020 +0.004 –0.005 0.033 MIN. 0.126 ± 0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.400 (T.P.) 0.339 0.010 +0.004 –0.003 0.007 0 ˜15 ° S28C-70-400B-1 24 µPD17P218 6. RECOMMENDED SOLDERING CONDITIONS For the µPD17P218, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document “Semiconductor device mounting technology manual” (IEI-1207). For other soldering methods, please consult with NEC sales personnel. 5 Table 6-1 Soldering Conditions of Surface-Mount Type µPD17P218GT: 28-pin plastic SOP (375 mil) Soldering Method Soldering Conditions Package peak temperature: 230 ˚C, Time: 30 seconds max. (more than 210 ˚C), Number of soldering operations: 1, Maximum number of days: 3 days Note (Afterwards, 20 hours prebaking at 125 ˚C is required) Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side) Recommended Conditions Reference Code Infrared Reflow IR30-203-1 Pin Partial Heating — Note: This means the number of days after unpacking the dry pack. Storage conditions are 25 ˚C and 65 % RH max. Caution: Do not use one soldering method in combination with another. (However, pin partial heating can be performed with other soldering methods.) Table 6-2 Soldering Conditions of Through-Hole Type µPD17P218CT: 28-pin plastic shrink DIP (400 mil) Soldering Method Wave Soldering (Only for lead part) Pin Partial Heating Soldering Conditions Solder bath temperature: 260 ˚C max., Time: 10 seconds max. Pin temperature: 300 ˚C max., Time: 10 seconds max. Caution: The wave soldering must be performed at the lead part only. Note that the solder must not be directly contacted to the package body. 25 µPD17P218 5 APPENDIX A. Item ROM Capacity FUNCTION OF µPD17215 SUB-SERIES PRODUCTS Product µPD17215 µPD17216 µPD17217 µPD17218 µPD17P218 4K bytes (2048 x 16) 8K bytes (4096 x 16) 12K bytes (6144 x 16) 16K bytes (8192 x 16) 16K bytes (8192 x 16) (mask ROM) (mask ROM) (mask ROM) (mask ROM) (one-time PROM) 111 x 4 bits 223 x 4 bits Provided (without LED output) 20 1 (rising-edge, falling-edge detection)  2 channels  8-bit modulo timer : 1 channel  Basic interval timer: 1 channel RAM Capacity Infrared Remote Controller Carrier Generator Circuit (REM) Number of I/O Ports External Interrupt (INT) Timer Watchdog Timer Low-Voltage Detector Circuit Note Serial Interface Stack Instruction Execution Time Operation of P0C and P0D in Standby Mode Operating Voltage Range Standby Function Package Provided (WDOUT output) Provided (WDOUT output) None 5 levels (3 levels of multiplexed interrupts) 2 µs (8-MHz ceramic oscillator: high-speed mode) 4 µs (4-MHz ceramic oscillator: high-speed mode) 16 µs (1-MHz ceramic oscillator: high-speed mode) Retain output level immediately before standby mode 2.2 to 5.5 V (4 MHz, high-speed mode) STOP mode, HALT mode 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) Note : Although the circuit configuration of the low-voltage detection circuit is identical, its electrical specifications differ depending on the product. 26 µPD17P218 APPENDIX B. DEVELOPMENT TOOLS 5 To develop the programs for the µPD17P218, the following development tools are available: Hardware Name In-Circuit Emulator Remarks IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators used in common with the 17K series microcomputer. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM as the host machine with RS-232C. EMU-17K is inserted into the expansion slot of a PC-9800 series. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOSTTM. EMU-17K also has a function by which you can check the contents of data memory realtime. This is an SE board for µPD17215 sub-series. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K28CT is an emulation probe for 17K series 28-pin shrink DIP (400mil). IE-17K, IE-17K-ET Note 1, EMU-17K Note 2 SE Board (SE-17215) Emulation Probe (EP-17K28CT) Emulation Probe (EP-17K28GT) Conversion Adapter (EV-9500GT-28 Note 3) PROM Programmer (AF-9703 Note 4, AF-9704 Note 4, 5, AF-9706 Note 4) Program Adapter (AF-9808JNote 4, AF-9808H Note 4) EP-17K28GT is an emulation probe for 17K series 28-pin SOP (375 mil). When used with EV-9500GT-28 Note 3, it connects an SE board to the target system. EV-9500GT-28 is a conversion adapter for 28-pin SOP (375 mil) and is used to connect EP-17K28GT to the target system. AF-9703, AF-9704, and AF-9706 are PROM programmers corresponding to µPD17P218. By connecting program adapter AF-9808J or AF-9808H to this PROM programmer, µPD17P218 can be programmed. AF-9808J and AF-9808H are adapters that is used to program µPD17P218CT and µPD17P218GT respectively, and is used in combination with AF-9703, AF-9704, or AF-9706. Note 1: Low-cost model: External power supply type 2: This is a product from IC Corp. For details, consult IC Corp. 3: Two EV-9500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are optionally available as a set. 4: These are products from Ando Electric. For details, consult Ando Electric. 5: Maintenance product (This is no longer produced.) 27 µPD17P218 Software Name Outline Host Machine OS Media Supply 5" 2HD PC-9800 series MS-DOS TM Order Code 17K Series Assembler (AS17K) AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the µPD17P218, AS17K is used in combination with a device file (AS17215, AS17216, AS17217, or AS17218). µS5A10AS17K µS5A13AS17K µS7B10AS17K µS7B13AS17K µS5A10AS17215 Note µS5A13AS17215 Note µS7B10AS17215 Note µS7B13AS17215 Note 3.5" 2HD 5" 2HC IBM PC/AT PC DOS TM 3.5" 2HC 5" 2HD Device File AS17215 AS17216 AS17217 AS17218 AS17215, AS17216, AS17217, and AS17218 are device files for µPD17215, 17216, 17217, and 17218 respectirely, and are used in combination with an assembler for the 17K series (AS17K). PC-9800 series MS-DOS 3.5" 2HD 5" 2HC IBM PC/AT PC DOS 3.5" 2HC 5" 2HD SIMPLEHOST is a software package that enables manmachine interface on the WindowsTM when a program is developed by using an incircuit emulator and a personal computer. PC-9800 series MS-DOS 3.5" 2HD Windows 5" 2HC IBM PC/AT PC DOS 3.5" 2HC µS5A10IE17K µS5A13IE17K µS7B10IE17K µS7B13IE17K Support Software (SIMPLEHOST) Note: µS××××AS17215 includes AS17215, AS17216, AS17217, and AS17218. Remarks: The corresponding OS versions are as follows: OS MS-DOS PC DOS Windows Ver. 3.30 to Ver. 5.00A Version Note Ver. 3.1 to Ver. 5.0 Note Ver. 3.0 to Ver. 3.1 Note: Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software. 28 µPD17P218 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 29 µPD17P218 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 SIMPLEHOST is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.